blob: 0c653915bdf83d95e76fff1a4c2c1a1441603720 [file] [log] [blame]
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -04001/*
2 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
3 *
Hugo Villeneuve2b1fa9d2008-07-08 11:02:05 -04004 * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
5 * Copyright (C) 2008 Philip Balister, OpenSDR <philip@opensdr.com>
6 *
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -04007 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#ifndef __CONFIG_H
24#define __CONFIG_H
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -040025
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -040026/* Board */
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -040027#define SFFSDR
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020028#define CONFIG_SYS_NAND_LARGEPAGE
29#define CONFIG_SYS_USE_NAND
David Brownell7a4f5112009-05-15 23:47:12 +020030#define CONFIG_SYS_USE_DSPLINK /* don't power up the DSP. */
31#define CONFIG_DISPLAY_CPUINFO
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -040032/* SoC Configuration */
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -040033#define CONFIG_ARM926EJS /* arm926ejs CPU core */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020034#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
35#define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */
36#define CONFIG_SYS_HZ 1000
David Brownellf7904362009-05-15 23:44:08 +020037#define CONFIG_SOC_DM644X
Hugo Villeneuve2b1fa9d2008-07-08 11:02:05 -040038/* EEPROM definitions for Atmel 24LC64 EEPROM chip */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020039#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
40#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
41#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
42#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -040043/* Memory Info */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020044#define CONFIG_SYS_MALLOC_LEN (0x10000 + 256*1024) /* malloc() len */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020045#define CONFIG_SYS_MEMTEST_START 0x80000000 /* memtest start address */
46#define CONFIG_SYS_MEMTEST_END 0x81000000 /* 16MB RAM test */
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -040047#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
48#define CONFIG_STACKSIZE (256*1024) /* regular stack */
49#define PHYS_SDRAM_1 0x80000000 /* DDR Start */
50#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */
51#define DDR_4BANKS /* 4-bank DDR2 (128MB) */
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -040052/* Serial Driver info */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020053#define CONFIG_SYS_NS16550
54#define CONFIG_SYS_NS16550_SERIAL
David Brownell7ee38c02009-04-12 15:38:06 -070055#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size, byteorder */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020056#define CONFIG_SYS_NS16550_COM1 0x01c20000 /* Base address of UART0 */
David Brownell7239c5da2009-04-12 15:40:16 -070057#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK /* Input clock to NS16550 */
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -040058#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
59#define CONFIG_BAUDRATE 115200 /* Default baud rate */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020060#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -040061/* I2C Configuration */
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -040062#define CONFIG_HARD_I2C
63#define CONFIG_DRIVER_DAVINCI_I2C
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020064#define CONFIG_SYS_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */
65#define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -040066/* Network & Ethernet Configuration */
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -040067#define CONFIG_DRIVER_TI_EMAC
68#define CONFIG_MII
69#define CONFIG_BOOTP_DEFAULT
70#define CONFIG_BOOTP_DNS
71#define CONFIG_BOOTP_DNS2
72#define CONFIG_BOOTP_SEND_HOSTNAME
73#define CONFIG_NET_RETRY_COUNT 10
74#define CONFIG_OVERWRITE_ETHADDR_ONCE
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -040075/* Flash & Environment */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +020076#undef CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020077#define CONFIG_SYS_NO_FLASH
Jean-Christophe PLAGNIOL-VILLARDee4f3e22009-03-30 18:58:39 +020078#define CONFIG_NAND_DAVINCI
Nick Thompson97f4eb82009-12-12 12:12:26 -050079#define CONFIG_SYS_NAND_CS 2
Jean-Christophe PLAGNIOL-VILLARD51bfee12008-09-10 22:47:58 +020080#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020081#define CONFIG_ENV_SECT_SIZE 2048 /* Env sector Size */
Sandeep Paulraja16df2c2009-09-08 17:09:52 -040082#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -040083#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020084#define CONFIG_SYS_NAND_BASE 0x02000000
85#define CONFIG_SYS_NAND_HW_ECC
86#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020087#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
Hugo Villeneuve2b1fa9d2008-07-08 11:02:05 -040088/* I2C switch definitions for PCA9543 chip */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020089#define CONFIG_SYS_I2C_PCA9543_ADDR 0x70
90#define CONFIG_SYS_I2C_PCA9543_ADDR_LEN 0 /* Single register. */
91#define CONFIG_SYS_I2C_PCA9543_ENABLE_CH0 0x01 /* Enable channel 0. */
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -040092/* U-Boot general configuration */
Hugo Villeneuve2b1fa9d2008-07-08 11:02:05 -040093#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -040094#define CONFIG_MISC_INIT_R
Hugo Villeneuve2b1fa9d2008-07-08 11:02:05 -040095#define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds. */
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -040096#define CONFIG_BOOTFILE "uImage" /* Boot file name */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020097#define CONFIG_SYS_PROMPT "U-Boot > " /* Monitor Command Prompt */
98#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
99#define CONFIG_SYS_PBSIZE \
100 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print buffer size */
101#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
102#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
103#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* Default Linux kernel
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -0400104 * load address. */
105#define CONFIG_VERSION_VARIABLE
106#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far,
107 * may be later */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200108#define CONFIG_SYS_HUSH_PARSER
109#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -0400110#define CONFIG_CMDLINE_EDITING
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111#define CONFIG_SYS_LONGHELP
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -0400112#define CONFIG_CRC32_VERIFY
113#define CONFIG_MX_CYCLIC
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -0400114/* Linux Information */
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -0400115#define LINUX_BOOT_PARAM_ADDR 0x80000100
116#define CONFIG_CMDLINE_TAG
117#define CONFIG_SETUP_MEMORY_TAGS
Hugo Villeneuve2b1fa9d2008-07-08 11:02:05 -0400118#define CONFIG_BOOTARGS \
119 "mem=56M " \
120 "console=ttyS0,115200n8 " \
121 "root=/dev/nfs rw noinitrd ip=dhcp " \
122 "nfsroot=${serverip}:/nfsroot/sffsdr " \
123 "eth0=${ethaddr}"
124#define CONFIG_BOOTCOMMAND \
125 "nand read 87A00000 100000 300000;" \
126 "bootelf 87A00000"
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -0400127/* U-Boot commands */
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -0400128#include <config_cmd_default.h>
129#define CONFIG_CMD_ASKENV
130#define CONFIG_CMD_DHCP
131#define CONFIG_CMD_DIAG
132#define CONFIG_CMD_I2C
133#define CONFIG_CMD_MII
134#define CONFIG_CMD_PING
135#define CONFIG_CMD_SAVES
136#define CONFIG_CMD_NAND
137#define CONFIG_CMD_EEPROM
Hugo Villeneuvec15947d2008-07-10 10:46:33 -0400138#define CONFIG_CMD_ELF /* Needed to load Integrity kernel. */
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -0400139#undef CONFIG_CMD_BDI
140#undef CONFIG_CMD_FPGA
141#undef CONFIG_CMD_SETGETDCR
142#undef CONFIG_CMD_FLASH
143#undef CONFIG_CMD_IMLS
Sandeep Paulrajebc3c6c2010-12-11 20:38:12 -0500144
145#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */
146
147#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
148#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
149#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
150 CONFIG_SYS_INIT_RAM_SIZE - \
151 GENERATED_GBL_DATA_SIZE)
152
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -0400153#endif /* __CONFIG_H */