blob: 787704f409df02addb209781698985cb58d489d7 [file] [log] [blame]
wdenke69b4b82002-09-17 21:26:59 +00001/*
2 * (C) Copyright 2002 ELTEC Elektronik AG
3 * Frank Gottschling <fgottschling@eltec.de>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020026#if defined(CONFIG_SYS_L2_BAB7xx)
wdenke69b4b82002-09-17 21:26:59 +000027
28#include <pci.h>
29#include <mpc106.h>
Wolfgang Denk700a0c62005-08-08 01:03:24 +020030#include <asm/processor.h>
wdenke69b4b82002-09-17 21:26:59 +000031
32/* defines L2CR register for MPC750 */
33
34#define L2CR_E 0x80000000
35#define L2CR_256K 0x10000000
36#define L2CR_512K 0x20000000
37#define L2CR_1024K 0x30000000
38#define L2CR_I 0x00200000
39#define L2CR_SL 0x00008000
40#define L2CR_IP 0x00000001
41
42/*----------------------------------------------------------------------------*/
43
44static int dummy (int dummy)
45{
46 return (dummy+1);
47}
48
49/*----------------------------------------------------------------------------*/
50
51int l2_cache_enable (int l2control)
52{
53 if (l2control) /* BAB750 */
54 {
wdenk8bde7f72003-06-27 21:31:46 +000055 mtspr(SPRN_L2CR, l2control);
56 mtspr(SPRN_L2CR, (l2control | L2CR_I));
57 while (mfspr(SPRN_L2CR) & L2CR_IP)
58 ;
59 mtspr(SPRN_L2CR, (l2control | L2CR_E));
60 return (0);
wdenke69b4b82002-09-17 21:26:59 +000061 }
62 else /* BAB740 */
63 {
wdenk8bde7f72003-06-27 21:31:46 +000064 int picr1, picr2, mask;
65 int picr2CacheSize, cacheSize;
66 int *d;
67 int devbusfn;
68 u32 reg32;
wdenke69b4b82002-09-17 21:26:59 +000069
wdenk8bde7f72003-06-27 21:31:46 +000070 devbusfn = pci_find_device(PCI_VENDOR_ID_MOTOROLA,
71 PCI_DEVICE_ID_MOTOROLA_MPC106, 0);
72 if (devbusfn == -1)
73 return (-1);
wdenke69b4b82002-09-17 21:26:59 +000074
wdenk8bde7f72003-06-27 21:31:46 +000075 pci_read_config_dword (devbusfn, PCI_PICR2, &reg32);
76 reg32 &= ~PICR2_L2_EN;
77 pci_write_config_dword (devbusfn, PCI_PICR2, reg32);
wdenke69b4b82002-09-17 21:26:59 +000078
wdenk8bde7f72003-06-27 21:31:46 +000079 /* cache size */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020080 if (*(volatile unsigned char *) (CONFIG_SYS_ISA_IO + 0x220) & 0x04)
wdenk8bde7f72003-06-27 21:31:46 +000081 {
82 /* cache size is 512 KB */
83 picr2CacheSize = PICR2_L2_SIZE_512K;
84 cacheSize = 0x80000;
85 }
86 else
87 {
88 /* cache size is 256 KB */
89 picr2CacheSize = PICR2_L2_SIZE_256K;
90 cacheSize = 0x40000;
91 }
wdenke69b4b82002-09-17 21:26:59 +000092
wdenk8bde7f72003-06-27 21:31:46 +000093 /* setup PICR1 */
94 mask =
95 ~(PICR1_CF_BREAD_WS(1) |
96 PICR1_CF_BREAD_WS(2) |
97 PICR1_CF_CBA(0xff) |
98 PICR1_CF_CACHE_1G |
99 PICR1_CF_DPARK |
100 PICR1_CF_APARK |
101 PICR1_CF_L2_CACHE_MASK);
wdenke69b4b82002-09-17 21:26:59 +0000102
wdenk8bde7f72003-06-27 21:31:46 +0000103 picr1 =
104 (PICR1_CF_CBA(0x3f) |
105 PICR1_CF_CACHE_1G |
106 PICR1_CF_APARK |
107 PICR1_CF_DPARK |
108 PICR1_CF_L2_COPY_BACK); /* PICR1_CF_L2_WRITE_THROUGH */
wdenke69b4b82002-09-17 21:26:59 +0000109
wdenk8bde7f72003-06-27 21:31:46 +0000110 pci_read_config_dword (devbusfn, PCI_PICR1, &reg32);
111 reg32 &= mask;
112 reg32 |= picr1;
113 pci_write_config_dword (devbusfn, PCI_PICR1, reg32);
wdenke69b4b82002-09-17 21:26:59 +0000114
wdenk8bde7f72003-06-27 21:31:46 +0000115 /*
116 * invalidate all L2 cache
117 */
118 picr2 =
119 (PICR2_CF_INV_MODE |
120 PICR2_CF_HIT_HIGH |
121 PICR2_CF_MOD_HIGH |
122 PICR2_CF_L2_HIT_DELAY(1) |
123 PICR2_CF_APHASE_WS(1) |
124 picr2CacheSize);
wdenke69b4b82002-09-17 21:26:59 +0000125
wdenk8bde7f72003-06-27 21:31:46 +0000126 pci_write_config_dword (devbusfn, PCI_PICR2, picr2);
wdenke69b4b82002-09-17 21:26:59 +0000127
wdenk8bde7f72003-06-27 21:31:46 +0000128 /*
129 * dummy transactions
130 */
131 for (d=0; d<(int *)(2*cacheSize); d++)
132 dummy(*d);
wdenke69b4b82002-09-17 21:26:59 +0000133
wdenk8bde7f72003-06-27 21:31:46 +0000134 pci_write_config_dword (devbusfn, PCI_PICR2,
135 (picr2 | PICR2_CF_FLUSH_L2));
wdenke69b4b82002-09-17 21:26:59 +0000136
wdenk8bde7f72003-06-27 21:31:46 +0000137 /* setup PICR2 */
138 picr2 =
139 (PICR2_CF_FAST_CASTOUT |
140 PICR2_CF_WDATA |
141 PICR2_CF_ADDR_ONLY_DISABLE |
142 PICR2_CF_HIT_HIGH |
143 PICR2_CF_MOD_HIGH |
144 PICR2_L2_UPDATE_EN |
145 PICR2_L2_EN |
146 PICR2_CF_APHASE_WS(1) |
147 PICR2_CF_DATA_RAM_PBURST |
148 PICR2_CF_L2_HIT_DELAY(1) |
149 PICR2_CF_SNOOP_WS(2) |
150 picr2CacheSize);
wdenke69b4b82002-09-17 21:26:59 +0000151
wdenk8bde7f72003-06-27 21:31:46 +0000152 pci_write_config_dword (devbusfn, PCI_PICR2, picr2);
wdenke69b4b82002-09-17 21:26:59 +0000153 }
154 return (0);
155}
156
157/*----------------------------------------------------------------------------*/
158
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159#endif /* (CONFIG_SYS_L2_BAB7xx) */