| Li Yang | 14aa71e | 2011-07-26 09:50:46 -0500 | [diff] [blame^] | 1 | Overview |
| 2 | -------- |
| 3 | P1_P2_RDB_PC represents a set of boards including |
| 4 | P1020MSBG-PC |
| 5 | P1020RDB-PC |
| 6 | P1020UTM-PC |
| 7 | P1021RDB-PC |
| 8 | P1024RDB |
| 9 | P1025RDB |
| 10 | P2020RDB-PC |
| 11 | |
| 12 | They have similar design of P1020RDB but have DDR3 instead of DDR2. P2020RDB-PC |
| 13 | has 64-bit DDR. All others have 32-bit DDR. |
| 14 | |
| 15 | Key features on these boards include: |
| 16 | * DDR3 |
| 17 | * NOR flash |
| 18 | * NAND flash (on RDB's only) |
| 19 | * SPI flash (on RDB's only) |
| 20 | * SDHC/MMC card slot |
| 21 | * VSC7385 Ethernet switch (on P1020MBG, P1020RDB, & P1021RDB) |
| 22 | * PCIE slot and mini-PCIE slots |
| 23 | |
| 24 | As these boards use soldered DDR chips not regular DIMMs, an on-board EEPROM |
| 25 | is used to store SPD data. In case of absent or corrupted SPD, falling back |
| 26 | to timing data embedded in the source code will be used. Raw timing data is |
| 27 | extracted from DDR chip datasheet. Different speeds of DDR are supported with |
| 28 | this approach. ODT option is forced to fit this set of boards, again because |
| 29 | they don't have regular DIMMs. |
| 30 | |
| 31 | CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS is defined as 5ms to meet specification |
| 32 | for writing timing. |
| 33 | |
| 34 | VSC firmware Address is defined by default in config file for eTSEC1. |
| 35 | |
| 36 | SD width is based off DIP switch. DIP switch is detected on the |
| 37 | board by reading i2c bus and setting the appropriate mux values. |
| 38 | |
| 39 | Some boards have QE module in the silicon (P1021 and P1025). QE and eLBC have |
| 40 | pins multiplexing. QE function needs to be disabled to access Nor Flash and |
| 41 | CPLD. QE-UEC and QE-UART can be enabled for linux kernel by setting "qe" |
| 42 | in hwconfig. In addition, QE-UEC and QE-TDM also have pins multiplexing, to |
| 43 | enable QE-TDM for linux kernel, set "qe;tdm" in hwconfig. Syntax is as below |
| 44 | |
| 45 | 'setenv hwconfig qe' to enable QE UEC/UART and disable Nor-Flash/CPLD. |
| 46 | 'setenv hwconfig 'qe;tdm'' to enalbe QE TDM and disable Nor-Flash/CPLD. |