blob: 49f200aa0b3df7c016ba1d7932632b1f76e695b4 [file] [log] [blame]
Stefan Roese17f50f222005-08-04 17:09:16 +02001/*
2 * (C) Copyright 2005
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
Stefan Roese17f50f222005-08-04 17:09:16 +02006 */
7
8/*----------------------------------------------------------------------------+
9 | FPGA registers and bit definitions
10 +----------------------------------------------------------------------------*/
11/*
12 * PowerPC 440EP Board FPGA is reached with physical address 0x80001FF0.
13 * TLB initialization makes it correspond to logical address 0x80001FF0.
14 * => Done init_chip.s in bootlib
15 */
Wolfgang Denkf901a832005-08-06 01:42:58 +020016#define FPGA_BASE_ADDR 0x80002000
Stefan Roese17f50f222005-08-04 17:09:16 +020017
18/*----------------------------------------------------------------------------+
19 | Board Jumpers Setting Register
20 | Board Settings provided by jumpers
21 +----------------------------------------------------------------------------*/
Wolfgang Denkf901a832005-08-06 01:42:58 +020022#define FPGA_SETTING_REG (FPGA_BASE_ADDR+0x3)
Stefan Roese17f50f222005-08-04 17:09:16 +020023/* Boot from small flash */
Wolfgang Denkf901a832005-08-06 01:42:58 +020024#define FPGA_SET_REG_BOOT_SMALL_FLASH 0x80
Stefan Roese17f50f222005-08-04 17:09:16 +020025/* Operational Flash versus SRAM position in Memory Map */
Wolfgang Denkf901a832005-08-06 01:42:58 +020026#define FPGA_SET_REG_OP_CODE_SRAM_SEL_MASK 0x40
27#define FPGA_SET_REG_OP_CODE_FLASH_ABOVE 0x40
28#define FPGA_SET_REG_SRAM_ABOVE 0x00
Stefan Roese17f50f222005-08-04 17:09:16 +020029/* Boot From NAND Flash */
Wolfgang Denkf901a832005-08-06 01:42:58 +020030#define FPGA_SET_REG_BOOT_NAND_FLASH_MASK 0x40
31#define FPGA_SET_REG_BOOT_NAND_FLASH_SELECT 0x00
Stefan Roese17f50f222005-08-04 17:09:16 +020032/* On Board PCI Arbiter Select */
Wolfgang Denkf901a832005-08-06 01:42:58 +020033#define FPGA_SET_REG_PCI_EXT_ARBITER_SEL_MASK 0x10
34#define FPGA_SET_REG_PCI_EXT_ARBITER_SEL 0x00
Stefan Roese17f50f222005-08-04 17:09:16 +020035
36/*----------------------------------------------------------------------------+
37 | Functions Selection Register 1
38 +----------------------------------------------------------------------------*/
Wolfgang Denkf901a832005-08-06 01:42:58 +020039#define FPGA_SELECTION_1_REG (FPGA_BASE_ADDR+0x4)
40#define FPGA_SEL_1_REG_PHY_MASK 0xE0
41#define FPGA_SEL_1_REG_MII 0x80
42#define FPGA_SEL_1_REG_RMII 0x40
43#define FPGA_SEL_1_REG_SMII 0x20
44#define FPGA_SEL_1_REG_USB2_DEV_SEL 0x10 /* USB2 Device Selection */
45#define FPGA_SEL_1_REG_USB2_HOST_SEL 0x08 /* USB2 Host Selection */
46#define FPGA_SEL_1_REG_NF_SELEC_MASK 0x07 /* NF Selection Mask */
47#define FPGA_SEL_1_REG_NF0_SEL_BY_NFCS1 0x04 /* NF0 Selected by NF_CS1 */
48#define FPGA_SEL_1_REG_NF1_SEL_BY_NFCS2 0x02 /* NF1 Selected by NF_CS2 */
49#define FPGA_SEL_1_REG_NF1_SEL_BY_NFCS3 0x01 /* NF1 Selected by NF_CS3 */
Stefan Roese17f50f222005-08-04 17:09:16 +020050
51/*----------------------------------------------------------------------------+
52 | Functions Selection Register 2
53 +----------------------------------------------------------------------------*/
Wolfgang Denkf901a832005-08-06 01:42:58 +020054#define FPGA_SELECTION_2_REG (FPGA_BASE_ADDR+0x5)
55#define FPGA_SEL2_REG_IIC1_SCP_SEL_MASK 0x80 /* IIC1 / SCP Selection */
56#define FPGA_SEL2_REG_SEL_FRAM 0x80 /* FRAM on IIC1 bus selected - SCP Select */
57#define FPGA_SEL2_REG_SEL_SCP 0x80 /* Identical to SCP Selection */
58#define FPGA_SEL2_REG_SEL_IIC1 0x00 /* IIC1 Selection - Default Value */
59#define FPGA_SEL2_REG_SEL_DMA_A_B 0x40 /* DMA A & B channels selected */
60#define FPGA_SEL2_REG_SEL_DMA_C_D 0x20 /* DMA C & D channels selected */
61#define FPGA_SEL2_REG_DMA_EOT_TC_3_SEL 0x10 /* 0 = EOT - input to 440EP */
62 /* 1 = TC - output from 440EP */
63#define FPGA_SEL2_REG_DMA_EOT_TC_2_SEL 0x08 /* 0 = EOT (input to 440EP) */
64 /* 1 = TC (output from 440EP) */
65#define FPGA_SEL2_REG_SEL_GPIO_1 0x04 /* EBC_GPIO & USB2_GPIO selected */
66#define FPGA_SEL2_REG_SEL_GPIO_2 0x02 /* Ether._GPIO & UART_GPIO selected */
67#define FPGA_SEL2_REG_SEL_GPIO_3 0x01 /* DMA_GPIO & Trace_GPIO selected */
Stefan Roese17f50f222005-08-04 17:09:16 +020068
69/*----------------------------------------------------------------------------+
70 | Functions Selection Register 3
71 +----------------------------------------------------------------------------*/
Wolfgang Denkf901a832005-08-06 01:42:58 +020072#define FPGA_SELECTION_3_REG (FPGA_BASE_ADDR+0x6)
73#define FPGA_SEL3_REG_EXP_SLOT_EN 0x80 /* Expansion Slot enabled */
74#define FPGA_SEL3_REG_SEL_UART_CONFIG_MASK 0x70
75#define FPGA_SEL3_REG_SEL_UART_CONFIG1 0x40 /* one 8_pin UART */
76#define FPGA_SEL3_REG_SEL_UART_CONFIG2 0x20 /* two 4_pin UARTs */
77#define FPGA_SEL3_REG_SEL_UART_CONFIG3 0x10 /* one 4_pin & two 2_pin UARTs */
78#define FPGA_SEL3_REG_SEL_UART_CONFIG4 0x08 /* four 2_pin UARTs */
79#define FPGA_SEL3_REG_DTR_DSR_MODE_4_PIN_UART 0x00 /* DTR/DSR mode for 4_pin_UART */
80#define FPGA_SEL3_REG_RTS_CTS_MODE_4_PIN_UART 0x04 /* RTS/CTS mode for 4_pin_UART */
Stefan Roese17f50f222005-08-04 17:09:16 +020081
82/*----------------------------------------------------------------------------+
83 | Soft Reset Register
84 +----------------------------------------------------------------------------*/
Wolfgang Denkf901a832005-08-06 01:42:58 +020085#define FPGA_RESET_REG (FPGA_BASE_ADDR+0x7)
86#define FPGA_RESET_REG_RESET_USB20_DEV 0x80 /* Hard Reset of the GT3200 */
87#define FPGA_RESET_REG_RESET_DISPLAY 0x40 /* Hard Reset on Display Device */
88#define FPGA_RESET_REG_STATUS_LED_0 0x08 /* 1 = Led On */
89#define FPGA_RESET_REG_STATUS_LED_1 0x04 /* 1 = Led On */
90#define FPGA_RESET_REG_STATUS_LED_2 0x02 /* 1 = Led On */
91#define FPGA_RESET_REG_STATUS_LED_3 0x01 /* 1 = Led On */
Stefan Roese17f50f222005-08-04 17:09:16 +020092
93
94/*----------------------------------------------------------------------------+
95| SDR Configuration registers
96+----------------------------------------------------------------------------*/
Wolfgang Denkf901a832005-08-06 01:42:58 +020097#define SDR0_SDSTP1_EBC_ROM_BS_MASK 0x00006000 /* EBC Boot Size Mask */
98#define SDR0_SDSTP1_EBC_ROM_BS_32BIT 0x00004000 /* EBC 32 bits */
99#define SDR0_SDSTP1_EBC_ROM_BS_16BIT 0x00002000 /* EBC 16 Bits */
100#define SDR0_SDSTP1_EBC_ROM_BS_8BIT 0x00000000 /* EBC 8 Bits */
Stefan Roese17f50f222005-08-04 17:09:16 +0200101
Wolfgang Denkf901a832005-08-06 01:42:58 +0200102#define SDR0_SDSTP1_BOOT_SEL_MASK 0x00001800 /* Boot device Selection Mask */
103#define SDR0_SDSTP1_BOOT_SEL_EBC 0x00000000 /* EBC */
104#define SDR0_SDSTP1_BOOT_SEL_PCI 0x00000800 /* PCI */
105#define SDR0_SDSTP1_BOOT_SEL_NDFC 0x00001000 /* NDFC */
Stefan Roese17f50f222005-08-04 17:09:16 +0200106
107/* Serial Device Enabled - Addr = 0xA8 */
108#define SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS5
109/* Serial Device Enabled - Addr = 0xA4 */
110#define SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS7
111
112/* Pin Straps Reg */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200113#define SDR0_PSTRP0 0x0040
114#define SDR0_PSTRP0_BOOTSTRAP_MASK 0xE0000000 /* Strap Bits */
Stefan Roese17f50f222005-08-04 17:09:16 +0200115
116#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS0 0x00000000 /* Default strap settings 0 */
117#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS1 0x20000000 /* Default strap settings 1 */
118#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS2 0x40000000 /* Default strap settings 2 */
119#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS3 0x60000000 /* Default strap settings 3 */
120#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS4 0x80000000 /* Default strap settings 4 */
121#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS5 0xA0000000 /* Default strap settings 5 */
122#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS6 0xC0000000 /* Default strap settings 6 */
123#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS7 0xE0000000 /* Default strap settings 7 */
124
125/*----------------------------------------------------------------------------+
126| EBC Configuration Register - EBC0_CFG
127+----------------------------------------------------------------------------*/
128/* External Bus Three-State Control */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200129#define EBC0_CFG_EBTC_DRIVEN 0x80000000
Stefan Roese17f50f222005-08-04 17:09:16 +0200130/* Device-Paced Time-out Disable */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200131#define EBC0_CFG_PTD_ENABLED 0x00000000
Stefan Roese17f50f222005-08-04 17:09:16 +0200132/* Ready Timeout Count */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200133#define EBC0_CFG_RTC_MASK 0x38000000
134#define EBC0_CFG_RTC_16PERCLK 0x00000000
135#define EBC0_CFG_RTC_32PERCLK 0x08000000
136#define EBC0_CFG_RTC_64PERCLK 0x10000000
137#define EBC0_CFG_RTC_128PERCLK 0x18000000
138#define EBC0_CFG_RTC_256PERCLK 0x20000000
139#define EBC0_CFG_RTC_512PERCLK 0x28000000
140#define EBC0_CFG_RTC_1024PERCLK 0x30000000
141#define EBC0_CFG_RTC_2048PERCLK 0x38000000
Stefan Roese17f50f222005-08-04 17:09:16 +0200142/* External Master Priority Low */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200143#define EBC0_CFG_EMPL_LOW 0x00000000
Stefan Roese17f50f222005-08-04 17:09:16 +0200144#define EBC0_CFG_EMPL_MEDIUM_LOW 0x02000000
145#define EBC0_CFG_EMPL_MEDIUM_HIGH 0x04000000
Wolfgang Denkf901a832005-08-06 01:42:58 +0200146#define EBC0_CFG_EMPL_HIGH 0x06000000
Stefan Roese17f50f222005-08-04 17:09:16 +0200147/* External Master Priority High */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200148#define EBC0_CFG_EMPH_LOW 0x00000000
Stefan Roese17f50f222005-08-04 17:09:16 +0200149#define EBC0_CFG_EMPH_MEDIUM_LOW 0x00800000
150#define EBC0_CFG_EMPH_MEDIUM_HIGH 0x01000000
Wolfgang Denkf901a832005-08-06 01:42:58 +0200151#define EBC0_CFG_EMPH_HIGH 0x01800000
Stefan Roese17f50f222005-08-04 17:09:16 +0200152/* Chip Select Three-State Control */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200153#define EBC0_CFG_CSTC_DRIVEN 0x00400000
Stefan Roese17f50f222005-08-04 17:09:16 +0200154/* Burst Prefetch */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200155#define EBC0_CFG_BPF_ONEDW 0x00000000
156#define EBC0_CFG_BPF_TWODW 0x00100000
157#define EBC0_CFG_BPF_FOURDW 0x00200000
Stefan Roese17f50f222005-08-04 17:09:16 +0200158/* External Master Size */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200159#define EBC0_CFG_EMS_8BIT 0x00000000
Stefan Roese17f50f222005-08-04 17:09:16 +0200160/* Power Management Enable */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200161#define EBC0_CFG_PME_DISABLED 0x00000000
162#define EBC0_CFG_PME_ENABLED 0x00020000
Stefan Roese17f50f222005-08-04 17:09:16 +0200163/* Power Management Timer */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200164#define EBC0_CFG_PMT_ENCODE(n) ((((unsigned long)(n))&0x1F)<<12)
Stefan Roese17f50f222005-08-04 17:09:16 +0200165
166/*----------------------------------------------------------------------------+
167| Peripheral Bank Configuration Register - EBC0_BnCR
168+----------------------------------------------------------------------------*/
169/* BAS - Base Address Select */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200170#define EBC0_BNCR_BAS_ENCODE(n) ((((unsigned long)(n))&0xFFF00000)<<0)
Stefan Roese17f50f222005-08-04 17:09:16 +0200171/* BS - Bank Size */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200172#define EBC0_BNCR_BS_MASK 0x000E0000
173#define EBC0_BNCR_BS_1MB 0x00000000
174#define EBC0_BNCR_BS_2MB 0x00020000
175#define EBC0_BNCR_BS_4MB 0x00040000
176#define EBC0_BNCR_BS_8MB 0x00060000
177#define EBC0_BNCR_BS_16MB 0x00080000
178#define EBC0_BNCR_BS_32MB 0x000A0000
179#define EBC0_BNCR_BS_64MB 0x000C0000
180#define EBC0_BNCR_BS_128MB 0x000E0000
Stefan Roese17f50f222005-08-04 17:09:16 +0200181/* BU - Bank Usage */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200182#define EBC0_BNCR_BU_MASK 0x00018000
183#define EBC0_BNCR_BU_RO 0x00008000
184#define EBC0_BNCR_BU_WO 0x00010000
185#define EBC0_BNCR_BU_RW 0x00018000
Stefan Roese17f50f222005-08-04 17:09:16 +0200186/* BW - Bus Width */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200187#define EBC0_BNCR_BW_MASK 0x00006000
188#define EBC0_BNCR_BW_8BIT 0x00000000
189#define EBC0_BNCR_BW_16BIT 0x00002000
190#define EBC0_BNCR_BW_32BIT 0x00004000
Stefan Roese17f50f222005-08-04 17:09:16 +0200191
192/*----------------------------------------------------------------------------+
193| Peripheral Bank Access Parameters - EBC0_BnAP
194+----------------------------------------------------------------------------*/
195/* Burst Mode Enable */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200196#define EBC0_BNAP_BME_ENABLED 0x80000000
197#define EBC0_BNAP_BME_DISABLED 0x00000000
Stefan Roese17f50f222005-08-04 17:09:16 +0200198/* Transfert Wait */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200199#define EBC0_BNAP_TWT_ENCODE(n) ((((unsigned long)(n))&0xFF)<<23) /* Bits 1:8 */
Stefan Roese17f50f222005-08-04 17:09:16 +0200200/* Chip Select On Timing */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200201#define EBC0_BNAP_CSN_ENCODE(n) ((((unsigned long)(n))&0x3)<<18) /* Bits 12:13 */
Stefan Roese17f50f222005-08-04 17:09:16 +0200202/* Output Enable On Timing */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200203#define EBC0_BNAP_OEN_ENCODE(n) ((((unsigned long)(n))&0x3)<<16) /* Bits 14:15 */
Stefan Roese17f50f222005-08-04 17:09:16 +0200204/* Write Back Enable On Timing */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200205#define EBC0_BNAP_WBN_ENCODE(n) ((((unsigned long)(n))&0x3)<<14) /* Bits 16:17 */
Stefan Roese17f50f222005-08-04 17:09:16 +0200206/* Write Back Enable Off Timing */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200207#define EBC0_BNAP_WBF_ENCODE(n) ((((unsigned long)(n))&0x3)<<12) /* Bits 18:19 */
Stefan Roese17f50f222005-08-04 17:09:16 +0200208/* Transfert Hold */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200209#define EBC0_BNAP_TH_ENCODE(n) ((((unsigned long)(n))&0x7)<<9) /* Bits 20:22 */
Stefan Roese17f50f222005-08-04 17:09:16 +0200210/* PerReady Enable */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200211#define EBC0_BNAP_RE_ENABLED 0x00000100
212#define EBC0_BNAP_RE_DISABLED 0x00000000
Stefan Roese17f50f222005-08-04 17:09:16 +0200213/* Sample On Ready */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200214#define EBC0_BNAP_SOR_DELAYED 0x00000000
Stefan Roese17f50f222005-08-04 17:09:16 +0200215#define EBC0_BNAP_SOR_NOT_DELAYED 0x00000080
216/* Byte Enable Mode */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200217#define EBC0_BNAP_BEM_WRITEONLY 0x00000000
218#define EBC0_BNAP_BEM_RW 0x00000040
Stefan Roese17f50f222005-08-04 17:09:16 +0200219/* Parity Enable */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200220#define EBC0_BNAP_PEN_DISABLED 0x00000000
221#define EBC0_BNAP_PEN_ENABLED 0x00000020
Stefan Roese17f50f222005-08-04 17:09:16 +0200222
223/*----------------------------------------------------------------------------+
224| Define Boot devices
225+----------------------------------------------------------------------------*/
226/* */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200227#define BOOT_FROM_SMALL_FLASH 0x00
228#define BOOT_FROM_LARGE_FLASH_OR_SRAM 0x01
229#define BOOT_FROM_NAND_FLASH0 0x02
230#define BOOT_FROM_PCI 0x03
231#define BOOT_DEVICE_UNKNOWN 0x04
Stefan Roese17f50f222005-08-04 17:09:16 +0200232
233
Wolfgang Denkf901a832005-08-06 01:42:58 +0200234#define PVR_POWERPC_440EP_PASS1 0x42221850
235#define PVR_POWERPC_440EP_PASS2 0x422218D3
Stefan Roese17f50f222005-08-04 17:09:16 +0200236
Wolfgang Denkf901a832005-08-06 01:42:58 +0200237#define GPIO0 0
238#define GPIO1 1
Stefan Roese17f50f222005-08-04 17:09:16 +0200239
Wolfgang Denkf901a832005-08-06 01:42:58 +0200240/*#define MAX_SELECTION_NB CORE_NB */
241#define MAX_CORE_SELECT_NB 22
Stefan Roese17f50f222005-08-04 17:09:16 +0200242
243/*----------------------------------------------------------------------------+
244 | PPC440EP GPIOs addresses.
245 +----------------------------------------------------------------------------*/
Wolfgang Denkf901a832005-08-06 01:42:58 +0200246#define GPIO0_REAL 0xEF600B00
Stefan Roese17f50f222005-08-04 17:09:16 +0200247
Wolfgang Denkf901a832005-08-06 01:42:58 +0200248#define GPIO1_REAL 0xEF600C00
Stefan Roese17f50f222005-08-04 17:09:16 +0200249
250/* Offsets */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200251#define GPIOx_OR 0x00 /* GPIO Output Register */
252#define GPIOx_TCR 0x04 /* GPIO Three-State Control Register */
253#define GPIOx_OSL 0x08 /* GPIO Output Select Register (Bits 0-31) */
254#define GPIOx_OSH 0x0C /* GPIO Ouput Select Register (Bits 32-63) */
255#define GPIOx_TSL 0x10 /* GPIO Three-State Select Register (Bits 0-31) */
256#define GPIOx_TSH 0x14 /* GPIO Three-State Select Register (Bits 32-63) */
257#define GPIOx_ODR 0x18 /* GPIO Open drain Register */
258#define GPIOx_IR 0x1C /* GPIO Input Register */
259#define GPIOx_RR1 0x20 /* GPIO Receive Register 1 */
260#define GPIOx_RR2 0x24 /* GPIO Receive Register 2 */
261#define GPIOx_RR3 0x28 /* GPIO Receive Register 3 */
262#define GPIOx_IS1L 0x30 /* GPIO Input Select Register 1 (Bits 0-31) */
263#define GPIOx_IS1H 0x34 /* GPIO Input Select Register 1 (Bits 32-63) */
264#define GPIOx_IS2L 0x38 /* GPIO Input Select Register 2 (Bits 0-31) */
265#define GPIOx_IS2H 0x3C /* GPIO Input Select Register 2 (Bits 32-63) */
266#define GPIOx_IS3L 0x40 /* GPIO Input Select Register 3 (Bits 0-31) */
267#define GPIOx_IS3H 0x44 /* GPIO Input Select Register 3 (Bits 32-63) */
Stefan Roese17f50f222005-08-04 17:09:16 +0200268
269/* GPIO0 */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200270#define GPIO0_IS1L (GPIO0_BASE+GPIOx_IS1L)
271#define GPIO0_IS1H (GPIO0_BASE+GPIOx_IS1H)
272#define GPIO0_IS2L (GPIO0_BASE+GPIOx_IS2L)
273#define GPIO0_IS2H (GPIO0_BASE+GPIOx_IS2H)
274#define GPIO0_IS3L (GPIO0_BASE+GPIOx_IS3L)
275#define GPIO0_IS3H (GPIO0_BASE+GPIOx_IS3L)
Stefan Roese17f50f222005-08-04 17:09:16 +0200276
277/* GPIO1 */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200278#define GPIO1_IS1L (GPIO1_BASE+GPIOx_IS1L)
279#define GPIO1_IS1H (GPIO1_BASE+GPIOx_IS1H)
280#define GPIO1_IS2L (GPIO1_BASE+GPIOx_IS2L)
281#define GPIO1_IS2H (GPIO1_BASE+GPIOx_IS2H)
282#define GPIO1_IS3L (GPIO1_BASE+GPIOx_IS3L)
283#define GPIO1_IS3H (GPIO1_BASE+GPIOx_IS3L)
Stefan Roese17f50f222005-08-04 17:09:16 +0200284
Wolfgang Denkf901a832005-08-06 01:42:58 +0200285#define GPIO_OS(x) (x+GPIOx_OSL) /* GPIO Output Register High or Low */
286#define GPIO_TS(x) (x+GPIOx_TSL) /* GPIO Three-state Control Reg High or Low */
287#define GPIO_IS1(x) (x+GPIOx_IS1L) /* GPIO Input register1 High or Low */
288#define GPIO_IS2(x) (x+GPIOx_IS2L) /* GPIO Input register2 High or Low */
289#define GPIO_IS3(x) (x+GPIOx_IS3L) /* GPIO Input register3 High or Low */
Stefan Roese17f50f222005-08-04 17:09:16 +0200290
291
292/*----------------------------------------------------------------------------+
Wolfgang Denkf901a832005-08-06 01:42:58 +0200293 | XX XX
Stefan Roese17f50f222005-08-04 17:09:16 +0200294 |
295 | XXXXXX XXX XX XXX XXX
Wolfgang Denkf901a832005-08-06 01:42:58 +0200296 | XX XX X XX XX XX
297 | XX XX X XX XX XX
298 | XX XX XX XX XX
Stefan Roese17f50f222005-08-04 17:09:16 +0200299 | XXXXXX XXX XXX XXXX XXXX
300 +----------------------------------------------------------------------------*/
301/*----------------------------------------------------------------------------+
302 | Defines
303 +----------------------------------------------------------------------------*/
304typedef enum zmii_config { ZMII_CONFIGURATION_UNKNOWN,
Wolfgang Denkf901a832005-08-06 01:42:58 +0200305 ZMII_CONFIGURATION_IS_MII,
306 ZMII_CONFIGURATION_IS_RMII,
307 ZMII_CONFIGURATION_IS_SMII
Stefan Roese17f50f222005-08-04 17:09:16 +0200308} zmii_config_t;
309
310/*----------------------------------------------------------------------------+
311 | Declare Configuration values
312 +----------------------------------------------------------------------------*/
313typedef enum uart_config_nb { L1, L2, L3, L4 } uart_config_nb_t;
314typedef enum core_selection { CORE_NOT_SELECTED, CORE_SELECTED} core_selection_t;
315typedef enum config_list { IIC_CORE,
Wolfgang Denkf901a832005-08-06 01:42:58 +0200316 SCP_CORE,
317 DMA_CHANNEL_AB,
318 UIC_4_9,
319 USB2_HOST,
320 DMA_CHANNEL_CD,
321 USB2_DEVICE,
322 PACKET_REJ_FUNC_AVAIL,
323 USB1_DEVICE,
324 EBC_MASTER,
325 NAND_FLASH,
326 UART_CORE0,
327 UART_CORE1,
328 UART_CORE2,
329 UART_CORE3,
330 MII_SEL,
331 RMII_SEL,
332 SMII_SEL,
333 PACKET_REJ_FUNC_EN,
334 UIC_0_3,
335 USB1_HOST,
336 PCI_PATCH,
337 CORE_NB
Stefan Roese17f50f222005-08-04 17:09:16 +0200338} core_list_t;
339
340typedef enum block3_value { B3_V1, B3_V2, B3_V3, B3_V4, B3_V5,
Wolfgang Denkf901a832005-08-06 01:42:58 +0200341 B3_V6, B3_V7, B3_V8, B3_V9, B3_V10,
342 B3_V11, B3_V12, B3_V13, B3_V14, B3_V15,
343 B3_V16, B3_VALUE_UNKNOWN
Stefan Roese17f50f222005-08-04 17:09:16 +0200344} block3_value_t;
345
346typedef enum config_validity { CONFIG_IS_VALID,
Wolfgang Denkf901a832005-08-06 01:42:58 +0200347 CONFIG_IS_INVALID
Stefan Roese17f50f222005-08-04 17:09:16 +0200348} config_validity_t;