blob: 6798e80985d63a4b1e70d6b48a2a0be09130506e [file] [log] [blame]
Stefan Roeseb765ffb2007-06-15 08:18:01 +02001/*
2 * (C) Copyright 2007
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#include <ppc_asm.tmpl>
27#include <config.h>
28#include <asm-ppc/mmu.h>
29
30/**************************************************************************
31 * TLB TABLE
32 *
33 * This table is used by the cpu boot code to setup the initial tlb
34 * entries. Rather than make broad assumptions in the cpu source tree,
35 * this table lets each board set things up however they like.
36 *
37 * Pointer to the table is returned in r1
38 *
39 *************************************************************************/
40 .section .bootpg,"ax"
41 .globl tlbtab
42
43tlbtab:
44 tlbtab_start
45
46 /*
47 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
48 * speed up boot process. It is patched after relocation to enable SA_I
49 */
50 tlbentry(CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G)
51
52 /*
53 * TLB entries for SDRAM are not needed on this platform.
54 * They are dynamically generated in the SPD DDR(2) detection
55 * routine.
56 */
57
58#ifdef CFG_INIT_RAM_DCACHE
59 /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
60 tlbentry(CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
61#endif
62
63 /* TLB-entry for PCI Memory */
64 tlbentry(CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I)
65 tlbentry(CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I)
66 tlbentry(CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I)
67 tlbentry(CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I)
68
69 /* TLB-entry for the FPGA Chip select 2 */
70 tlbentry(CFG_FPGA_BASE_0, SZ_1M, CFG_FPGA_BASE_0, 1, AC_R|AC_W|AC_X|SA_I|SA_G)
71
72 /* TLB-entry for the FPGA Chip select 3 */
73 tlbentry(CFG_FPGA_BASE_1, SZ_1M, CFG_FPGA_BASE_1, 1,AC_R|AC_W|AC_X|SA_I|SA_G)
74
75 /* TLB-entry for the LIME Controller */
76 tlbentry(CFG_LIME_BASE_0, SZ_16M, CFG_LIME_BASE_0, 1, AC_R|AC_W|AC_X|SA_I|SA_G)
77 tlbentry(CFG_LIME_BASE_1, SZ_16M, CFG_LIME_BASE_1, 1, AC_R|AC_W|AC_X|SA_I|SA_G)
78 tlbentry(CFG_LIME_BASE_2, SZ_16M, CFG_LIME_BASE_2, 1, AC_R|AC_W|AC_X|SA_I|SA_G)
79 tlbentry(CFG_LIME_BASE_3, SZ_16M, CFG_LIME_BASE_3, 1, AC_R|AC_W|AC_X|SA_I|SA_G)
80
81 /* TLB-entry for Internal Registers & OCM */
82 tlbentry(0xe0000000, SZ_16M, 0xe0000000, 0, AC_R|AC_W|AC_X|SA_I)
83
84 /*TLB-entry PCI registers*/
85 tlbentry(0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
86
87 /* TLB-entry for peripherals */
88 tlbentry(0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
89
90 tlbtab_end