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wdenkb4676a22003-12-07 19:24:00 +00001/*
2 * GNU General Public License for more details.
3 *
4 * MATRIX Vision GmbH / June 2002-Nov 2003
5 * Andre Schwarz
6 */
7
8#include <common.h>
9#include <mpc824x.h>
10#include <asm/io.h>
11#include <ns16550.h>
12
13#ifdef CONFIG_PCI
wdenkd4ca31c2004-01-02 14:00:00 +000014#include <pci.h>
wdenkb4676a22003-12-07 19:24:00 +000015#endif
16
Wolfgang Denkd87080b2006-03-31 18:32:53 +020017DECLARE_GLOBAL_DATA_PTR;
18
wdenkd4ca31c2004-01-02 14:00:00 +000019u32 get_BoardType (void);
wdenkb4676a22003-12-07 19:24:00 +000020
21#define PCI_CONFIG(b,d,f,r) cpu_to_le32(0x80000000 | ((b&0xff)<<16) \
wdenkd4ca31c2004-01-02 14:00:00 +000022 | ((d&0x1f)<<11) \
23 | ((f&0x7)<<7) \
24 | (r&0xfc) )
wdenkb4676a22003-12-07 19:24:00 +000025
wdenkd4ca31c2004-01-02 14:00:00 +000026int mv_pci_read (int bus, int dev, int func, int reg)
wdenkb4676a22003-12-07 19:24:00 +000027{
wdenkd4ca31c2004-01-02 14:00:00 +000028 *(u32 *) (0xfec00cf8) = PCI_CONFIG (bus, dev, func, reg);
29 asm ("sync");
30 return cpu_to_le32 (*(u32 *) (0xfee00cfc));
wdenkb4676a22003-12-07 19:24:00 +000031}
32
wdenkd4ca31c2004-01-02 14:00:00 +000033u32 get_BoardType ()
wdenkb4676a22003-12-07 19:24:00 +000034{
wdenkd4ca31c2004-01-02 14:00:00 +000035 return (mv_pci_read (0, 0xe, 0, 0) == 0x06801095 ? 0 : 1);
36}
37
38void init_2nd_DUART (void)
39{
40 NS16550_t console = (NS16550_t) CFG_NS16550_COM2;
wdenkb4676a22003-12-07 19:24:00 +000041 int clock_divisor = CFG_NS16550_CLK / 16 / CONFIG_BAUDRATE;
wdenkd4ca31c2004-01-02 14:00:00 +000042
43 *(u8 *) (0xfc004511) = 0x1;
44 NS16550_init (console, clock_divisor);
wdenkb4676a22003-12-07 19:24:00 +000045}
wdenkd4ca31c2004-01-02 14:00:00 +000046void hw_watchdog_reset (void)
wdenkb4676a22003-12-07 19:24:00 +000047{
wdenkd4ca31c2004-01-02 14:00:00 +000048 if (get_BoardType () == 0) {
49 *(u32 *) (0xff000005) = 0;
50 asm ("sync");
wdenkb4676a22003-12-07 19:24:00 +000051 }
52}
53int checkboard (void)
54{
wdenkd4ca31c2004-01-02 14:00:00 +000055 ulong busfreq = get_bus_freq (0);
56 char buf[32];
57 u32 BoardType = get_BoardType ();
wdenkb4676a22003-12-07 19:24:00 +000058 char *BoardName[2] = { "mvBlueBOX", "mvBlueLYNX" };
59 char *p;
60 bd_t *bd = gd->bd;
61
wdenkd4ca31c2004-01-02 14:00:00 +000062 hw_watchdog_reset ();
wdenkb4676a22003-12-07 19:24:00 +000063
wdenkd4ca31c2004-01-02 14:00:00 +000064 printf ("U-Boot (%s) running on mvBLUE device.\n", MV_VERSION);
65 printf (" Found %s running at %s MHz memory clock.\n",
66 BoardName[BoardType], strmhz (buf, busfreq));
wdenkb4676a22003-12-07 19:24:00 +000067
wdenkd4ca31c2004-01-02 14:00:00 +000068 init_2nd_DUART ();
wdenkb4676a22003-12-07 19:24:00 +000069
wdenkd4ca31c2004-01-02 14:00:00 +000070 if ((p = getenv ("console_nr")) != NULL) {
71 unsigned long con_nr = simple_strtoul (p, NULL, 10) & 3;
72
73 bd->bi_baudrate &= ~3;
74 bd->bi_baudrate |= con_nr & 3;
wdenkb4676a22003-12-07 19:24:00 +000075 }
76 return 0;
77}
78
Becky Bruce9973e3c2008-06-09 16:03:40 -050079phys_size_t initdram (int board_type)
wdenkb4676a22003-12-07 19:24:00 +000080{
wdenkc83bf6a2004-01-06 22:38:14 +000081 long size;
82 long new_bank0_end;
83 long mear1;
84 long emear1;
wdenkb4676a22003-12-07 19:24:00 +000085
wdenkc83bf6a2004-01-06 22:38:14 +000086 size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
wdenkb4676a22003-12-07 19:24:00 +000087
wdenkc83bf6a2004-01-06 22:38:14 +000088 new_bank0_end = size - 1;
89 mear1 = mpc824x_mpc107_getreg(MEAR1);
90 emear1 = mpc824x_mpc107_getreg(EMEAR1);
91 mear1 = (mear1 & 0xFFFFFF00) |
92 ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
93 emear1 = (emear1 & 0xFFFFFF00) |
94 ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
95 mpc824x_mpc107_setreg(MEAR1, mear1);
96 mpc824x_mpc107_setreg(EMEAR1, emear1);
wdenkb4676a22003-12-07 19:24:00 +000097
wdenkc83bf6a2004-01-06 22:38:14 +000098 return (size);
wdenkb4676a22003-12-07 19:24:00 +000099}
100
101/* ------------------------------------------------------------------------- */
wdenkd4ca31c2004-01-02 14:00:00 +0000102u8 *dhcp_vendorex_prep (u8 * e)
wdenkb4676a22003-12-07 19:24:00 +0000103{
wdenkd4ca31c2004-01-02 14:00:00 +0000104 char *ptr;
wdenkb4676a22003-12-07 19:24:00 +0000105
106 /* DHCP vendor-class-identifier = 60 */
wdenkd4ca31c2004-01-02 14:00:00 +0000107 if ((ptr = getenv ("dhcp_vendor-class-identifier"))) {
108 *e++ = 60;
109 *e++ = strlen (ptr);
110 while (*ptr)
111 *e++ = *ptr++;
112 }
wdenkb4676a22003-12-07 19:24:00 +0000113 /* my DHCP_CLIENT_IDENTIFIER = 61 */
wdenkd4ca31c2004-01-02 14:00:00 +0000114 if ((ptr = getenv ("dhcp_client_id"))) {
115 *e++ = 61;
116 *e++ = strlen (ptr);
117 while (*ptr)
118 *e++ = *ptr++;
119 }
120 return e;
wdenkb4676a22003-12-07 19:24:00 +0000121}
wdenkd4ca31c2004-01-02 14:00:00 +0000122
123u8 *dhcp_vendorex_proc (u8 * popt)
wdenkb4676a22003-12-07 19:24:00 +0000124{
wdenkd4ca31c2004-01-02 14:00:00 +0000125 return NULL;
wdenkb4676a22003-12-07 19:24:00 +0000126}
wdenkd4ca31c2004-01-02 14:00:00 +0000127
wdenkb4676a22003-12-07 19:24:00 +0000128/* ------------------------------------------------------------------------- */
129
130/*
131 * Initialize PCI Devices
132 */
133#ifdef CONFIG_PCI
wdenkd4ca31c2004-01-02 14:00:00 +0000134void pci_mvblue_clear_base (struct pci_controller *hose, pci_dev_t dev)
wdenkb4676a22003-12-07 19:24:00 +0000135{
136 u32 cnt;
wdenkd4ca31c2004-01-02 14:00:00 +0000137
138 printf ("clear base @ dev/func 0x%02x/0x%02x ... ", PCI_DEV (dev),
139 PCI_FUNC (dev));
140 for (cnt = 0; cnt < 6; cnt++)
141 pci_hose_write_config_dword (hose, dev, 0x10 + (4 * cnt),
142 0x0);
143 printf ("done\n");
wdenkb4676a22003-12-07 19:24:00 +0000144}
145
wdenkd4ca31c2004-01-02 14:00:00 +0000146void duart_setup (u32 base, u16 divisor)
wdenkb4676a22003-12-07 19:24:00 +0000147{
wdenkd4ca31c2004-01-02 14:00:00 +0000148 printf ("duart setup ...");
149 out_8 ((u8 *) (CFG_ISA_IO + base + 3), 0x80);
150 out_8 ((u8 *) (CFG_ISA_IO + base + 0), divisor & 0xff);
151 out_8 ((u8 *) (CFG_ISA_IO + base + 1), divisor >> 8);
152 out_8 ((u8 *) (CFG_ISA_IO + base + 3), 0x03);
153 out_8 ((u8 *) (CFG_ISA_IO + base + 4), 0x03);
154 out_8 ((u8 *) (CFG_ISA_IO + base + 2), 0x07);
155 printf ("done\n");
wdenkb4676a22003-12-07 19:24:00 +0000156}
157
wdenkd4ca31c2004-01-02 14:00:00 +0000158void pci_mvblue_fixup_irq_behind_bridge (struct pci_controller *hose,
159 pci_dev_t bridge, unsigned char irq)
wdenkb4676a22003-12-07 19:24:00 +0000160{
161 pci_dev_t d;
wdenkd4ca31c2004-01-02 14:00:00 +0000162 unsigned char bus;
163 unsigned short vendor, class;
wdenkb4676a22003-12-07 19:24:00 +0000164
wdenkd4ca31c2004-01-02 14:00:00 +0000165 pci_hose_read_config_byte (hose, bridge, PCI_SECONDARY_BUS, &bus);
166 for (d = PCI_BDF (bus, 0, 0);
167 d < PCI_BDF (bus, PCI_MAX_PCI_DEVICES - 1,
168 PCI_MAX_PCI_FUNCTIONS - 1);
169 d += PCI_BDF (0, 0, 1)) {
170 pci_hose_read_config_word (hose, d, PCI_VENDOR_ID, &vendor);
171 if (vendor != 0xffff && vendor != 0x0000) {
172 pci_hose_read_config_word (hose, d, PCI_CLASS_DEVICE,
173 &class);
174 if (class == PCI_CLASS_BRIDGE_PCI)
175 pci_mvblue_fixup_irq_behind_bridge (hose, d,
176 irq);
wdenkb4676a22003-12-07 19:24:00 +0000177 else
wdenkd4ca31c2004-01-02 14:00:00 +0000178 pci_hose_write_config_byte (hose, d,
179 PCI_INTERRUPT_LINE,
180 irq);
wdenkb4676a22003-12-07 19:24:00 +0000181 }
182 }
183}
184
185#define MV_MAX_PCI_BUSSES 3
186#define SLOT0_IRQ 3
187#define SLOT1_IRQ 4
wdenkd4ca31c2004-01-02 14:00:00 +0000188void pci_mvblue_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
wdenkb4676a22003-12-07 19:24:00 +0000189{
wdenkd4ca31c2004-01-02 14:00:00 +0000190 unsigned char line = 0xff;
191 unsigned short class;
wdenkb4676a22003-12-07 19:24:00 +0000192
wdenkd4ca31c2004-01-02 14:00:00 +0000193 if (PCI_BUS (dev) == 0) {
194 switch (PCI_DEV (dev)) {
195 case 0xd:
196 if (get_BoardType () == 0) {
wdenkb4676a22003-12-07 19:24:00 +0000197 line = 1;
198 } else
199 /* mvBL */
wdenkd4ca31c2004-01-02 14:00:00 +0000200 line = 2;
201 break;
202 case 0xe:
wdenkb4676a22003-12-07 19:24:00 +0000203 /* mvBB: IDE */
204 line = 2;
wdenkd4ca31c2004-01-02 14:00:00 +0000205 pci_hose_write_config_byte (hose, dev, 0x8a, 0x20);
wdenkb4676a22003-12-07 19:24:00 +0000206 break;
207 case 0xf:
208 /* mvBB: Slot0 (Grabber) */
wdenkd4ca31c2004-01-02 14:00:00 +0000209 pci_hose_read_config_word (hose, dev,
210 PCI_CLASS_DEVICE, &class);
211 if (class == PCI_CLASS_BRIDGE_PCI) {
212 pci_mvblue_fixup_irq_behind_bridge (hose, dev,
213 SLOT0_IRQ);
wdenkb4676a22003-12-07 19:24:00 +0000214 line = 0xff;
215 } else
216 line = SLOT0_IRQ;
217 break;
218 case 0x10:
219 /* mvBB: Slot1 */
wdenkd4ca31c2004-01-02 14:00:00 +0000220 pci_hose_read_config_word (hose, dev,
221 PCI_CLASS_DEVICE, &class);
222 if (class == PCI_CLASS_BRIDGE_PCI) {
223 pci_mvblue_fixup_irq_behind_bridge (hose, dev,
224 SLOT1_IRQ);
wdenkb4676a22003-12-07 19:24:00 +0000225 line = 0xff;
226 } else
227 line = SLOT1_IRQ;
228 break;
wdenkd4ca31c2004-01-02 14:00:00 +0000229 default:
230 printf ("***pci_scan: illegal dev = 0x%08x\n",
231 PCI_DEV (dev));
wdenkb4676a22003-12-07 19:24:00 +0000232 line = 0xff;
233 break;
wdenkd4ca31c2004-01-02 14:00:00 +0000234 }
235 pci_hose_write_config_byte (hose, dev, PCI_INTERRUPT_LINE,
236 line);
wdenkb4676a22003-12-07 19:24:00 +0000237 }
238}
239
240struct pci_controller hose = {
wdenkd4ca31c2004-01-02 14:00:00 +0000241 fixup_irq:pci_mvblue_fixup_irq
wdenkb4676a22003-12-07 19:24:00 +0000242};
243
wdenkd4ca31c2004-01-02 14:00:00 +0000244void pci_init_board (void)
wdenkb4676a22003-12-07 19:24:00 +0000245{
wdenkd4ca31c2004-01-02 14:00:00 +0000246 pci_mpc824x_init (&hose);
wdenkb4676a22003-12-07 19:24:00 +0000247}
248#endif