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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 18d66533ac773f59efc93e5c19971fad5e6af82f / . / drivers / ddr / fsl / interactive.c
blob: 4e2120f7c457ac2d26fca088e7fc48bd9545c3ff [file] [log] [blame]
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]1/*
York Sun34e026f2014-03-27 17:54:47 -0700[diff] [blame]2 * Copyright 2010-2014 Freescale Semiconductor, Inc.
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]3 *
Wolfgang Denk1a459662013-07-08 09:37:19 +0200[diff] [blame]4 * SPDX-License-Identifier: GPL-2.0+
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]5 */
6
7/*
8 * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
9 * Based on code from spd_sdram.c
10 * Author: James Yang [at freescale.com]
11 * York Sun [at freescale.com]
12 */
13
14#include <common.h>
Simon Glass18d66532014-04-10 20:01:25 -0600[diff] [blame^]15#include <cli.h>
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]16#include <linux/ctype.h>
17#include <asm/types.h>
York Sun5614e712013-09-30 09:22:09 -0700[diff] [blame]18#include <asm/io.h>
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]19
York Sun5614e712013-09-30 09:22:09 -0700[diff] [blame]20#include <fsl_ddr_sdram.h>
21#include <fsl_ddr.h>
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]22
23/* Option parameter Structures */
24struct options_string {
25 const char *option_name;
26 size_t offset;
27 unsigned int size;
28 const char printhex;
29};
30
31static unsigned int picos_to_mhz(unsigned int picos)
32{
33 return 1000000 / picos;
34}
35
36static void print_option_table(const struct options_string *table,
37 int table_size,
38 const void *base)
39{
40 unsigned int i;
41 unsigned int *ptr;
42 unsigned long long *ptr_l;
43
44 for (i = 0; i < table_size; i++) {
45 switch (table[i].size) {
46 case 4:
47 ptr = (unsigned int *) (base + table[i].offset);
48 if (table[i].printhex) {
49 printf("%s = 0x%08X\n",
50 table[i].option_name, *ptr);
51 } else {
52 printf("%s = %u\n",
53 table[i].option_name, *ptr);
54 }
55 break;
56 case 8:
57 ptr_l = (unsigned long long *) (base + table[i].offset);
58 printf("%s = %llu\n",
59 table[i].option_name, *ptr_l);
60 break;
61 default:
62 printf("Unrecognized size!\n");
63 break;
64 }
65 }
66}
67
68static int handle_option_table(const struct options_string *table,
69 int table_size,
70 void *base,
71 const char *opt,
72 const char *val)
73{
74 unsigned int i;
75 unsigned int value, *ptr;
76 unsigned long long value_l, *ptr_l;
77
78 for (i = 0; i < table_size; i++) {
79 if (strcmp(table[i].option_name, opt) != 0)
80 continue;
81 switch (table[i].size) {
82 case 4:
83 value = simple_strtoul(val, NULL, 0);
84 ptr = base + table[i].offset;
85 *ptr = value;
86 break;
87 case 8:
88 value_l = simple_strtoull(val, NULL, 0);
89 ptr_l = base + table[i].offset;
90 *ptr_l = value_l;
91 break;
92 default:
93 printf("Unrecognized size!\n");
94 break;
95 }
96 return 1;
97 }
98
99 return 0;
100}
101
102static void fsl_ddr_generic_edit(void *pdata,
103 void *pend,
104 unsigned int element_size,
105 unsigned int element_num,
106 unsigned int value)
107{
108 char *pcdata = (char *)pdata; /* BIG ENDIAN ONLY */
109
110 pcdata += element_num * element_size;
111 if ((pcdata + element_size) > (char *) pend) {
112 printf("trying to write past end of data\n");
113 return;
114 }
115
116 switch (element_size) {
117 case 1:
118 __raw_writeb(value, pcdata);
119 break;
120 case 2:
121 __raw_writew(value, pcdata);
122 break;
123 case 4:
124 __raw_writel(value, pcdata);
125 break;
126 default:
127 printf("unexpected element size %u\n", element_size);
128 break;
129 }
130}
131
132static void fsl_ddr_spd_edit(fsl_ddr_info_t *pinfo,
133 unsigned int ctrl_num,
134 unsigned int dimm_num,
135 unsigned int element_num,
136 unsigned int value)
137{
138 generic_spd_eeprom_t *pspd;
139
140 pspd = &(pinfo->spd_installed_dimms[ctrl_num][dimm_num]);
141 fsl_ddr_generic_edit(pspd, pspd + 1, 1, element_num, value);
142}
143
144#define COMMON_TIMING(x) {#x, offsetof(common_timing_params_t, x), \
145 sizeof((common_timing_params_t *)0)->x, 0}
146
147static void lowest_common_dimm_parameters_edit(fsl_ddr_info_t *pinfo,
148 unsigned int ctrl_num,
149 const char *optname_str,
150 const char *value_str)
151{
152 common_timing_params_t *p = &pinfo->common_timing_params[ctrl_num];
153
154 static const struct options_string options[] = {
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530[diff] [blame]155 COMMON_TIMING(tckmin_x_ps),
156 COMMON_TIMING(tckmax_ps),
York Sun34e026f2014-03-27 17:54:47 -0700[diff] [blame]157 COMMON_TIMING(taamin_ps),
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530[diff] [blame]158 COMMON_TIMING(trcd_ps),
159 COMMON_TIMING(trp_ps),
160 COMMON_TIMING(tras_ps),
York Sun34e026f2014-03-27 17:54:47 -0700[diff] [blame]161
162#ifdef CONFIG_SYS_FSL_DDR4
163 COMMON_TIMING(trfc1_ps),
164 COMMON_TIMING(trfc2_ps),
165 COMMON_TIMING(trfc4_ps),
166 COMMON_TIMING(trrds_ps),
167 COMMON_TIMING(trrdl_ps),
168 COMMON_TIMING(tccdl_ps),
169#else
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530[diff] [blame]170 COMMON_TIMING(twtr_ps),
171 COMMON_TIMING(trfc_ps),
172 COMMON_TIMING(trrd_ps),
York Sun34e026f2014-03-27 17:54:47 -0700[diff] [blame]173 COMMON_TIMING(trtp_ps),
174#endif
175 COMMON_TIMING(twr_ps),
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530[diff] [blame]176 COMMON_TIMING(trc_ps),
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]177 COMMON_TIMING(refresh_rate_ps),
York Sun34e026f2014-03-27 17:54:47 -0700[diff] [blame]178 COMMON_TIMING(extended_op_srt),
179#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530[diff] [blame]180 COMMON_TIMING(tis_ps),
181 COMMON_TIMING(tih_ps),
182 COMMON_TIMING(tds_ps),
183 COMMON_TIMING(tdh_ps),
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530[diff] [blame]184 COMMON_TIMING(tdqsq_max_ps),
185 COMMON_TIMING(tqhs_ps),
York Sun34e026f2014-03-27 17:54:47 -0700[diff] [blame]186#endif
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]187 COMMON_TIMING(ndimms_present),
York Sun34e026f2014-03-27 17:54:47 -0700[diff] [blame]188 COMMON_TIMING(lowest_common_spd_caslat),
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]189 COMMON_TIMING(highest_common_derated_caslat),
190 COMMON_TIMING(additive_latency),
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530[diff] [blame]191 COMMON_TIMING(all_dimms_burst_lengths_bitmask),
192 COMMON_TIMING(all_dimms_registered),
193 COMMON_TIMING(all_dimms_unbuffered),
194 COMMON_TIMING(all_dimms_ecc_capable),
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]195 COMMON_TIMING(total_mem),
196 COMMON_TIMING(base_address),
197 };
198 static const unsigned int n_opts = ARRAY_SIZE(options);
199
200 if (handle_option_table(options, n_opts, p, optname_str, value_str))
201 return;
202
203 printf("Error: couldn't find option string %s\n", optname_str);
204}
205
206#define DIMM_PARM(x) {#x, offsetof(dimm_params_t, x), \
207 sizeof((dimm_params_t *)0)->x, 0}
208
209static void fsl_ddr_dimm_parameters_edit(fsl_ddr_info_t *pinfo,
210 unsigned int ctrl_num,
211 unsigned int dimm_num,
212 const char *optname_str,
213 const char *value_str)
214{
215 dimm_params_t *p = &(pinfo->dimm_params[ctrl_num][dimm_num]);
216
217 static const struct options_string options[] = {
218 DIMM_PARM(n_ranks),
219 DIMM_PARM(data_width),
220 DIMM_PARM(primary_sdram_width),
221 DIMM_PARM(ec_sdram_width),
222 DIMM_PARM(registered_dimm),
York Sunb61e0612013-06-25 11:37:47 -0700[diff] [blame]223 DIMM_PARM(device_width),
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]224
225 DIMM_PARM(n_row_addr),
226 DIMM_PARM(n_col_addr),
227 DIMM_PARM(edc_config),
York Sun34e026f2014-03-27 17:54:47 -0700[diff] [blame]228#ifdef CONFIG_SYS_FSL_DDR4
229 DIMM_PARM(bank_addr_bits),
230 DIMM_PARM(bank_group_bits),
231#else
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]232 DIMM_PARM(n_banks_per_sdram_device),
York Sun34e026f2014-03-27 17:54:47 -0700[diff] [blame]233#endif
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]234 DIMM_PARM(burst_lengths_bitmask),
235 DIMM_PARM(row_density),
236
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530[diff] [blame]237 DIMM_PARM(tckmin_x_ps),
238 DIMM_PARM(tckmin_x_minus_1_ps),
239 DIMM_PARM(tckmin_x_minus_2_ps),
240 DIMM_PARM(tckmax_ps),
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]241
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530[diff] [blame]242 DIMM_PARM(caslat_x),
243 DIMM_PARM(caslat_x_minus_1),
244 DIMM_PARM(caslat_x_minus_2),
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]245
246 DIMM_PARM(caslat_lowest_derated),
247
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530[diff] [blame]248 DIMM_PARM(trcd_ps),
249 DIMM_PARM(trp_ps),
250 DIMM_PARM(tras_ps),
York Sun34e026f2014-03-27 17:54:47 -0700[diff] [blame]251#ifdef CONFIG_SYS_FSL_DDR4
252 DIMM_PARM(trfc1_ps),
253 DIMM_PARM(trfc2_ps),
254 DIMM_PARM(trfc4_ps),
255 DIMM_PARM(trrds_ps),
256 DIMM_PARM(trrdl_ps),
257 DIMM_PARM(tccdl_ps),
258#else
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530[diff] [blame]259 DIMM_PARM(twr_ps),
260 DIMM_PARM(twtr_ps),
261 DIMM_PARM(trfc_ps),
262 DIMM_PARM(trrd_ps),
York Sun34e026f2014-03-27 17:54:47 -0700[diff] [blame]263 DIMM_PARM(trtp_ps),
264#endif
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530[diff] [blame]265 DIMM_PARM(trc_ps),
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]266 DIMM_PARM(refresh_rate_ps),
York Sun34e026f2014-03-27 17:54:47 -0700[diff] [blame]267 DIMM_PARM(extended_op_srt),
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]268
York Sun34e026f2014-03-27 17:54:47 -0700[diff] [blame]269#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530[diff] [blame]270 DIMM_PARM(tis_ps),
271 DIMM_PARM(tih_ps),
272 DIMM_PARM(tds_ps),
273 DIMM_PARM(tdh_ps),
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530[diff] [blame]274 DIMM_PARM(tdqsq_max_ps),
275 DIMM_PARM(tqhs_ps),
York Sun34e026f2014-03-27 17:54:47 -0700[diff] [blame]276#endif
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]277
278 DIMM_PARM(rank_density),
279 DIMM_PARM(capacity),
280 DIMM_PARM(base_address),
281 };
282
283 static const unsigned int n_opts = ARRAY_SIZE(options);
284
285 if (handle_option_table(options, n_opts, p, optname_str, value_str))
286 return;
287
288 printf("couldn't find option string %s\n", optname_str);
289}
290
291static void print_dimm_parameters(const dimm_params_t *pdimm)
292{
293 static const struct options_string options[] = {
294 DIMM_PARM(n_ranks),
295 DIMM_PARM(data_width),
296 DIMM_PARM(primary_sdram_width),
297 DIMM_PARM(ec_sdram_width),
298 DIMM_PARM(registered_dimm),
York Sunb61e0612013-06-25 11:37:47 -0700[diff] [blame]299 DIMM_PARM(device_width),
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]300
301 DIMM_PARM(n_row_addr),
302 DIMM_PARM(n_col_addr),
303 DIMM_PARM(edc_config),
York Sun34e026f2014-03-27 17:54:47 -0700[diff] [blame]304#ifdef CONFIG_SYS_FSL_DDR4
305 DIMM_PARM(bank_addr_bits),
306 DIMM_PARM(bank_group_bits),
307#else
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]308 DIMM_PARM(n_banks_per_sdram_device),
York Sun34e026f2014-03-27 17:54:47 -0700[diff] [blame]309#endif
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]310
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530[diff] [blame]311 DIMM_PARM(tckmin_x_ps),
312 DIMM_PARM(tckmin_x_minus_1_ps),
313 DIMM_PARM(tckmin_x_minus_2_ps),
314 DIMM_PARM(tckmax_ps),
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]315
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530[diff] [blame]316 DIMM_PARM(caslat_x),
317 DIMM_PARM(taa_ps),
318 DIMM_PARM(caslat_x_minus_1),
319 DIMM_PARM(caslat_x_minus_2),
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]320 DIMM_PARM(caslat_lowest_derated),
321
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530[diff] [blame]322 DIMM_PARM(trcd_ps),
323 DIMM_PARM(trp_ps),
324 DIMM_PARM(tras_ps),
York Sun34e026f2014-03-27 17:54:47 -0700[diff] [blame]325#ifdef CONFIG_SYS_FSL_DDR4
326 DIMM_PARM(trfc1_ps),
327 DIMM_PARM(trfc2_ps),
328 DIMM_PARM(trfc4_ps),
329 DIMM_PARM(trrds_ps),
330 DIMM_PARM(trrdl_ps),
331 DIMM_PARM(tccdl_ps),
332#else
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530[diff] [blame]333 DIMM_PARM(twr_ps),
334 DIMM_PARM(twtr_ps),
335 DIMM_PARM(trfc_ps),
336 DIMM_PARM(trrd_ps),
York Sun34e026f2014-03-27 17:54:47 -0700[diff] [blame]337 DIMM_PARM(trtp_ps),
338#endif
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530[diff] [blame]339 DIMM_PARM(trc_ps),
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]340 DIMM_PARM(refresh_rate_ps),
341
York Sun34e026f2014-03-27 17:54:47 -0700[diff] [blame]342#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530[diff] [blame]343 DIMM_PARM(tis_ps),
344 DIMM_PARM(tih_ps),
345 DIMM_PARM(tds_ps),
346 DIMM_PARM(tdh_ps),
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530[diff] [blame]347 DIMM_PARM(tdqsq_max_ps),
348 DIMM_PARM(tqhs_ps),
York Sun34e026f2014-03-27 17:54:47 -0700[diff] [blame]349#endif
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]350 };
351 static const unsigned int n_opts = ARRAY_SIZE(options);
352
353 if (pdimm->n_ranks == 0) {
354 printf("DIMM not present\n");
355 return;
356 }
357 printf("DIMM organization parameters:\n");
358 printf("module part name = %s\n", pdimm->mpart);
359 printf("rank_density = %llu bytes (%llu megabytes)\n",
360 pdimm->rank_density, pdimm->rank_density / 0x100000);
361 printf("capacity = %llu bytes (%llu megabytes)\n",
362 pdimm->capacity, pdimm->capacity / 0x100000);
363 printf("burst_lengths_bitmask = %02X\n",
364 pdimm->burst_lengths_bitmask);
365 printf("base_addresss = %llu (%08llX %08llX)\n",
366 pdimm->base_address,
367 (pdimm->base_address >> 32),
368 pdimm->base_address & 0xFFFFFFFF);
369 print_option_table(options, n_opts, pdimm);
370}
371
372static void print_lowest_common_dimm_parameters(
373 const common_timing_params_t *plcd_dimm_params)
374{
375 static const struct options_string options[] = {
York Sun34e026f2014-03-27 17:54:47 -0700[diff] [blame]376 COMMON_TIMING(taamin_ps),
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530[diff] [blame]377 COMMON_TIMING(trcd_ps),
378 COMMON_TIMING(trp_ps),
379 COMMON_TIMING(tras_ps),
York Sun34e026f2014-03-27 17:54:47 -0700[diff] [blame]380#ifdef CONFIG_SYS_FSL_DDR4
381 COMMON_TIMING(trfc1_ps),
382 COMMON_TIMING(trfc2_ps),
383 COMMON_TIMING(trfc4_ps),
384 COMMON_TIMING(trrds_ps),
385 COMMON_TIMING(trrdl_ps),
386 COMMON_TIMING(tccdl_ps),
387#else
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530[diff] [blame]388 COMMON_TIMING(twtr_ps),
389 COMMON_TIMING(trfc_ps),
390 COMMON_TIMING(trrd_ps),
York Sun34e026f2014-03-27 17:54:47 -0700[diff] [blame]391 COMMON_TIMING(trtp_ps),
392#endif
393 COMMON_TIMING(twr_ps),
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530[diff] [blame]394 COMMON_TIMING(trc_ps),
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]395 COMMON_TIMING(refresh_rate_ps),
York Sun34e026f2014-03-27 17:54:47 -0700[diff] [blame]396 COMMON_TIMING(extended_op_srt),
397#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530[diff] [blame]398 COMMON_TIMING(tis_ps),
York Sun34e026f2014-03-27 17:54:47 -0700[diff] [blame]399 COMMON_TIMING(tih_ps),
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530[diff] [blame]400 COMMON_TIMING(tds_ps),
401 COMMON_TIMING(tdh_ps),
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530[diff] [blame]402 COMMON_TIMING(tdqsq_max_ps),
403 COMMON_TIMING(tqhs_ps),
York Sun34e026f2014-03-27 17:54:47 -0700[diff] [blame]404#endif
405 COMMON_TIMING(lowest_common_spd_caslat),
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]406 COMMON_TIMING(highest_common_derated_caslat),
407 COMMON_TIMING(additive_latency),
408 COMMON_TIMING(ndimms_present),
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530[diff] [blame]409 COMMON_TIMING(all_dimms_registered),
410 COMMON_TIMING(all_dimms_unbuffered),
411 COMMON_TIMING(all_dimms_ecc_capable),
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]412 };
413 static const unsigned int n_opts = ARRAY_SIZE(options);
414
415 /* Clock frequencies */
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530[diff] [blame]416 printf("tckmin_x_ps = %u (%u MHz)\n",
417 plcd_dimm_params->tckmin_x_ps,
418 picos_to_mhz(plcd_dimm_params->tckmin_x_ps));
419 printf("tckmax_ps = %u (%u MHz)\n",
420 plcd_dimm_params->tckmax_ps,
421 picos_to_mhz(plcd_dimm_params->tckmax_ps));
422 printf("all_dimms_burst_lengths_bitmask = %02X\n",
423 plcd_dimm_params->all_dimms_burst_lengths_bitmask);
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]424
425 print_option_table(options, n_opts, plcd_dimm_params);
426
427 printf("total_mem = %llu (%llu megabytes)\n",
428 plcd_dimm_params->total_mem,
429 plcd_dimm_params->total_mem / 0x100000);
430 printf("base_address = %llu (%llu megabytes)\n",
431 plcd_dimm_params->base_address,
432 plcd_dimm_params->base_address / 0x100000);
433}
434
435#define CTRL_OPTIONS(x) {#x, offsetof(memctl_options_t, x), \
436 sizeof((memctl_options_t *)0)->x, 0}
437#define CTRL_OPTIONS_CS(x, y) {"cs" #x "_" #y, \
438 offsetof(memctl_options_t, cs_local_opts[x].y), \
439 sizeof((memctl_options_t *)0)->cs_local_opts[x].y, 0}
440
441static void fsl_ddr_options_edit(fsl_ddr_info_t *pinfo,
442 unsigned int ctl_num,
443 const char *optname_str,
444 const char *value_str)
445{
446 memctl_options_t *p = &(pinfo->memctl_opts[ctl_num]);
447 /*
448 * This array all on the stack and *computed* each time this
449 * function is rung.
450 */
451 static const struct options_string options[] = {
452 CTRL_OPTIONS_CS(0, odt_rd_cfg),
453 CTRL_OPTIONS_CS(0, odt_wr_cfg),
454#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
455 CTRL_OPTIONS_CS(1, odt_rd_cfg),
456 CTRL_OPTIONS_CS(1, odt_wr_cfg),
457#endif
458#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
459 CTRL_OPTIONS_CS(2, odt_rd_cfg),
460 CTRL_OPTIONS_CS(2, odt_wr_cfg),
461#endif
462#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
463 CTRL_OPTIONS_CS(3, odt_rd_cfg),
464 CTRL_OPTIONS_CS(3, odt_wr_cfg),
465#endif
York Sun5614e712013-09-30 09:22:09 -0700[diff] [blame]466#if defined(CONFIG_SYS_FSL_DDR3)
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]467 CTRL_OPTIONS_CS(0, odt_rtt_norm),
468 CTRL_OPTIONS_CS(0, odt_rtt_wr),
469#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
470 CTRL_OPTIONS_CS(1, odt_rtt_norm),
471 CTRL_OPTIONS_CS(1, odt_rtt_wr),
472#endif
473#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
474 CTRL_OPTIONS_CS(2, odt_rtt_norm),
475 CTRL_OPTIONS_CS(2, odt_rtt_wr),
476#endif
477#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
478 CTRL_OPTIONS_CS(3, odt_rtt_norm),
479 CTRL_OPTIONS_CS(3, odt_rtt_wr),
480#endif
481#endif
482 CTRL_OPTIONS(memctl_interleaving),
483 CTRL_OPTIONS(memctl_interleaving_mode),
484 CTRL_OPTIONS(ba_intlv_ctl),
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530[diff] [blame]485 CTRL_OPTIONS(ecc_mode),
486 CTRL_OPTIONS(ecc_init_using_memctl),
487 CTRL_OPTIONS(dqs_config),
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]488 CTRL_OPTIONS(self_refresh_in_sleep),
489 CTRL_OPTIONS(dynamic_power),
490 CTRL_OPTIONS(data_bus_width),
491 CTRL_OPTIONS(burst_length),
492 CTRL_OPTIONS(cas_latency_override),
493 CTRL_OPTIONS(cas_latency_override_value),
494 CTRL_OPTIONS(use_derated_caslat),
495 CTRL_OPTIONS(additive_latency_override),
496 CTRL_OPTIONS(additive_latency_override_value),
497 CTRL_OPTIONS(clk_adjust),
498 CTRL_OPTIONS(cpo_override),
499 CTRL_OPTIONS(write_data_delay),
500 CTRL_OPTIONS(half_strength_driver_enable),
501
502 /*
503 * These can probably be changed to 2T_EN and 3T_EN
504 * (using a leading numerical character) without problem
505 */
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530[diff] [blame]506 CTRL_OPTIONS(twot_en),
507 CTRL_OPTIONS(threet_en),
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]508 CTRL_OPTIONS(ap_en),
York Sunb61e0612013-06-25 11:37:47 -0700[diff] [blame]509 CTRL_OPTIONS(x4_en),
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]510 CTRL_OPTIONS(bstopre),
511 CTRL_OPTIONS(wrlvl_override),
512 CTRL_OPTIONS(wrlvl_sample),
513 CTRL_OPTIONS(wrlvl_start),
514 CTRL_OPTIONS(rcw_override),
515 CTRL_OPTIONS(rcw_1),
516 CTRL_OPTIONS(rcw_2),
York Sun57495e42012-10-08 07:44:22 +0000[diff] [blame]517 CTRL_OPTIONS(ddr_cdr1),
518 CTRL_OPTIONS(ddr_cdr2),
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530[diff] [blame]519 CTRL_OPTIONS(tcke_clock_pulse_width_ps),
520 CTRL_OPTIONS(tfaw_window_four_activates_ps),
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]521 CTRL_OPTIONS(trwt_override),
522 CTRL_OPTIONS(trwt),
York Sun34e026f2014-03-27 17:54:47 -0700[diff] [blame]523 CTRL_OPTIONS(rtt_override),
524 CTRL_OPTIONS(rtt_override_value),
525 CTRL_OPTIONS(rtt_wr_override_value),
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]526 };
527
528 static const unsigned int n_opts = ARRAY_SIZE(options);
529
530 if (handle_option_table(options, n_opts, p,
531 optname_str, value_str))
532 return;
533
534 printf("couldn't find option string %s\n", optname_str);
535}
536
537#define CFG_REGS(x) {#x, offsetof(fsl_ddr_cfg_regs_t, x), \
538 sizeof((fsl_ddr_cfg_regs_t *)0)->x, 1}
539#define CFG_REGS_CS(x, y) {"cs" #x "_" #y, \
540 offsetof(fsl_ddr_cfg_regs_t, cs[x].y), \
541 sizeof((fsl_ddr_cfg_regs_t *)0)->cs[x].y, 1}
542
543static void print_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
544{
545 unsigned int i;
546 static const struct options_string options[] = {
547 CFG_REGS_CS(0, bnds),
548 CFG_REGS_CS(0, config),
549 CFG_REGS_CS(0, config_2),
550#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
551 CFG_REGS_CS(1, bnds),
552 CFG_REGS_CS(1, config),
553 CFG_REGS_CS(1, config_2),
554#endif
555#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
556 CFG_REGS_CS(2, bnds),
557 CFG_REGS_CS(2, config),
558 CFG_REGS_CS(2, config_2),
559#endif
560#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
561 CFG_REGS_CS(3, bnds),
562 CFG_REGS_CS(3, config),
563 CFG_REGS_CS(3, config_2),
564#endif
565 CFG_REGS(timing_cfg_3),
566 CFG_REGS(timing_cfg_0),
567 CFG_REGS(timing_cfg_1),
568 CFG_REGS(timing_cfg_2),
569 CFG_REGS(ddr_sdram_cfg),
570 CFG_REGS(ddr_sdram_cfg_2),
York Sun34e026f2014-03-27 17:54:47 -0700[diff] [blame]571 CFG_REGS(ddr_sdram_cfg_3),
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]572 CFG_REGS(ddr_sdram_mode),
573 CFG_REGS(ddr_sdram_mode_2),
574 CFG_REGS(ddr_sdram_mode_3),
575 CFG_REGS(ddr_sdram_mode_4),
576 CFG_REGS(ddr_sdram_mode_5),
577 CFG_REGS(ddr_sdram_mode_6),
578 CFG_REGS(ddr_sdram_mode_7),
579 CFG_REGS(ddr_sdram_mode_8),
York Sun34e026f2014-03-27 17:54:47 -0700[diff] [blame]580#ifdef CONFIG_SYS_FSL_DDR4
581 CFG_REGS(ddr_sdram_mode_9),
582 CFG_REGS(ddr_sdram_mode_10),
583 CFG_REGS(ddr_sdram_mode_11),
584 CFG_REGS(ddr_sdram_mode_12),
585 CFG_REGS(ddr_sdram_mode_13),
586 CFG_REGS(ddr_sdram_mode_14),
587 CFG_REGS(ddr_sdram_mode_15),
588 CFG_REGS(ddr_sdram_mode_16),
589#endif
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]590 CFG_REGS(ddr_sdram_interval),
591 CFG_REGS(ddr_data_init),
592 CFG_REGS(ddr_sdram_clk_cntl),
593 CFG_REGS(ddr_init_addr),
594 CFG_REGS(ddr_init_ext_addr),
595 CFG_REGS(timing_cfg_4),
596 CFG_REGS(timing_cfg_5),
York Sun34e026f2014-03-27 17:54:47 -0700[diff] [blame]597#ifdef CONFIG_SYS_FSL_DDR4
598 CFG_REGS(timing_cfg_6),
599 CFG_REGS(timing_cfg_7),
600 CFG_REGS(timing_cfg_8),
601 CFG_REGS(timing_cfg_9),
602#endif
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]603 CFG_REGS(ddr_zq_cntl),
604 CFG_REGS(ddr_wrlvl_cntl),
York Sun57495e42012-10-08 07:44:22 +0000[diff] [blame]605 CFG_REGS(ddr_wrlvl_cntl_2),
606 CFG_REGS(ddr_wrlvl_cntl_3),
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]607 CFG_REGS(ddr_sr_cntr),
608 CFG_REGS(ddr_sdram_rcw_1),
609 CFG_REGS(ddr_sdram_rcw_2),
610 CFG_REGS(ddr_cdr1),
611 CFG_REGS(ddr_cdr2),
York Sun34e026f2014-03-27 17:54:47 -0700[diff] [blame]612 CFG_REGS(dq_map_0),
613 CFG_REGS(dq_map_1),
614 CFG_REGS(dq_map_2),
615 CFG_REGS(dq_map_3),
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]616 CFG_REGS(err_disable),
617 CFG_REGS(err_int_en),
York Sun57495e42012-10-08 07:44:22 +0000[diff] [blame]618 CFG_REGS(ddr_eor),
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]619 };
620 static const unsigned int n_opts = ARRAY_SIZE(options);
621
622 print_option_table(options, n_opts, ddr);
623
624 for (i = 0; i < 32; i++)
625 printf("debug_%02d = 0x%08X\n", i+1, ddr->debug[i]);
626}
627
628static void fsl_ddr_regs_edit(fsl_ddr_info_t *pinfo,
629 unsigned int ctrl_num,
630 const char *regname,
631 const char *value_str)
632{
633 unsigned int i;
634 fsl_ddr_cfg_regs_t *ddr;
635 char buf[20];
636 static const struct options_string options[] = {
637 CFG_REGS_CS(0, bnds),
638 CFG_REGS_CS(0, config),
639 CFG_REGS_CS(0, config_2),
640#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
641 CFG_REGS_CS(1, bnds),
642 CFG_REGS_CS(1, config),
643 CFG_REGS_CS(1, config_2),
644#endif
645#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
646 CFG_REGS_CS(2, bnds),
647 CFG_REGS_CS(2, config),
648 CFG_REGS_CS(2, config_2),
649#endif
650#if (CONFIG_CHIP_SELECTS_PER_CTRL > 3)
651 CFG_REGS_CS(3, bnds),
652 CFG_REGS_CS(3, config),
653 CFG_REGS_CS(3, config_2),
654#endif
655 CFG_REGS(timing_cfg_3),
656 CFG_REGS(timing_cfg_0),
657 CFG_REGS(timing_cfg_1),
658 CFG_REGS(timing_cfg_2),
659 CFG_REGS(ddr_sdram_cfg),
660 CFG_REGS(ddr_sdram_cfg_2),
York Sun34e026f2014-03-27 17:54:47 -0700[diff] [blame]661 CFG_REGS(ddr_sdram_cfg_3),
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]662 CFG_REGS(ddr_sdram_mode),
663 CFG_REGS(ddr_sdram_mode_2),
664 CFG_REGS(ddr_sdram_mode_3),
665 CFG_REGS(ddr_sdram_mode_4),
666 CFG_REGS(ddr_sdram_mode_5),
667 CFG_REGS(ddr_sdram_mode_6),
668 CFG_REGS(ddr_sdram_mode_7),
669 CFG_REGS(ddr_sdram_mode_8),
York Sun34e026f2014-03-27 17:54:47 -0700[diff] [blame]670#ifdef CONFIG_SYS_FSL_DDR4
671 CFG_REGS(ddr_sdram_mode_9),
672 CFG_REGS(ddr_sdram_mode_10),
673 CFG_REGS(ddr_sdram_mode_11),
674 CFG_REGS(ddr_sdram_mode_12),
675 CFG_REGS(ddr_sdram_mode_13),
676 CFG_REGS(ddr_sdram_mode_14),
677 CFG_REGS(ddr_sdram_mode_15),
678 CFG_REGS(ddr_sdram_mode_16),
679#endif
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]680 CFG_REGS(ddr_sdram_interval),
681 CFG_REGS(ddr_data_init),
682 CFG_REGS(ddr_sdram_clk_cntl),
683 CFG_REGS(ddr_init_addr),
684 CFG_REGS(ddr_init_ext_addr),
685 CFG_REGS(timing_cfg_4),
686 CFG_REGS(timing_cfg_5),
York Sun34e026f2014-03-27 17:54:47 -0700[diff] [blame]687#ifdef CONFIG_SYS_FSL_DDR4
688 CFG_REGS(timing_cfg_6),
689 CFG_REGS(timing_cfg_7),
690 CFG_REGS(timing_cfg_8),
691 CFG_REGS(timing_cfg_9),
692#endif
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]693 CFG_REGS(ddr_zq_cntl),
694 CFG_REGS(ddr_wrlvl_cntl),
York Sun57495e42012-10-08 07:44:22 +0000[diff] [blame]695 CFG_REGS(ddr_wrlvl_cntl_2),
696 CFG_REGS(ddr_wrlvl_cntl_3),
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]697 CFG_REGS(ddr_sr_cntr),
698 CFG_REGS(ddr_sdram_rcw_1),
699 CFG_REGS(ddr_sdram_rcw_2),
700 CFG_REGS(ddr_cdr1),
701 CFG_REGS(ddr_cdr2),
York Sun34e026f2014-03-27 17:54:47 -0700[diff] [blame]702 CFG_REGS(dq_map_0),
703 CFG_REGS(dq_map_1),
704 CFG_REGS(dq_map_2),
705 CFG_REGS(dq_map_3),
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]706 CFG_REGS(err_disable),
707 CFG_REGS(err_int_en),
708 CFG_REGS(ddr_sdram_rcw_2),
709 CFG_REGS(ddr_sdram_rcw_2),
York Sun57495e42012-10-08 07:44:22 +0000[diff] [blame]710 CFG_REGS(ddr_eor),
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]711 };
712 static const unsigned int n_opts = ARRAY_SIZE(options);
713
714 debug("fsl_ddr_regs_edit: ctrl_num = %u, "
715 "regname = %s, value = %s\n",
716 ctrl_num, regname, value_str);
717 if (ctrl_num > CONFIG_NUM_DDR_CONTROLLERS)
718 return;
719
720 ddr = &(pinfo->fsl_ddr_config_reg[ctrl_num]);
721
722 if (handle_option_table(options, n_opts, ddr, regname, value_str))
723 return;
724
725 for (i = 0; i < 32; i++) {
726 unsigned int value = simple_strtoul(value_str, NULL, 0);
727 sprintf(buf, "debug_%u", i + 1);
728 if (strcmp(buf, regname) == 0) {
729 ddr->debug[i] = value;
730 return;
731 }
732 }
733 printf("Error: couldn't find register string %s\n", regname);
734}
735
736#define CTRL_OPTIONS_HEX(x) {#x, offsetof(memctl_options_t, x), \
737 sizeof((memctl_options_t *)0)->x, 1}
738
739static void print_memctl_options(const memctl_options_t *popts)
740{
741 static const struct options_string options[] = {
742 CTRL_OPTIONS_CS(0, odt_rd_cfg),
743 CTRL_OPTIONS_CS(0, odt_wr_cfg),
744#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
745 CTRL_OPTIONS_CS(1, odt_rd_cfg),
746 CTRL_OPTIONS_CS(1, odt_wr_cfg),
747#endif
748#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
749 CTRL_OPTIONS_CS(2, odt_rd_cfg),
750 CTRL_OPTIONS_CS(2, odt_wr_cfg),
751#endif
752#if (CONFIG_CHIP_SELECTS_PER_CTRL > 3)
753 CTRL_OPTIONS_CS(3, odt_rd_cfg),
754 CTRL_OPTIONS_CS(3, odt_wr_cfg),
755#endif
York Sun5614e712013-09-30 09:22:09 -0700[diff] [blame]756#if defined(CONFIG_SYS_FSL_DDR3)
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]757 CTRL_OPTIONS_CS(0, odt_rtt_norm),
758 CTRL_OPTIONS_CS(0, odt_rtt_wr),
759#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
760 CTRL_OPTIONS_CS(1, odt_rtt_norm),
761 CTRL_OPTIONS_CS(1, odt_rtt_wr),
762#endif
763#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
764 CTRL_OPTIONS_CS(2, odt_rtt_norm),
765 CTRL_OPTIONS_CS(2, odt_rtt_wr),
766#endif
767#if (CONFIG_CHIP_SELECTS_PER_CTRL > 3)
768 CTRL_OPTIONS_CS(3, odt_rtt_norm),
769 CTRL_OPTIONS_CS(3, odt_rtt_wr),
770#endif
771#endif
772 CTRL_OPTIONS(memctl_interleaving),
773 CTRL_OPTIONS(memctl_interleaving_mode),
774 CTRL_OPTIONS_HEX(ba_intlv_ctl),
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530[diff] [blame]775 CTRL_OPTIONS(ecc_mode),
776 CTRL_OPTIONS(ecc_init_using_memctl),
777 CTRL_OPTIONS(dqs_config),
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]778 CTRL_OPTIONS(self_refresh_in_sleep),
779 CTRL_OPTIONS(dynamic_power),
780 CTRL_OPTIONS(data_bus_width),
781 CTRL_OPTIONS(burst_length),
782 CTRL_OPTIONS(cas_latency_override),
783 CTRL_OPTIONS(cas_latency_override_value),
784 CTRL_OPTIONS(use_derated_caslat),
785 CTRL_OPTIONS(additive_latency_override),
786 CTRL_OPTIONS(additive_latency_override_value),
787 CTRL_OPTIONS(clk_adjust),
788 CTRL_OPTIONS(cpo_override),
789 CTRL_OPTIONS(write_data_delay),
790 CTRL_OPTIONS(half_strength_driver_enable),
791 /*
792 * These can probably be changed to 2T_EN and 3T_EN
793 * (using a leading numerical character) without problem
794 */
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530[diff] [blame]795 CTRL_OPTIONS(twot_en),
796 CTRL_OPTIONS(threet_en),
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]797 CTRL_OPTIONS(registered_dimm_en),
798 CTRL_OPTIONS(ap_en),
York Sunb61e0612013-06-25 11:37:47 -0700[diff] [blame]799 CTRL_OPTIONS(x4_en),
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]800 CTRL_OPTIONS(bstopre),
801 CTRL_OPTIONS(wrlvl_override),
802 CTRL_OPTIONS(wrlvl_sample),
803 CTRL_OPTIONS(wrlvl_start),
804 CTRL_OPTIONS(rcw_override),
805 CTRL_OPTIONS(rcw_1),
806 CTRL_OPTIONS(rcw_2),
York Sun57495e42012-10-08 07:44:22 +0000[diff] [blame]807 CTRL_OPTIONS_HEX(ddr_cdr1),
808 CTRL_OPTIONS_HEX(ddr_cdr2),
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530[diff] [blame]809 CTRL_OPTIONS(tcke_clock_pulse_width_ps),
810 CTRL_OPTIONS(tfaw_window_four_activates_ps),
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]811 CTRL_OPTIONS(trwt_override),
812 CTRL_OPTIONS(trwt),
York Sun34e026f2014-03-27 17:54:47 -0700[diff] [blame]813 CTRL_OPTIONS(rtt_override),
814 CTRL_OPTIONS(rtt_override_value),
815 CTRL_OPTIONS(rtt_wr_override_value),
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]816 };
817 static const unsigned int n_opts = ARRAY_SIZE(options);
818
819 print_option_table(options, n_opts, popts);
820}
821
York Sun5614e712013-09-30 09:22:09 -0700[diff] [blame]822#ifdef CONFIG_SYS_FSL_DDR1
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]823void ddr1_spd_dump(const ddr1_spd_eeprom_t *spd)
824{
825 unsigned int i;
826
827 printf("%-3d : %02x %s\n", 0, spd->info_size,
828 " spd->info_size, * 0 # bytes written into serial memory *");
829 printf("%-3d : %02x %s\n", 1, spd->chip_size,
830 " spd->chip_size, * 1 Total # bytes of SPD memory device *");
831 printf("%-3d : %02x %s\n", 2, spd->mem_type,
832 " spd->mem_type, * 2 Fundamental memory type *");
833 printf("%-3d : %02x %s\n", 3, spd->nrow_addr,
834 " spd->nrow_addr, * 3 # of Row Addresses on this assembly *");
835 printf("%-3d : %02x %s\n", 4, spd->ncol_addr,
836 " spd->ncol_addr, * 4 # of Column Addrs on this assembly *");
837 printf("%-3d : %02x %s\n", 5, spd->nrows,
838 " spd->nrows * 5 # of DIMM Banks *");
839 printf("%-3d : %02x %s\n", 6, spd->dataw_lsb,
840 " spd->dataw_lsb, * 6 Data Width lsb of this assembly *");
841 printf("%-3d : %02x %s\n", 7, spd->dataw_msb,
842 " spd->dataw_msb, * 7 Data Width msb of this assembly *");
843 printf("%-3d : %02x %s\n", 8, spd->voltage,
844 " spd->voltage, * 8 Voltage intf std of this assembly *");
845 printf("%-3d : %02x %s\n", 9, spd->clk_cycle,
846 " spd->clk_cycle, * 9 SDRAM Cycle time at CL=X *");
847 printf("%-3d : %02x %s\n", 10, spd->clk_access,
848 " spd->clk_access, * 10 SDRAM Access from Clock at CL=X *");
849 printf("%-3d : %02x %s\n", 11, spd->config,
850 " spd->config, * 11 DIMM Configuration type *");
851 printf("%-3d : %02x %s\n", 12, spd->refresh,
852 " spd->refresh, * 12 Refresh Rate/Type *");
853 printf("%-3d : %02x %s\n", 13, spd->primw,
854 " spd->primw, * 13 Primary SDRAM Width *");
855 printf("%-3d : %02x %s\n", 14, spd->ecw,
856 " spd->ecw, * 14 Error Checking SDRAM width *");
857 printf("%-3d : %02x %s\n", 15, spd->min_delay,
858 " spd->min_delay, * 15 Back to Back Random Access *");
859 printf("%-3d : %02x %s\n", 16, spd->burstl,
860 " spd->burstl, * 16 Burst Lengths Supported *");
861 printf("%-3d : %02x %s\n", 17, spd->nbanks,
862 " spd->nbanks, * 17 # of Banks on Each SDRAM Device *");
863 printf("%-3d : %02x %s\n", 18, spd->cas_lat,
864 " spd->cas_lat, * 18 CAS# Latencies Supported *");
865 printf("%-3d : %02x %s\n", 19, spd->cs_lat,
866 " spd->cs_lat, * 19 Chip Select Latency *");
867 printf("%-3d : %02x %s\n", 20, spd->write_lat,
868 " spd->write_lat, * 20 Write Latency/Recovery *");
869 printf("%-3d : %02x %s\n", 21, spd->mod_attr,
870 " spd->mod_attr, * 21 SDRAM Module Attributes *");
871 printf("%-3d : %02x %s\n", 22, spd->dev_attr,
872 " spd->dev_attr, * 22 SDRAM Device Attributes *");
873 printf("%-3d : %02x %s\n", 23, spd->clk_cycle2,
874 " spd->clk_cycle2, * 23 Min SDRAM Cycle time at CL=X-1 *");
875 printf("%-3d : %02x %s\n", 24, spd->clk_access2,
876 " spd->clk_access2, * 24 SDRAM Access from Clock at CL=X-1 *");
877 printf("%-3d : %02x %s\n", 25, spd->clk_cycle3,
878 " spd->clk_cycle3, * 25 Min SDRAM Cycle time at CL=X-2 *");
879 printf("%-3d : %02x %s\n", 26, spd->clk_access3,
880 " spd->clk_access3, * 26 Max Access from Clock at CL=X-2 *");
881 printf("%-3d : %02x %s\n", 27, spd->trp,
882 " spd->trp, * 27 Min Row Precharge Time (tRP)*");
883 printf("%-3d : %02x %s\n", 28, spd->trrd,
884 " spd->trrd, * 28 Min Row Active to Row Active (tRRD) *");
885 printf("%-3d : %02x %s\n", 29, spd->trcd,
886 " spd->trcd, * 29 Min RAS to CAS Delay (tRCD) *");
887 printf("%-3d : %02x %s\n", 30, spd->tras,
888 " spd->tras, * 30 Minimum RAS Pulse Width (tRAS) *");
889 printf("%-3d : %02x %s\n", 31, spd->bank_dens,
890 " spd->bank_dens, * 31 Density of each bank on module *");
891 printf("%-3d : %02x %s\n", 32, spd->ca_setup,
892 " spd->ca_setup, * 32 Cmd + Addr signal input setup time *");
893 printf("%-3d : %02x %s\n", 33, spd->ca_hold,
894 " spd->ca_hold, * 33 Cmd and Addr signal input hold time *");
895 printf("%-3d : %02x %s\n", 34, spd->data_setup,
896 " spd->data_setup, * 34 Data signal input setup time *");
897 printf("%-3d : %02x %s\n", 35, spd->data_hold,
898 " spd->data_hold, * 35 Data signal input hold time *");
899 printf("%-3d : %02x %s\n", 36, spd->res_36_40[0],
900 " spd->res_36_40[0], * 36 Reserved / tWR *");
901 printf("%-3d : %02x %s\n", 37, spd->res_36_40[1],
902 " spd->res_36_40[1], * 37 Reserved / tWTR *");
903 printf("%-3d : %02x %s\n", 38, spd->res_36_40[2],
904 " spd->res_36_40[2], * 38 Reserved / tRTP *");
905 printf("%-3d : %02x %s\n", 39, spd->res_36_40[3],
906 " spd->res_36_40[3], * 39 Reserved / mem_probe *");
907 printf("%-3d : %02x %s\n", 40, spd->res_36_40[4],
908 " spd->res_36_40[4], * 40 Reserved / trc,trfc extensions *");
909 printf("%-3d : %02x %s\n", 41, spd->trc,
910 " spd->trc, * 41 Min Active to Auto refresh time tRC *");
911 printf("%-3d : %02x %s\n", 42, spd->trfc,
912 " spd->trfc, * 42 Min Auto to Active period tRFC *");
913 printf("%-3d : %02x %s\n", 43, spd->tckmax,
914 " spd->tckmax, * 43 Max device cycle time tCKmax *");
915 printf("%-3d : %02x %s\n", 44, spd->tdqsq,
916 " spd->tdqsq, * 44 Max DQS to DQ skew *");
917 printf("%-3d : %02x %s\n", 45, spd->tqhs,
918 " spd->tqhs, * 45 Max Read DataHold skew tQHS *");
919 printf("%-3d : %02x %s\n", 46, spd->res_46,
920 " spd->res_46, * 46 Reserved/ PLL Relock time *");
921 printf("%-3d : %02x %s\n", 47, spd->dimm_height,
922 " spd->dimm_height * 47 SDRAM DIMM Height *");
923
924 printf("%-3d-%3d: ", 48, 61);
925
926 for (i = 0; i < 14; i++)
927 printf("%02x", spd->res_48_61[i]);
928
929 printf(" * 48-61 IDD in SPD and Reserved space *\n");
930
931 printf("%-3d : %02x %s\n", 62, spd->spd_rev,
932 " spd->spd_rev, * 62 SPD Data Revision Code *");
933 printf("%-3d : %02x %s\n", 63, spd->cksum,
934 " spd->cksum, * 63 Checksum for bytes 0-62 *");
935 printf("%-3d-%3d: ", 64, 71);
936
937 for (i = 0; i < 8; i++)
938 printf("%02x", spd->mid[i]);
939
940 printf("* 64 Mfr's JEDEC ID code per JEP-108E *\n");
941 printf("%-3d : %02x %s\n", 72, spd->mloc,
942 " spd->mloc, * 72 Manufacturing Location *");
943
944 printf("%-3d-%3d: >>", 73, 90);
945
946 for (i = 0; i < 18; i++)
947 printf("%c", spd->mpart[i]);
948
949 printf("<<* 73 Manufacturer's Part Number *\n");
950
951 printf("%-3d-%3d: %02x %02x %s\n", 91, 92, spd->rev[0], spd->rev[1],
952 "* 91 Revision Code *");
953 printf("%-3d-%3d: %02x %02x %s\n", 93, 94, spd->mdate[0], spd->mdate[1],
954 "* 93 Manufacturing Date *");
955 printf("%-3d-%3d: ", 95, 98);
956
957 for (i = 0; i < 4; i++)
958 printf("%02x", spd->sernum[i]);
959
960 printf("* 95 Assembly Serial Number *\n");
961
962 printf("%-3d-%3d: ", 99, 127);
963
964 for (i = 0; i < 27; i++)
965 printf("%02x", spd->mspec[i]);
966
967 printf("* 99 Manufacturer Specific Data *\n");
968}
969#endif
970
York Sun5614e712013-09-30 09:22:09 -0700[diff] [blame]971#ifdef CONFIG_SYS_FSL_DDR2
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]972void ddr2_spd_dump(const ddr2_spd_eeprom_t *spd)
973{
974 unsigned int i;
975
976 printf("%-3d : %02x %s\n", 0, spd->info_size,
977 " spd->info_size, * 0 # bytes written into serial memory *");
978 printf("%-3d : %02x %s\n", 1, spd->chip_size,
979 " spd->chip_size, * 1 Total # bytes of SPD memory device *");
980 printf("%-3d : %02x %s\n", 2, spd->mem_type,
981 " spd->mem_type, * 2 Fundamental memory type *");
982 printf("%-3d : %02x %s\n", 3, spd->nrow_addr,
983 " spd->nrow_addr, * 3 # of Row Addresses on this assembly *");
984 printf("%-3d : %02x %s\n", 4, spd->ncol_addr,
985 " spd->ncol_addr, * 4 # of Column Addrs on this assembly *");
986 printf("%-3d : %02x %s\n", 5, spd->mod_ranks,
987 " spd->mod_ranks * 5 # of Module Rows on this assembly *");
988 printf("%-3d : %02x %s\n", 6, spd->dataw,
989 " spd->dataw, * 6 Data Width of this assembly *");
990 printf("%-3d : %02x %s\n", 7, spd->res_7,
991 " spd->res_7, * 7 Reserved *");
992 printf("%-3d : %02x %s\n", 8, spd->voltage,
993 " spd->voltage, * 8 Voltage intf std of this assembly *");
994 printf("%-3d : %02x %s\n", 9, spd->clk_cycle,
995 " spd->clk_cycle, * 9 SDRAM Cycle time at CL=X *");
996 printf("%-3d : %02x %s\n", 10, spd->clk_access,
997 " spd->clk_access, * 10 SDRAM Access from Clock at CL=X *");
998 printf("%-3d : %02x %s\n", 11, spd->config,
999 " spd->config, * 11 DIMM Configuration type *");
1000 printf("%-3d : %02x %s\n", 12, spd->refresh,
1001 " spd->refresh, * 12 Refresh Rate/Type *");
1002 printf("%-3d : %02x %s\n", 13, spd->primw,
1003 " spd->primw, * 13 Primary SDRAM Width *");
1004 printf("%-3d : %02x %s\n", 14, spd->ecw,
1005 " spd->ecw, * 14 Error Checking SDRAM width *");
1006 printf("%-3d : %02x %s\n", 15, spd->res_15,
1007 " spd->res_15, * 15 Reserved *");
1008 printf("%-3d : %02x %s\n", 16, spd->burstl,
1009 " spd->burstl, * 16 Burst Lengths Supported *");
1010 printf("%-3d : %02x %s\n", 17, spd->nbanks,
1011 " spd->nbanks, * 17 # of Banks on Each SDRAM Device *");
1012 printf("%-3d : %02x %s\n", 18, spd->cas_lat,
1013 " spd->cas_lat, * 18 CAS# Latencies Supported *");
1014 printf("%-3d : %02x %s\n", 19, spd->mech_char,
1015 " spd->mech_char, * 19 Mechanical Characteristics *");
1016 printf("%-3d : %02x %s\n", 20, spd->dimm_type,
1017 " spd->dimm_type, * 20 DIMM type *");
1018 printf("%-3d : %02x %s\n", 21, spd->mod_attr,
1019 " spd->mod_attr, * 21 SDRAM Module Attributes *");
1020 printf("%-3d : %02x %s\n", 22, spd->dev_attr,
1021 " spd->dev_attr, * 22 SDRAM Device Attributes *");
1022 printf("%-3d : %02x %s\n", 23, spd->clk_cycle2,
1023 " spd->clk_cycle2, * 23 Min SDRAM Cycle time at CL=X-1 *");
1024 printf("%-3d : %02x %s\n", 24, spd->clk_access2,
1025 " spd->clk_access2, * 24 SDRAM Access from Clock at CL=X-1 *");
1026 printf("%-3d : %02x %s\n", 25, spd->clk_cycle3,
1027 " spd->clk_cycle3, * 25 Min SDRAM Cycle time at CL=X-2 *");
1028 printf("%-3d : %02x %s\n", 26, spd->clk_access3,
1029 " spd->clk_access3, * 26 Max Access from Clock at CL=X-2 *");
1030 printf("%-3d : %02x %s\n", 27, spd->trp,
1031 " spd->trp, * 27 Min Row Precharge Time (tRP)*");
1032 printf("%-3d : %02x %s\n", 28, spd->trrd,
1033 " spd->trrd, * 28 Min Row Active to Row Active (tRRD) *");
1034 printf("%-3d : %02x %s\n", 29, spd->trcd,
1035 " spd->trcd, * 29 Min RAS to CAS Delay (tRCD) *");
1036 printf("%-3d : %02x %s\n", 30, spd->tras,
1037 " spd->tras, * 30 Minimum RAS Pulse Width (tRAS) *");
1038 printf("%-3d : %02x %s\n", 31, spd->rank_dens,
1039 " spd->rank_dens, * 31 Density of each rank on module *");
1040 printf("%-3d : %02x %s\n", 32, spd->ca_setup,
1041 " spd->ca_setup, * 32 Cmd + Addr signal input setup time *");
1042 printf("%-3d : %02x %s\n", 33, spd->ca_hold,
1043 " spd->ca_hold, * 33 Cmd and Addr signal input hold time *");
1044 printf("%-3d : %02x %s\n", 34, spd->data_setup,
1045 " spd->data_setup, * 34 Data signal input setup time *");
1046 printf("%-3d : %02x %s\n", 35, spd->data_hold,
1047 " spd->data_hold, * 35 Data signal input hold time *");
1048 printf("%-3d : %02x %s\n", 36, spd->twr,
1049 " spd->twr, * 36 Write Recovery time tWR *");
1050 printf("%-3d : %02x %s\n", 37, spd->twtr,
1051 " spd->twtr, * 37 Int write to read delay tWTR *");
1052 printf("%-3d : %02x %s\n", 38, spd->trtp,
1053 " spd->trtp, * 38 Int read to precharge delay tRTP *");
1054 printf("%-3d : %02x %s\n", 39, spd->mem_probe,
1055 " spd->mem_probe, * 39 Mem analysis probe characteristics *");
1056 printf("%-3d : %02x %s\n", 40, spd->trctrfc_ext,
1057 " spd->trctrfc_ext, * 40 Extensions to trc and trfc *");
1058 printf("%-3d : %02x %s\n", 41, spd->trc,
1059 " spd->trc, * 41 Min Active to Auto refresh time tRC *");
1060 printf("%-3d : %02x %s\n", 42, spd->trfc,
1061 " spd->trfc, * 42 Min Auto to Active period tRFC *");
1062 printf("%-3d : %02x %s\n", 43, spd->tckmax,
1063 " spd->tckmax, * 43 Max device cycle time tCKmax *");
1064 printf("%-3d : %02x %s\n", 44, spd->tdqsq,
1065 " spd->tdqsq, * 44 Max DQS to DQ skew *");
1066 printf("%-3d : %02x %s\n", 45, spd->tqhs,
1067 " spd->tqhs, * 45 Max Read DataHold skew tQHS *");
1068 printf("%-3d : %02x %s\n", 46, spd->pll_relock,
1069 " spd->pll_relock, * 46 PLL Relock time *");
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530[diff] [blame]1070 printf("%-3d : %02x %s\n", 47, spd->t_casemax,
1071 " spd->t_casemax, * 47 t_casemax *");
1072 printf("%-3d : %02x %s\n", 48, spd->psi_ta_dram,
1073 " spd->psi_ta_dram, * 48 Thermal Resistance of DRAM Package "
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]1074 "from Top (Case) to Ambient (Psi T-A DRAM) *");
1075 printf("%-3d : %02x %s\n", 49, spd->dt0_mode,
1076 " spd->dt0_mode, * 49 DRAM Case Temperature Rise from "
1077 "Ambient due to Activate-Precharge/Mode Bits "
1078 "(DT0/Mode Bits) *)");
1079 printf("%-3d : %02x %s\n", 50, spd->dt2n_dt2q,
1080 " spd->dt2n_dt2q, * 50 DRAM Case Temperature Rise from "
1081 "Ambient due to Precharge/Quiet Standby "
1082 "(DT2N/DT2Q) *");
1083 printf("%-3d : %02x %s\n", 51, spd->dt2p,
1084 " spd->dt2p, * 51 DRAM Case Temperature Rise from "
1085 "Ambient due to Precharge Power-Down (DT2P) *");
1086 printf("%-3d : %02x %s\n", 52, spd->dt3n,
1087 " spd->dt3n, * 52 DRAM Case Temperature Rise from "
1088 "Ambient due to Active Standby (DT3N) *");
1089 printf("%-3d : %02x %s\n", 53, spd->dt3pfast,
1090 " spd->dt3pfast, * 53 DRAM Case Temperature Rise from "
1091 "Ambient due to Active Power-Down with Fast PDN Exit "
1092 "(DT3Pfast) *");
1093 printf("%-3d : %02x %s\n", 54, spd->dt3pslow,
1094 " spd->dt3pslow, * 54 DRAM Case Temperature Rise from "
1095 "Ambient due to Active Power-Down with Slow PDN Exit "
1096 "(DT3Pslow) *");
1097 printf("%-3d : %02x %s\n", 55, spd->dt4r_dt4r4w,
1098 " spd->dt4r_dt4r4w, * 55 DRAM Case Temperature Rise from "
1099 "Ambient due to Page Open Burst Read/DT4R4W Mode Bit "
1100 "(DT4R/DT4R4W Mode Bit) *");
1101 printf("%-3d : %02x %s\n", 56, spd->dt5b,
1102 " spd->dt5b, * 56 DRAM Case Temperature Rise from "
1103 "Ambient due to Burst Refresh (DT5B) *");
1104 printf("%-3d : %02x %s\n", 57, spd->dt7,
1105 " spd->dt7, * 57 DRAM Case Temperature Rise from "
1106 "Ambient due to Bank Interleave Reads with "
1107 "Auto-Precharge (DT7) *");
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530[diff] [blame]1108 printf("%-3d : %02x %s\n", 58, spd->psi_ta_pll,
1109 " spd->psi_ta_pll, * 58 Thermal Resistance of PLL Package form"
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]1110 " Top (Case) to Ambient (Psi T-A PLL) *");
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530[diff] [blame]1111 printf("%-3d : %02x %s\n", 59, spd->psi_ta_reg,
1112 " spd->psi_ta_reg, * 59 Thermal Reisitance of Register Package"
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]1113 " from Top (Case) to Ambient (Psi T-A Register) *");
1114 printf("%-3d : %02x %s\n", 60, spd->dtpllactive,
1115 " spd->dtpllactive, * 60 PLL Case Temperature Rise from "
1116 "Ambient due to PLL Active (DT PLL Active) *");
1117 printf("%-3d : %02x %s\n", 61, spd->dtregact,
1118 " spd->dtregact, "
1119 "* 61 Register Case Temperature Rise from Ambient due to "
1120 "Register Active/Mode Bit (DT Register Active/Mode Bit) *");
1121 printf("%-3d : %02x %s\n", 62, spd->spd_rev,
1122 " spd->spd_rev, * 62 SPD Data Revision Code *");
1123 printf("%-3d : %02x %s\n", 63, spd->cksum,
1124 " spd->cksum, * 63 Checksum for bytes 0-62 *");
1125
1126 printf("%-3d-%3d: ", 64, 71);
1127
1128 for (i = 0; i < 8; i++)
1129 printf("%02x", spd->mid[i]);
1130
1131 printf("* 64 Mfr's JEDEC ID code per JEP-108E *\n");
1132
1133 printf("%-3d : %02x %s\n", 72, spd->mloc,
1134 " spd->mloc, * 72 Manufacturing Location *");
1135
1136 printf("%-3d-%3d: >>", 73, 90);
1137 for (i = 0; i < 18; i++)
1138 printf("%c", spd->mpart[i]);
1139
1140
1141 printf("<<* 73 Manufacturer's Part Number *\n");
1142
1143 printf("%-3d-%3d: %02x %02x %s\n", 91, 92, spd->rev[0], spd->rev[1],
1144 "* 91 Revision Code *");
1145 printf("%-3d-%3d: %02x %02x %s\n", 93, 94, spd->mdate[0], spd->mdate[1],
1146 "* 93 Manufacturing Date *");
1147 printf("%-3d-%3d: ", 95, 98);
1148
1149 for (i = 0; i < 4; i++)
1150 printf("%02x", spd->sernum[i]);
1151
1152 printf("* 95 Assembly Serial Number *\n");
1153
1154 printf("%-3d-%3d: ", 99, 127);
1155 for (i = 0; i < 27; i++)
1156 printf("%02x", spd->mspec[i]);
1157
1158
1159 printf("* 99 Manufacturer Specific Data *\n");
1160}
1161#endif
1162
York Sun5614e712013-09-30 09:22:09 -0700[diff] [blame]1163#ifdef CONFIG_SYS_FSL_DDR3
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]1164void ddr3_spd_dump(const ddr3_spd_eeprom_t *spd)
1165{
1166 unsigned int i;
1167
1168 /* General Section: Bytes 0-59 */
1169
York Sun1d083ff2012-08-17 08:22:43 +0000[diff] [blame]1170#define PRINT_NXS(x, y, z...) printf("%-3d : %02x " z "\n", x, (u8)y);
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]1171#define PRINT_NNXXS(n0, n1, x0, x1, s) \
1172 printf("%-3d-%3d: %02x %02x " s "\n", n0, n1, x0, x1);
1173
1174 PRINT_NXS(0, spd->info_size_crc,
1175 "info_size_crc bytes written into serial memory, "
1176 "CRC coverage");
1177 PRINT_NXS(1, spd->spd_rev,
1178 "spd_rev SPD Revision");
1179 PRINT_NXS(2, spd->mem_type,
1180 "mem_type Key Byte / DRAM Device Type");
1181 PRINT_NXS(3, spd->module_type,
1182 "module_type Key Byte / Module Type");
1183 PRINT_NXS(4, spd->density_banks,
1184 "density_banks SDRAM Density and Banks");
1185 PRINT_NXS(5, spd->addressing,
1186 "addressing SDRAM Addressing");
1187 PRINT_NXS(6, spd->module_vdd,
1188 "module_vdd Module Nominal Voltage, VDD");
1189 PRINT_NXS(7, spd->organization,
1190 "organization Module Organization");
1191 PRINT_NXS(8, spd->bus_width,
1192 "bus_width Module Memory Bus Width");
1193 PRINT_NXS(9, spd->ftb_div,
1194 "ftb_div Fine Timebase (FTB) Dividend / Divisor");
1195 PRINT_NXS(10, spd->mtb_dividend,
1196 "mtb_dividend Medium Timebase (MTB) Dividend");
1197 PRINT_NXS(11, spd->mtb_divisor,
1198 "mtb_divisor Medium Timebase (MTB) Divisor");
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530[diff] [blame]1199 PRINT_NXS(12, spd->tck_min,
1200 "tck_min SDRAM Minimum Cycle Time");
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]1201 PRINT_NXS(13, spd->res_13,
1202 "res_13 Reserved");
1203 PRINT_NXS(14, spd->caslat_lsb,
1204 "caslat_lsb CAS Latencies Supported, LSB");
1205 PRINT_NXS(15, spd->caslat_msb,
1206 "caslat_msb CAS Latencies Supported, MSB");
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530[diff] [blame]1207 PRINT_NXS(16, spd->taa_min,
1208 "taa_min Min CAS Latency Time");
1209 PRINT_NXS(17, spd->twr_min,
1210 "twr_min Min Write REcovery Time");
1211 PRINT_NXS(18, spd->trcd_min,
1212 "trcd_min Min RAS# to CAS# Delay Time");
1213 PRINT_NXS(19, spd->trrd_min,
1214 "trrd_min Min Row Active to Row Active Delay Time");
1215 PRINT_NXS(20, spd->trp_min,
1216 "trp_min Min Row Precharge Delay Time");
1217 PRINT_NXS(21, spd->tras_trc_ext,
1218 "tras_trc_ext Upper Nibbles for tRAS and tRC");
1219 PRINT_NXS(22, spd->tras_min_lsb,
1220 "tras_min_lsb Min Active to Precharge Delay Time, LSB");
1221 PRINT_NXS(23, spd->trc_min_lsb,
1222 "trc_min_lsb Min Active to Active/Refresh Delay Time, LSB");
1223 PRINT_NXS(24, spd->trfc_min_lsb,
1224 "trfc_min_lsb Min Refresh Recovery Delay Time LSB");
1225 PRINT_NXS(25, spd->trfc_min_msb,
1226 "trfc_min_msb Min Refresh Recovery Delay Time MSB");
1227 PRINT_NXS(26, spd->twtr_min,
1228 "twtr_min Min Internal Write to Read Command Delay Time");
1229 PRINT_NXS(27, spd->trtp_min,
1230 "trtp_min "
1231 "Min Internal Read to Precharge Command Delay Time");
1232 PRINT_NXS(28, spd->tfaw_msb,
1233 "tfaw_msb Upper Nibble for tFAW");
1234 PRINT_NXS(29, spd->tfaw_min,
1235 "tfaw_min Min Four Activate Window Delay Time");
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]1236 PRINT_NXS(30, spd->opt_features,
1237 "opt_features SDRAM Optional Features");
1238 PRINT_NXS(31, spd->therm_ref_opt,
1239 "therm_ref_opt SDRAM Thermal and Refresh Opts");
1240 PRINT_NXS(32, spd->therm_sensor,
1241 "therm_sensor SDRAM Thermal Sensor");
1242 PRINT_NXS(33, spd->device_type,
1243 "device_type SDRAM Device Type");
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530[diff] [blame]1244 PRINT_NXS(34, spd->fine_tck_min,
1245 "fine_tck_min Fine offset for tCKmin");
1246 PRINT_NXS(35, spd->fine_taa_min,
1247 "fine_taa_min Fine offset for tAAmin");
1248 PRINT_NXS(36, spd->fine_trcd_min,
1249 "fine_trcd_min Fine offset for tRCDmin");
1250 PRINT_NXS(37, spd->fine_trp_min,
1251 "fine_trp_min Fine offset for tRPmin");
1252 PRINT_NXS(38, spd->fine_trc_min,
1253 "fine_trc_min Fine offset for tRCmin");
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]1254
York Sun73b53962012-08-17 08:22:37 +0000[diff] [blame]1255 printf("%-3d-%3d: ", 39, 59); /* Reserved, General Section */
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]1256
York Sun73b53962012-08-17 08:22:37 +0000[diff] [blame]1257 for (i = 39; i <= 59; i++)
1258 printf("%02x ", spd->res_39_59[i - 39]);
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]1259
1260 puts("\n");
1261
1262 switch (spd->module_type) {
1263 case 0x02: /* UDIMM */
1264 case 0x03: /* SO-DIMM */
1265 case 0x04: /* Micro-DIMM */
1266 case 0x06: /* Mini-UDIMM */
1267 PRINT_NXS(60, spd->mod_section.unbuffered.mod_height,
1268 "mod_height (Unbuffered) Module Nominal Height");
1269 PRINT_NXS(61, spd->mod_section.unbuffered.mod_thickness,
1270 "mod_thickness (Unbuffered) Module Maximum Thickness");
1271 PRINT_NXS(62, spd->mod_section.unbuffered.ref_raw_card,
1272 "ref_raw_card (Unbuffered) Reference Raw Card Used");
1273 PRINT_NXS(63, spd->mod_section.unbuffered.addr_mapping,
1274 "addr_mapping (Unbuffered) Address mapping from "
1275 "Edge Connector to DRAM");
1276 break;
1277 case 0x01: /* RDIMM */
1278 case 0x05: /* Mini-RDIMM */
1279 PRINT_NXS(60, spd->mod_section.registered.mod_height,
1280 "mod_height (Registered) Module Nominal Height");
1281 PRINT_NXS(61, spd->mod_section.registered.mod_thickness,
1282 "mod_thickness (Registered) Module Maximum Thickness");
1283 PRINT_NXS(62, spd->mod_section.registered.ref_raw_card,
1284 "ref_raw_card (Registered) Reference Raw Card Used");
1285 PRINT_NXS(63, spd->mod_section.registered.modu_attr,
1286 "modu_attr (Registered) DIMM Module Attributes");
1287 PRINT_NXS(64, spd->mod_section.registered.thermal,
1288 "thermal (Registered) Thermal Heat "
1289 "Spreader Solution");
1290 PRINT_NXS(65, spd->mod_section.registered.reg_id_lo,
1291 "reg_id_lo (Registered) Register Manufacturer ID "
1292 "Code, LSB");
1293 PRINT_NXS(66, spd->mod_section.registered.reg_id_hi,
1294 "reg_id_hi (Registered) Register Manufacturer ID "
1295 "Code, MSB");
1296 PRINT_NXS(67, spd->mod_section.registered.reg_rev,
1297 "reg_rev (Registered) Register "
1298 "Revision Number");
1299 PRINT_NXS(68, spd->mod_section.registered.reg_type,
1300 "reg_type (Registered) Register Type");
1301 for (i = 69; i <= 76; i++) {
1302 printf("%-3d : %02x rcw[%d]\n", i,
1303 spd->mod_section.registered.rcw[i-69], i-69);
1304 }
1305 break;
1306 default:
1307 /* Module-specific Section, Unsupported Module Type */
1308 printf("%-3d-%3d: ", 60, 116);
1309
1310 for (i = 60; i <= 116; i++)
1311 printf("%02x", spd->mod_section.uc[i - 60]);
1312
1313 break;
1314 }
1315
1316 /* Unique Module ID: Bytes 117-125 */
1317 PRINT_NXS(117, spd->mmid_lsb, "Module MfgID Code LSB - JEP-106");
1318 PRINT_NXS(118, spd->mmid_msb, "Module MfgID Code MSB - JEP-106");
1319 PRINT_NXS(119, spd->mloc, "Mfg Location");
1320 PRINT_NNXXS(120, 121, spd->mdate[0], spd->mdate[1], "Mfg Date");
1321
1322 printf("%-3d-%3d: ", 122, 125);
1323
1324 for (i = 122; i <= 125; i++)
1325 printf("%02x ", spd->sernum[i - 122]);
1326 printf(" Module Serial Number\n");
1327
1328 /* CRC: Bytes 126-127 */
1329 PRINT_NNXXS(126, 127, spd->crc[0], spd->crc[1], " SPD CRC");
1330
1331 /* Other Manufacturer Fields and User Space: Bytes 128-255 */
1332 printf("%-3d-%3d: ", 128, 145);
1333 for (i = 128; i <= 145; i++)
1334 printf("%02x ", spd->mpart[i - 128]);
1335 printf(" Mfg's Module Part Number\n");
1336
1337 PRINT_NNXXS(146, 147, spd->mrev[0], spd->mrev[1],
1338 "Module Revision code");
1339
1340 PRINT_NXS(148, spd->dmid_lsb, "DRAM MfgID Code LSB - JEP-106");
1341 PRINT_NXS(149, spd->dmid_msb, "DRAM MfgID Code MSB - JEP-106");
1342
1343 printf("%-3d-%3d: ", 150, 175);
1344 for (i = 150; i <= 175; i++)
1345 printf("%02x ", spd->msd[i - 150]);
1346 printf(" Mfg's Specific Data\n");
1347
1348 printf("%-3d-%3d: ", 176, 255);
1349 for (i = 176; i <= 255; i++)
1350 printf("%02x", spd->cust[i - 176]);
1351 printf(" Mfg's Specific Data\n");
1352
1353}
1354#endif
1355
York Sun34e026f2014-03-27 17:54:47 -0700[diff] [blame]1356#ifdef CONFIG_SYS_FSL_DDR4
1357void ddr4_spd_dump(const struct ddr4_spd_eeprom_s *spd)
1358{
1359 unsigned int i;
1360
1361 /* General Section: Bytes 0-127 */
1362
1363#define PRINT_NXS(x, y, z...) printf("%-3d : %02x " z "\n", x, (u8)y);
1364#define PRINT_NNXXS(n0, n1, x0, x1, s) \
1365 printf("%-3d-%3d: %02x %02x " s "\n", n0, n1, x0, x1);
1366
1367 PRINT_NXS(0, spd->info_size_crc,
1368 "info_size_crc bytes written into serial memory, CRC coverage");
1369 PRINT_NXS(1, spd->spd_rev,
1370 "spd_rev SPD Revision");
1371 PRINT_NXS(2, spd->mem_type,
1372 "mem_type Key Byte / DRAM Device Type");
1373 PRINT_NXS(3, spd->module_type,
1374 "module_type Key Byte / Module Type");
1375 PRINT_NXS(4, spd->density_banks,
1376 "density_banks SDRAM Density and Banks");
1377 PRINT_NXS(5, spd->addressing,
1378 "addressing SDRAM Addressing");
1379 PRINT_NXS(6, spd->package_type,
1380 "package_type Package type");
1381 PRINT_NXS(7, spd->opt_feature,
1382 "opt_feature Optional features");
1383 PRINT_NXS(8, spd->thermal_ref,
1384 "thermal_ref Thermal and Refresh options");
1385 PRINT_NXS(9, spd->oth_opt_features,
1386 "oth_opt_features Other SDRAM optional features");
1387 PRINT_NXS(10, spd->res_10,
1388 "res_10 Reserved");
1389 PRINT_NXS(11, spd->module_vdd,
1390 "module_vdd Module Nominal Voltage, VDD");
1391 PRINT_NXS(12, spd->organization,
1392 "organization Module Organization");
1393 PRINT_NXS(13, spd->bus_width,
1394 "bus_width Module Memory Bus Width");
1395 PRINT_NXS(14, spd->therm_sensor,
1396 "therm_sensor Module Thermal Sensor");
1397 PRINT_NXS(15, spd->ext_type,
1398 "ext_type Extended module type");
1399 PRINT_NXS(16, spd->res_16,
1400 "res_16 Reserved");
1401 PRINT_NXS(17, spd->timebases,
1402 "timebases MTb and FTB");
1403 PRINT_NXS(18, spd->tck_min,
1404 "tck_min tCKAVGmin");
1405 PRINT_NXS(19, spd->tck_max,
1406 "tck_max TCKAVGmax");
1407 PRINT_NXS(20, spd->caslat_b1,
1408 "caslat_b1 CAS latencies, 1st byte");
1409 PRINT_NXS(21, spd->caslat_b2,
1410 "caslat_b2 CAS latencies, 2nd byte");
1411 PRINT_NXS(22, spd->caslat_b3,
1412 "caslat_b3 CAS latencies, 3rd byte ");
1413 PRINT_NXS(23, spd->caslat_b4,
1414 "caslat_b4 CAS latencies, 4th byte");
1415 PRINT_NXS(24, spd->taa_min,
1416 "taa_min Min CAS Latency Time");
1417 PRINT_NXS(25, spd->trcd_min,
1418 "trcd_min Min RAS# to CAS# Delay Time");
1419 PRINT_NXS(26, spd->trp_min,
1420 "trp_min Min Row Precharge Delay Time");
1421 PRINT_NXS(27, spd->tras_trc_ext,
1422 "tras_trc_ext Upper Nibbles for tRAS and tRC");
1423 PRINT_NXS(28, spd->tras_min_lsb,
1424 "tras_min_lsb tRASmin, lsb");
1425 PRINT_NXS(29, spd->trc_min_lsb,
1426 "trc_min_lsb tRCmin, lsb");
1427 PRINT_NXS(30, spd->trfc1_min_lsb,
1428 "trfc1_min_lsb Min Refresh Recovery Delay Time, LSB");
1429 PRINT_NXS(31, spd->trfc1_min_msb,
1430 "trfc1_min_msb Min Refresh Recovery Delay Time, MSB ");
1431 PRINT_NXS(32, spd->trfc2_min_lsb,
1432 "trfc2_min_lsb Min Refresh Recovery Delay Time, LSB");
1433 PRINT_NXS(33, spd->trfc2_min_msb,
1434 "trfc2_min_msb Min Refresh Recovery Delay Time, MSB");
1435 PRINT_NXS(34, spd->trfc4_min_lsb,
1436 "trfc4_min_lsb Min Refresh Recovery Delay Time, LSB");
1437 PRINT_NXS(35, spd->trfc4_min_msb,
1438 "trfc4_min_msb Min Refresh Recovery Delay Time, MSB");
1439 PRINT_NXS(36, spd->tfaw_msb,
1440 "tfaw_msb Upper Nibble for tFAW");
1441 PRINT_NXS(37, spd->tfaw_min,
1442 "tfaw_min tFAW, lsb");
1443 PRINT_NXS(38, spd->trrds_min,
1444 "trrds_min tRRD_Smin, MTB");
1445 PRINT_NXS(39, spd->trrdl_min,
1446 "trrdl_min tRRD_Lmin, MTB");
1447 PRINT_NXS(40, spd->tccdl_min,
1448 "tccdl_min tCCS_Lmin, MTB");
1449
1450 printf("%-3d-%3d: ", 41, 59); /* Reserved, General Section */
1451 for (i = 41; i <= 59; i++)
1452 printf("%02x ", spd->res_41[i - 41]);
1453
1454 puts("\n");
1455 printf("%-3d-%3d: ", 60, 77);
1456 for (i = 60; i <= 77; i++)
1457 printf("%02x ", spd->mapping[i - 60]);
1458 puts(" mapping[] Connector to SDRAM bit map\n");
1459
1460 PRINT_NXS(117, spd->fine_tccdl_min,
1461 "fine_tccdl_min Fine offset for tCCD_Lmin");
1462 PRINT_NXS(118, spd->fine_trrdl_min,
1463 "fine_trrdl_min Fine offset for tRRD_Lmin");
1464 PRINT_NXS(119, spd->fine_trrds_min,
1465 "fine_trrds_min Fine offset for tRRD_Smin");
1466 PRINT_NXS(120, spd->fine_trc_min,
1467 "fine_trc_min Fine offset for tRCmin");
1468 PRINT_NXS(121, spd->fine_trp_min,
1469 "fine_trp_min Fine offset for tRPmin");
1470 PRINT_NXS(122, spd->fine_trcd_min,
1471 "fine_trcd_min Fine offset for tRCDmin");
1472 PRINT_NXS(123, spd->fine_taa_min,
1473 "fine_taa_min Fine offset for tAAmin");
1474 PRINT_NXS(124, spd->fine_tck_max,
1475 "fine_tck_max Fine offset for tCKAVGmax");
1476 PRINT_NXS(125, spd->fine_tck_min,
1477 "fine_tck_min Fine offset for tCKAVGmin");
1478
1479 /* CRC: Bytes 126-127 */
1480 PRINT_NNXXS(126, 127, spd->crc[0], spd->crc[1], " SPD CRC");
1481
1482 switch (spd->module_type) {
1483 case 0x02: /* UDIMM */
1484 case 0x03: /* SO-DIMM */
1485 PRINT_NXS(128, spd->mod_section.unbuffered.mod_height,
1486 "mod_height (Unbuffered) Module Nominal Height");
1487 PRINT_NXS(129, spd->mod_section.unbuffered.mod_thickness,
1488 "mod_thickness (Unbuffered) Module Maximum Thickness");
1489 PRINT_NXS(130, spd->mod_section.unbuffered.ref_raw_card,
1490 "ref_raw_card (Unbuffered) Reference Raw Card Used");
1491 PRINT_NXS(131, spd->mod_section.unbuffered.addr_mapping,
1492 "addr_mapping (Unbuffered) Address mapping from Edge Connector to DRAM");
1493 PRINT_NNXXS(254, 255, spd->mod_section.unbuffered.crc[0],
1494 spd->mod_section.unbuffered.crc[1], " Module CRC");
1495 break;
1496 case 0x01: /* RDIMM */
1497 PRINT_NXS(128, spd->mod_section.registered.mod_height,
1498 "mod_height (Registered) Module Nominal Height");
1499 PRINT_NXS(129, spd->mod_section.registered.mod_thickness,
1500 "mod_thickness (Registered) Module Maximum Thickness");
1501 PRINT_NXS(130, spd->mod_section.registered.ref_raw_card,
1502 "ref_raw_card (Registered) Reference Raw Card Used");
1503 PRINT_NXS(131, spd->mod_section.registered.modu_attr,
1504 "modu_attr (Registered) DIMM Module Attributes");
1505 PRINT_NXS(132, spd->mod_section.registered.thermal,
1506 "thermal (Registered) Thermal Heat Spreader Solution");
1507 PRINT_NXS(133, spd->mod_section.registered.reg_id_lo,
1508 "reg_id_lo (Registered) Register Manufacturer ID Code, LSB");
1509 PRINT_NXS(134, spd->mod_section.registered.reg_id_hi,
1510 "reg_id_hi (Registered) Register Manufacturer ID Code, MSB");
1511 PRINT_NXS(135, spd->mod_section.registered.reg_rev,
1512 "reg_rev (Registered) Register Revision Number");
1513 PRINT_NXS(136, spd->mod_section.registered.reg_map,
1514 "reg_map (Registered) Address mapping");
1515 PRINT_NNXXS(254, 255, spd->mod_section.registered.crc[0],
1516 spd->mod_section.registered.crc[1], " Module CRC");
1517 break;
1518 case 0x04: /* LRDIMM */
1519 PRINT_NXS(128, spd->mod_section.loadreduced.mod_height,
1520 "mod_height (Loadreduced) Module Nominal Height");
1521 PRINT_NXS(129, spd->mod_section.loadreduced.mod_thickness,
1522 "mod_thickness (Loadreduced) Module Maximum Thickness");
1523 PRINT_NXS(130, spd->mod_section.loadreduced.ref_raw_card,
1524 "ref_raw_card (Loadreduced) Reference Raw Card Used");
1525 PRINT_NXS(131, spd->mod_section.loadreduced.modu_attr,
1526 "modu_attr (Loadreduced) DIMM Module Attributes");
1527 PRINT_NXS(132, spd->mod_section.loadreduced.thermal,
1528 "thermal (Loadreduced) Thermal Heat Spreader Solution");
1529 PRINT_NXS(133, spd->mod_section.loadreduced.reg_id_lo,
1530 "reg_id_lo (Loadreduced) Register Manufacturer ID Code, LSB");
1531 PRINT_NXS(134, spd->mod_section.loadreduced.reg_id_hi,
1532 "reg_id_hi (Loadreduced) Register Manufacturer ID Code, MSB");
1533 PRINT_NXS(135, spd->mod_section.loadreduced.reg_rev,
1534 "reg_rev (Loadreduced) Register Revision Number");
1535 PRINT_NXS(136, spd->mod_section.loadreduced.reg_map,
1536 "reg_map (Loadreduced) Address mapping");
1537 PRINT_NXS(137, spd->mod_section.loadreduced.reg_drv,
1538 "reg_drv (Loadreduced) Reg output drive strength");
1539 PRINT_NXS(138, spd->mod_section.loadreduced.reg_drv_ck,
1540 "reg_drv_ck (Loadreduced) Reg output drive strength for CK");
1541 PRINT_NXS(139, spd->mod_section.loadreduced.data_buf_rev,
1542 "data_buf_rev (Loadreduced) Data Buffer Revision Numbe");
1543 PRINT_NXS(140, spd->mod_section.loadreduced.vrefqe_r0,
1544 "vrefqe_r0 (Loadreduced) DRAM VrefDQ for Package Rank 0");
1545 PRINT_NXS(141, spd->mod_section.loadreduced.vrefqe_r1,
1546 "vrefqe_r1 (Loadreduced) DRAM VrefDQ for Package Rank 1");
1547 PRINT_NXS(142, spd->mod_section.loadreduced.vrefqe_r2,
1548 "vrefqe_r2 (Loadreduced) DRAM VrefDQ for Package Rank 2");
1549 PRINT_NXS(143, spd->mod_section.loadreduced.vrefqe_r3,
1550 "vrefqe_r3 (Loadreduced) DRAM VrefDQ for Package Rank 3");
1551 PRINT_NXS(144, spd->mod_section.loadreduced.data_intf,
1552 "data_intf (Loadreduced) Data Buffer VrefDQ for DRAM Interface");
1553 PRINT_NXS(145, spd->mod_section.loadreduced.data_drv_1866,
1554 "data_drv_1866 (Loadreduced) Data Buffer MDQ Drive Strength and RTT");
1555 PRINT_NXS(146, spd->mod_section.loadreduced.data_drv_2400,
1556 "data_drv_2400 (Loadreduced) Data Buffer MDQ Drive Strength and RTT");
1557 PRINT_NXS(147, spd->mod_section.loadreduced.data_drv_3200,
1558 "data_drv_3200 (Loadreduced) Data Buffer MDQ Drive Strength and RTT");
1559 PRINT_NXS(148, spd->mod_section.loadreduced.dram_drv,
1560 "dram_drv (Loadreduced) DRAM Drive Strength");
1561 PRINT_NXS(149, spd->mod_section.loadreduced.dram_odt_1866,
1562 "dram_odt_1866 (Loadreduced) DRAM ODT (RTT_WR, RTT_NOM)");
1563 PRINT_NXS(150, spd->mod_section.loadreduced.dram_odt_2400,
1564 "dram_odt_2400 (Loadreduced) DRAM ODT (RTT_WR, RTT_NOM)");
1565 PRINT_NXS(151, spd->mod_section.loadreduced.dram_odt_3200,
1566 "dram_odt_3200 (Loadreduced) DRAM ODT (RTT_WR, RTT_NOM)");
1567 PRINT_NXS(152, spd->mod_section.loadreduced.dram_odt_park_1866,
1568 "dram_odt_park_1866 (Loadreduced) DRAM ODT (RTT_PARK)");
1569 PRINT_NXS(153, spd->mod_section.loadreduced.dram_odt_park_2400,
1570 "dram_odt_park_2400 (Loadreduced) DRAM ODT (RTT_PARK)");
1571 PRINT_NXS(154, spd->mod_section.loadreduced.dram_odt_park_3200,
1572 "dram_odt_park_3200 (Loadreduced) DRAM ODT (RTT_PARK)");
1573 PRINT_NNXXS(254, 255, spd->mod_section.loadreduced.crc[0],
1574 spd->mod_section.loadreduced.crc[1],
1575 " Module CRC");
1576 break;
1577 default:
1578 /* Module-specific Section, Unsupported Module Type */
1579 printf("%-3d-%3d: ", 128, 255);
1580
1581 for (i = 128; i <= 255; i++)
1582 printf("%02x", spd->mod_section.uc[i - 60]);
1583
1584 break;
1585 }
1586
1587 /* Unique Module ID: Bytes 320-383 */
1588 PRINT_NXS(320, spd->mmid_lsb, "Module MfgID Code LSB - JEP-106");
1589 PRINT_NXS(321, spd->mmid_msb, "Module MfgID Code MSB - JEP-106");
1590 PRINT_NXS(322, spd->mloc, "Mfg Location");
1591 PRINT_NNXXS(323, 324, spd->mdate[0], spd->mdate[1], "Mfg Date");
1592
1593 printf("%-3d-%3d: ", 325, 328);
1594
1595 for (i = 325; i <= 328; i++)
1596 printf("%02x ", spd->sernum[i - 325]);
1597 printf(" Module Serial Number\n");
1598
1599 printf("%-3d-%3d: ", 329, 348);
1600 for (i = 329; i <= 348; i++)
1601 printf("%02x ", spd->mpart[i - 329]);
1602 printf(" Mfg's Module Part Number\n");
1603
1604 PRINT_NXS(349, spd->mrev, "Module Revision code");
1605 PRINT_NXS(350, spd->dmid_lsb, "DRAM MfgID Code LSB - JEP-106");
1606 PRINT_NXS(351, spd->dmid_msb, "DRAM MfgID Code MSB - JEP-106");
1607 PRINT_NXS(352, spd->stepping, "DRAM stepping");
1608
1609 printf("%-3d-%3d: ", 353, 381);
1610 for (i = 353; i <= 381; i++)
1611 printf("%02x ", spd->msd[i - 353]);
1612 printf(" Mfg's Specific Data\n");
1613}
1614#endif
1615
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]1616static inline void generic_spd_dump(const generic_spd_eeprom_t *spd)
1617{
York Sun5614e712013-09-30 09:22:09 -0700[diff] [blame]1618#if defined(CONFIG_SYS_FSL_DDR1)
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]1619 ddr1_spd_dump(spd);
York Sun5614e712013-09-30 09:22:09 -0700[diff] [blame]1620#elif defined(CONFIG_SYS_FSL_DDR2)
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]1621 ddr2_spd_dump(spd);
York Sun5614e712013-09-30 09:22:09 -0700[diff] [blame]1622#elif defined(CONFIG_SYS_FSL_DDR3)
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]1623 ddr3_spd_dump(spd);
York Sun34e026f2014-03-27 17:54:47 -0700[diff] [blame]1624#elif defined(CONFIG_SYS_FSL_DDR4)
1625 ddr4_spd_dump(spd);
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]1626#endif
1627}
1628
1629static void fsl_ddr_printinfo(const fsl_ddr_info_t *pinfo,
1630 unsigned int ctrl_mask,
1631 unsigned int dimm_mask,
1632 unsigned int do_mask)
1633{
1634 unsigned int i, j, retval;
1635
1636 /* STEP 1: DIMM SPD data */
1637 if (do_mask & STEP_GET_SPD) {
1638 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
1639 if (!(ctrl_mask & (1 << i)))
1640 continue;
1641
1642 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
1643 if (!(dimm_mask & (1 << j)))
1644 continue;
1645
1646 printf("SPD info: Controller=%u "
1647 "DIMM=%u\n", i, j);
1648 generic_spd_dump(
1649 &(pinfo->spd_installed_dimms[i][j]));
1650 printf("\n");
1651 }
1652 printf("\n");
1653 }
1654 printf("\n");
1655 }
1656
1657 /* STEP 2: DIMM Parameters */
1658 if (do_mask & STEP_COMPUTE_DIMM_PARMS) {
1659 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
1660 if (!(ctrl_mask & (1 << i)))
1661 continue;
1662 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
1663 if (!(dimm_mask & (1 << j)))
1664 continue;
1665 printf("DIMM parameters: Controller=%u "
1666 "DIMM=%u\n", i, j);
1667 print_dimm_parameters(
1668 &(pinfo->dimm_params[i][j]));
1669 printf("\n");
1670 }
1671 printf("\n");
1672 }
1673 printf("\n");
1674 }
1675
1676 /* STEP 3: Common Parameters */
1677 if (do_mask & STEP_COMPUTE_COMMON_PARMS) {
1678 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
1679 if (!(ctrl_mask & (1 << i)))
1680 continue;
1681 printf("\"lowest common\" DIMM parameters: "
1682 "Controller=%u\n", i);
1683 print_lowest_common_dimm_parameters(
1684 &pinfo->common_timing_params[i]);
1685 printf("\n");
1686 }
1687 printf("\n");
1688 }
1689
1690 /* STEP 4: User Configuration Options */
1691 if (do_mask & STEP_GATHER_OPTS) {
1692 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
1693 if (!(ctrl_mask & (1 << i)))
1694 continue;
1695 printf("User Config Options: Controller=%u\n", i);
1696 print_memctl_options(&pinfo->memctl_opts[i]);
1697 printf("\n");
1698 }
1699 printf("\n");
1700 }
1701
1702 /* STEP 5: Address assignment */
1703 if (do_mask & STEP_ASSIGN_ADDRESSES) {
1704 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
1705 if (!(ctrl_mask & (1 << i)))
1706 continue;
1707 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
1708 printf("Address Assignment: Controller=%u "
1709 "DIMM=%u\n", i, j);
1710 printf("Don't have this functionality yet\n");
1711 }
1712 printf("\n");
1713 }
1714 printf("\n");
1715 }
1716
1717 /* STEP 6: computed controller register values */
1718 if (do_mask & STEP_COMPUTE_REGS) {
1719 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
1720 if (!(ctrl_mask & (1 << i)))
1721 continue;
1722 printf("Computed Register Values: Controller=%u\n", i);
1723 print_fsl_memctl_config_regs(
1724 &pinfo->fsl_ddr_config_reg[i]);
1725 retval = check_fsl_memctl_config_regs(
1726 &pinfo->fsl_ddr_config_reg[i]);
1727 if (retval) {
1728 printf("check_fsl_memctl_config_regs "
1729 "result = %u\n", retval);
1730 }
1731 printf("\n");
1732 }
1733 printf("\n");
1734 }
1735}
1736
1737struct data_strings {
1738 const char *data_name;
1739 unsigned int step_mask;
1740 unsigned int dimm_number_required;
1741};
1742
1743#define DATA_OPTIONS(name, step, dimm) {#name, step, dimm}
1744
James Yangbf418932013-01-04 08:14:00 +0000[diff] [blame]1745static unsigned int fsl_ddr_parse_interactive_cmd(
1746 char **argv,
1747 int argc,
1748 unsigned int *pstep_mask,
1749 unsigned int *pctlr_mask,
1750 unsigned int *pdimm_mask,
1751 unsigned int *pdimm_number_required
1752 ) {
1753
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]1754 static const struct data_strings options[] = {
1755 DATA_OPTIONS(spd, STEP_GET_SPD, 1),
1756 DATA_OPTIONS(dimmparms, STEP_COMPUTE_DIMM_PARMS, 1),
1757 DATA_OPTIONS(commonparms, STEP_COMPUTE_COMMON_PARMS, 0),
1758 DATA_OPTIONS(opts, STEP_GATHER_OPTS, 0),
1759 DATA_OPTIONS(addresses, STEP_ASSIGN_ADDRESSES, 0),
1760 DATA_OPTIONS(regs, STEP_COMPUTE_REGS, 0),
1761 };
1762 static const unsigned int n_opts = ARRAY_SIZE(options);
James Yangbf418932013-01-04 08:14:00 +0000[diff] [blame]1763
1764 unsigned int i, j;
1765 unsigned int error = 0;
James Yangbf418932013-01-04 08:14:00 +0000[diff] [blame]1766
1767 for (i = 1; i < argc; i++) {
James Yang992f2fb2013-01-04 08:14:01 +0000[diff] [blame]1768 unsigned int matched = 0;
1769
James Yangbf418932013-01-04 08:14:00 +0000[diff] [blame]1770 for (j = 0; j < n_opts; j++) {
1771 if (strcmp(options[j].data_name, argv[i]) != 0)
1772 continue;
1773 *pstep_mask |= options[j].step_mask;
1774 *pdimm_number_required =
1775 options[j].dimm_number_required;
1776 matched = 1;
1777 break;
1778 }
1779
1780 if (matched)
1781 continue;
1782
1783 if (argv[i][0] == 'c') {
1784 char c = argv[i][1];
1785 if (isdigit(c))
1786 *pctlr_mask |= 1 << (c - '0');
1787 continue;
1788 }
1789
1790 if (argv[i][0] == 'd') {
1791 char c = argv[i][1];
1792 if (isdigit(c))
1793 *pdimm_mask |= 1 << (c - '0');
1794 continue;
1795 }
1796
1797 printf("unknown arg %s\n", argv[i]);
1798 *pstep_mask = 0;
1799 error = 1;
1800 break;
1801 }
1802
1803 return error;
1804}
1805
James Yange8ba6c52013-01-07 14:01:03 +0000[diff] [blame]1806int fsl_ddr_interactive_env_var_exists(void)
1807{
1808 char buffer[CONFIG_SYS_CBSIZE];
1809
1810 if (getenv_f("ddr_interactive", buffer, CONFIG_SYS_CBSIZE) >= 0)
1811 return 1;
1812
1813 return 0;
1814}
1815
1816unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set)
James Yangbf418932013-01-04 08:14:00 +0000[diff] [blame]1817{
1818 unsigned long long ddrsize;
1819 const char *prompt = "FSL DDR>";
1820 char buffer[CONFIG_SYS_CBSIZE];
James Yange8ba6c52013-01-07 14:01:03 +0000[diff] [blame]1821 char buffer2[CONFIG_SYS_CBSIZE];
1822 char *p = NULL;
James Yangbf418932013-01-04 08:14:00 +0000[diff] [blame]1823 char *argv[CONFIG_SYS_MAXARGS + 1]; /* NULL terminated */
1824 int argc;
1825 unsigned int next_step = STEP_GET_SPD;
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]1826 const char *usage = {
1827 "commands:\n"
1828 "print print SPD and intermediate computed data\n"
1829 "reset reboot machine\n"
1830 "recompute reload SPD and options to default and recompute regs\n"
1831 "edit modify spd, parameter, or option\n"
1832 "compute recompute registers from current next_step to end\n"
James Yang5926ee32013-01-04 08:14:02 +0000[diff] [blame]1833 "copy copy parameters\n"
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]1834 "next_step shows current next_step\n"
1835 "help this message\n"
1836 "go program the memory controller and continue with u-boot\n"
1837 };
1838
James Yange8ba6c52013-01-07 14:01:03 +0000[diff] [blame]1839 if (var_is_set) {
1840 if (getenv_f("ddr_interactive", buffer2, CONFIG_SYS_CBSIZE) > 0) {
1841 p = buffer2;
1842 } else {
1843 var_is_set = 0;
1844 }
1845 }
1846
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]1847 /*
1848 * The strategy for next_step is that it points to the next
1849 * step in the computation process that needs to be done.
1850 */
1851 while (1) {
James Yange8ba6c52013-01-07 14:01:03 +0000[diff] [blame]1852 if (var_is_set) {
1853 char *pend = strchr(p, ';');
1854 if (pend) {
1855 /* found command separator, copy sub-command */
1856 *pend = '\0';
1857 strcpy(buffer, p);
1858 p = pend + 1;
1859 } else {
1860 /* separator not found, copy whole string */
1861 strcpy(buffer, p);
1862 p = NULL;
1863 var_is_set = 0;
1864 }
1865 } else {
1866 /*
1867 * No need to worry for buffer overflow here in
1868 * this function; readline() maxes out at CFG_CBSIZE
1869 */
1870 readline_into_buffer(prompt, buffer, 0);
1871 }
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]1872 argc = parse_line(buffer, argv);
1873 if (argc == 0)
1874 continue;
1875
1876
1877 if (strcmp(argv[0], "help") == 0) {
1878 puts(usage);
1879 continue;
1880 }
1881
1882 if (strcmp(argv[0], "next_step") == 0) {
1883 printf("next_step = 0x%02X (%s)\n",
1884 next_step,
1885 step_to_string(next_step));
1886 continue;
1887 }
1888
James Yang5926ee32013-01-04 08:14:02 +0000[diff] [blame]1889 if (strcmp(argv[0], "copy") == 0) {
1890 unsigned int error = 0;
1891 unsigned int step_mask = 0;
1892 unsigned int src_ctlr_mask = 0;
1893 unsigned int src_dimm_mask = 0;
1894 unsigned int dimm_number_required = 0;
1895 unsigned int src_ctlr_num = 0;
1896 unsigned int src_dimm_num = 0;
1897 unsigned int dst_ctlr_num = -1;
1898 unsigned int dst_dimm_num = -1;
1899 unsigned int i, num_dest_parms;
1900
1901 if (argc == 1) {
1902 printf("copy <src c#> <src d#> <spd|dimmparms|commonparms|opts|addresses|regs> <dst c#> <dst d#>\n");
1903 continue;
1904 }
1905
1906 error = fsl_ddr_parse_interactive_cmd(
1907 argv, argc,
1908 &step_mask,
1909 &src_ctlr_mask,
1910 &src_dimm_mask,
1911 &dimm_number_required
1912 );
1913
1914 /* XXX: only dimm_number_required and step_mask will
1915 be used by this function. Parse the controller and
1916 DIMM number separately because it is easier. */
1917
1918 if (error)
1919 continue;
1920
1921 /* parse source destination controller / DIMM */
1922
1923 num_dest_parms = dimm_number_required ? 2 : 1;
1924
1925 for (i = 0; i < argc; i++) {
1926 if (argv[i][0] == 'c') {
1927 char c = argv[i][1];
1928 if (isdigit(c)) {
1929 src_ctlr_num = (c - '0');
1930 break;
1931 }
1932 }
1933 }
1934
1935 for (i = 0; i < argc; i++) {
1936 if (argv[i][0] == 'd') {
1937 char c = argv[i][1];
1938 if (isdigit(c)) {
1939 src_dimm_num = (c - '0');
1940 break;
1941 }
1942 }
1943 }
1944
1945 /* parse destination controller / DIMM */
1946
1947 for (i = argc - 1; i >= argc - num_dest_parms; i--) {
1948 if (argv[i][0] == 'c') {
1949 char c = argv[i][1];
1950 if (isdigit(c)) {
1951 dst_ctlr_num = (c - '0');
1952 break;
1953 }
1954 }
1955 }
1956
1957 for (i = argc - 1; i >= argc - num_dest_parms; i--) {
1958 if (argv[i][0] == 'd') {
1959 char c = argv[i][1];
1960 if (isdigit(c)) {
1961 dst_dimm_num = (c - '0');
1962 break;
1963 }
1964 }
1965 }
1966
1967 /* TODO: validate inputs */
1968
1969 debug("src_ctlr_num = %u, src_dimm_num = %u, dst_ctlr_num = %u, dst_dimm_num = %u, step_mask = %x\n",
1970 src_ctlr_num, src_dimm_num, dst_ctlr_num, dst_dimm_num, step_mask);
1971
1972
1973 switch (step_mask) {
1974
1975 case STEP_GET_SPD:
1976 memcpy(&(pinfo->spd_installed_dimms[dst_ctlr_num][dst_dimm_num]),
1977 &(pinfo->spd_installed_dimms[src_ctlr_num][src_dimm_num]),
1978 sizeof(pinfo->spd_installed_dimms[0][0]));
1979 break;
1980
1981 case STEP_COMPUTE_DIMM_PARMS:
1982 memcpy(&(pinfo->dimm_params[dst_ctlr_num][dst_dimm_num]),
1983 &(pinfo->dimm_params[src_ctlr_num][src_dimm_num]),
1984 sizeof(pinfo->dimm_params[0][0]));
1985 break;
1986
1987 case STEP_COMPUTE_COMMON_PARMS:
1988 memcpy(&(pinfo->common_timing_params[dst_ctlr_num]),
1989 &(pinfo->common_timing_params[src_ctlr_num]),
1990 sizeof(pinfo->common_timing_params[0]));
1991 break;
1992
1993 case STEP_GATHER_OPTS:
1994 memcpy(&(pinfo->memctl_opts[dst_ctlr_num]),
1995 &(pinfo->memctl_opts[src_ctlr_num]),
1996 sizeof(pinfo->memctl_opts[0]));
1997 break;
1998
1999 /* someday be able to have addresses to copy addresses... */
2000
2001 case STEP_COMPUTE_REGS:
2002 memcpy(&(pinfo->fsl_ddr_config_reg[dst_ctlr_num]),
2003 &(pinfo->fsl_ddr_config_reg[src_ctlr_num]),
2004 sizeof(pinfo->memctl_opts[0]));
2005 break;
2006
2007 default:
2008 printf("unexpected step_mask value\n");
2009 }
2010
2011 continue;
2012
2013 }
2014
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]2015 if (strcmp(argv[0], "edit") == 0) {
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]2016 unsigned int error = 0;
2017 unsigned int step_mask = 0;
2018 unsigned int ctlr_mask = 0;
2019 unsigned int dimm_mask = 0;
2020 char *p_element = NULL;
2021 char *p_value = NULL;
2022 unsigned int dimm_number_required = 0;
2023 unsigned int ctrl_num;
2024 unsigned int dimm_num;
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]2025
2026 if (argc == 1) {
2027 /* Only the element and value must be last */
2028 printf("edit <c#> <d#> "
2029 "<spd|dimmparms|commonparms|opts|"
2030 "addresses|regs> <element> <value>\n");
2031 printf("for spd, specify byte number for "
2032 "element\n");
2033 continue;
2034 }
2035
James Yangbf418932013-01-04 08:14:00 +0000[diff] [blame]2036 error = fsl_ddr_parse_interactive_cmd(
2037 argv, argc - 2,
2038 &step_mask,
2039 &ctlr_mask,
2040 &dimm_mask,
2041 &dimm_number_required
2042 );
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]2043
2044 if (error)
2045 continue;
2046
2047
2048 /* Check arguments */
2049
2050 /* ERROR: If no steps were found */
2051 if (step_mask == 0) {
2052 printf("Error: No valid steps were specified "
2053 "in argument.\n");
2054 continue;
2055 }
2056
2057 /* ERROR: If multiple steps were found */
2058 if (step_mask & (step_mask - 1)) {
2059 printf("Error: Multiple steps specified in "
2060 "argument.\n");
2061 continue;
2062 }
2063
2064 /* ERROR: Controller not specified */
2065 if (ctlr_mask == 0) {
2066 printf("Error: controller number not "
2067 "specified or no element and "
2068 "value specified\n");
2069 continue;
2070 }
2071
2072 if (ctlr_mask & (ctlr_mask - 1)) {
2073 printf("Error: multiple controllers "
2074 "specified, %X\n", ctlr_mask);
2075 continue;
2076 }
2077
2078 /* ERROR: DIMM number not specified */
2079 if (dimm_number_required && dimm_mask == 0) {
2080 printf("Error: DIMM number number not "
2081 "specified or no element and "
2082 "value specified\n");
2083 continue;
2084 }
2085
2086 if (dimm_mask & (dimm_mask - 1)) {
2087 printf("Error: multipled DIMMs specified\n");
2088 continue;
2089 }
2090
2091 p_element = argv[argc - 2];
2092 p_value = argv[argc - 1];
2093
2094 ctrl_num = __ilog2(ctlr_mask);
2095 dimm_num = __ilog2(dimm_mask);
2096
2097 switch (step_mask) {
2098 case STEP_GET_SPD:
2099 {
2100 unsigned int element_num;
2101 unsigned int value;
2102
2103 element_num = simple_strtoul(p_element,
2104 NULL, 0);
2105 value = simple_strtoul(p_value,
2106 NULL, 0);
2107 fsl_ddr_spd_edit(pinfo,
2108 ctrl_num,
2109 dimm_num,
2110 element_num,
2111 value);
2112 next_step = STEP_COMPUTE_DIMM_PARMS;
2113 }
2114 break;
2115
2116 case STEP_COMPUTE_DIMM_PARMS:
2117 fsl_ddr_dimm_parameters_edit(
2118 pinfo, ctrl_num, dimm_num,
2119 p_element, p_value);
2120 next_step = STEP_COMPUTE_COMMON_PARMS;
2121 break;
2122
2123 case STEP_COMPUTE_COMMON_PARMS:
2124 lowest_common_dimm_parameters_edit(pinfo,
2125 ctrl_num, p_element, p_value);
2126 next_step = STEP_GATHER_OPTS;
2127 break;
2128
2129 case STEP_GATHER_OPTS:
2130 fsl_ddr_options_edit(pinfo, ctrl_num,
2131 p_element, p_value);
2132 next_step = STEP_ASSIGN_ADDRESSES;
2133 break;
2134
2135 case STEP_ASSIGN_ADDRESSES:
2136 printf("editing of address assignment "
2137 "not yet implemented\n");
2138 break;
2139
2140 case STEP_COMPUTE_REGS:
2141 {
2142 fsl_ddr_regs_edit(pinfo,
2143 ctrl_num,
2144 p_element,
2145 p_value);
2146 next_step = STEP_PROGRAM_REGS;
2147 }
2148 break;
2149
2150 default:
2151 printf("programming error\n");
2152 while (1)
2153 ;
2154 break;
2155 }
2156 continue;
2157 }
2158
2159 if (strcmp(argv[0], "reset") == 0) {
2160 /*
2161 * Reboot machine.
2162 * Args don't seem to matter because this
2163 * doesn't return
2164 */
2165 do_reset(NULL, 0, 0, NULL);
York Sun57495e42012-10-08 07:44:22 +0000[diff] [blame]2166 printf("Reset didn't work\n");
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]2167 }
2168
2169 if (strcmp(argv[0], "recompute") == 0) {
2170 /*
2171 * Recalculate everything, starting with
2172 * loading SPD EEPROM from DIMMs
2173 */
2174 next_step = STEP_GET_SPD;
2175 ddrsize = fsl_ddr_compute(pinfo, next_step, 0);
2176 continue;
2177 }
2178
2179 if (strcmp(argv[0], "compute") == 0) {
2180 /*
2181 * Compute rest of steps starting at
2182 * the current next_step/
2183 */
2184 ddrsize = fsl_ddr_compute(pinfo, next_step, 0);
2185 continue;
2186 }
2187
2188 if (strcmp(argv[0], "print") == 0) {
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]2189 unsigned int error = 0;
2190 unsigned int step_mask = 0;
2191 unsigned int ctlr_mask = 0;
2192 unsigned int dimm_mask = 0;
James Yangbf418932013-01-04 08:14:00 +0000[diff] [blame]2193 unsigned int dimm_number_required = 0;
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]2194
2195 if (argc == 1) {
2196 printf("print [c<n>] [d<n>] [spd] [dimmparms] "
2197 "[commonparms] [opts] [addresses] [regs]\n");
2198 continue;
2199 }
2200
James Yangbf418932013-01-04 08:14:00 +0000[diff] [blame]2201 error = fsl_ddr_parse_interactive_cmd(
2202 argv, argc,
2203 &step_mask,
2204 &ctlr_mask,
2205 &dimm_mask,
2206 &dimm_number_required
2207 );
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]2208
2209 if (error)
2210 continue;
2211
2212 /* If no particular controller was found, print all */
2213 if (ctlr_mask == 0)
2214 ctlr_mask = 0xFF;
2215
2216 /* If no particular dimm was found, print all dimms. */
2217 if (dimm_mask == 0)
2218 dimm_mask = 0xFF;
2219
2220 /* If no steps were found, print all steps. */
2221 if (step_mask == 0)
2222 step_mask = STEP_ALL;
2223
2224 fsl_ddr_printinfo(pinfo, ctlr_mask,
2225 dimm_mask, step_mask);
2226 continue;
2227 }
2228
2229 if (strcmp(argv[0], "go") == 0) {
2230 if (next_step)
2231 ddrsize = fsl_ddr_compute(pinfo, next_step, 0);
2232 break;
2233 }
2234
2235 printf("unknown command %s\n", argv[0]);
2236 }
2237
2238 debug("end of memory = %llu\n", (u64)ddrsize);
2239
2240 return ddrsize;
2241}