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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 19268834fb208a7deb43f9a00b034e0c6abab3cd / . / arch / x86 / dts / crownbay.dts
blob: e81054ebc53c091c6cfc66218c420de3f4bd76a2 [file] [log] [blame]
Bin Meng568868d2014-12-12 21:05:24 +0800[diff] [blame]1/*
2 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7/dts-v1/;
8
Bin Meng120c4162014-12-24 13:06:39 +0800[diff] [blame]9/include/ "skeleton.dtsi"
Bin Meng9ca5a0c2014-12-24 13:06:38 +0800[diff] [blame]10/include/ "serial.dtsi"
Bin Meng568868d2014-12-12 21:05:24 +0800[diff] [blame]11
12/ {
Bin Meng568868d2014-12-12 21:05:24 +0800[diff] [blame]13 model = "Intel Crown Bay";
14 compatible = "intel,crownbay", "intel,queensbay";
15
16 config {
17 silent_console = <0>;
18 };
19
20 gpioa {
21 compatible = "intel,ich6-gpio";
22 u-boot,dm-pre-reloc;
23 reg = <0 0x20>;
24 bank-name = "A";
25 };
26
27 gpiob {
28 compatible = "intel,ich6-gpio";
29 u-boot,dm-pre-reloc;
30 reg = <0x20 0x20>;
31 bank-name = "B";
32 };
33
Bin Meng120c4162014-12-24 13:06:39 +0800[diff] [blame]34 chosen {
Bin Mengb21b2082014-12-31 16:05:14 +0800[diff] [blame]35 /*
36 * By default the legacy superio serial port is used as the
37 * U-Boot serial console. If we want to use UART from Topcliff
38 * PCH as the console, change this property to &pciuart#.
39 *
40 * For example, stdout-path = &pciuart0 will use the first
41 * UART on Topcliff PCH.
42 */
Bin Meng120c4162014-12-24 13:06:39 +0800[diff] [blame]43 stdout-path = "/serial";
Bin Meng568868d2014-12-12 21:05:24 +0800[diff] [blame]44 };
45
Bin Meng568868d2014-12-12 21:05:24 +0800[diff] [blame]46 spi {
47 #address-cells = <1>;
48 #size-cells = <0>;
49 compatible = "intel,ich7";
50 spi-flash@0 {
51 reg = <0>;
52 compatible = "sst,25vf016b", "spi-flash";
53 memory-map = <0xffe00000 0x00200000>;
54 };
55 };
Simon Glass0f61de82014-12-17 15:50:37 +0800[diff] [blame]56
57 microcode {
58 update@0 {
59#include "microcode/m0220661105_cv.dtsi"
60 };
61 };
62
Bin Mengb21b2082014-12-31 16:05:14 +0800[diff] [blame]63 pci {
64 #address-cells = <3>;
65 #size-cells = <2>;
66 compatible = "intel,pci";
67 device_type = "pci";
68
69 pcie@17,0 {
70 #address-cells = <3>;
71 #size-cells = <2>;
72 compatible = "intel,pci";
73 device_type = "pci";
74
75 topcliff@0,0 {
76 #address-cells = <3>;
77 #size-cells = <2>;
78 compatible = "intel,pci";
79 device_type = "pci";
80
81 pciuart0: uart@a,1 {
82 compatible = "pci8086,8811.00",
83 "pci8086,8811",
84 "pciclass,070002",
85 "pciclass,0700",
86 "x86-uart";
87 reg = <0x00025100 0x0 0x0 0x0 0x0
88 0x01025110 0x0 0x0 0x0 0x0>;
89 reg-shift = <0>;
90 clock-frequency = <1843200>;
91 current-speed = <115200>;
92 };
93
94 pciuart1: uart@a,2 {
95 compatible = "pci8086,8812.00",
96 "pci8086,8812",
97 "pciclass,070002",
98 "pciclass,0700",
99 "x86-uart";
100 reg = <0x00025200 0x0 0x0 0x0 0x0
101 0x01025210 0x0 0x0 0x0 0x0>;
102 reg-shift = <0>;
103 clock-frequency = <1843200>;
104 current-speed = <115200>;
105 };
106
107 pciuart2: uart@a,3 {
108 compatible = "pci8086,8813.00",
109 "pci8086,8813",
110 "pciclass,070002",
111 "pciclass,0700",
112 "x86-uart";
113 reg = <0x00025300 0x0 0x0 0x0 0x0
114 0x01025310 0x0 0x0 0x0 0x0>;
115 reg-shift = <0>;
116 clock-frequency = <1843200>;
117 current-speed = <115200>;
118 };
119
120 pciuart3: uart@a,4 {
121 compatible = "pci8086,8814.00",
122 "pci8086,8814",
123 "pciclass,070002",
124 "pciclass,0700",
125 "x86-uart";
126 reg = <0x00025400 0x0 0x0 0x0 0x0
127 0x01025410 0x0 0x0 0x0 0x0>;
128 reg-shift = <0>;
129 clock-frequency = <1843200>;
130 current-speed = <115200>;
131 };
132 };
133 };
134 };
135
Bin Meng568868d2014-12-12 21:05:24 +0800[diff] [blame]136};