Blame - board/amcc/ocotea/ocotea.h - platform/external/u-boot

wdenk

0e6d798

2004-03-14 00:07:33 +0000

[diff] [blame]

1

/*

2

3

* Wolfgang Denk, DENX Software Engineering, wd@denx.de.

4

*

Wolfgang Denk

1a45966

2013-07-08 09:37:19 +0200

[diff] [blame^]

5

* SPDX-License-Identifier: GPL-2.0+

wdenk

0e6d798

2004-03-14 00:07:33 +0000

[diff] [blame]

6

*/

7

8

/* Board specific FPGA stuff ... */

Jean-Christophe PLAGNIOL-VILLARD

6d0f6bc

2008-10-16 15:01:15 +0200

[diff] [blame]

9

#define FPGA_REG0 (CONFIG_SYS_FPGA_BASE + 0x00)

wdenk

0e6d798

2004-03-14 00:07:33 +0000

[diff] [blame]

10

#define FPGA_REG0_SSCG_MASK 0x80

11

#define FPGA_REG0_SSCG_DISABLE 0x00

12

#define FPGA_REG0_SSCG_ENABLE 0x80

13

#define FPGA_REG0_BOOT_MASK 0x40

14

#define FPGA_REG0_BOOT_LARGE_FLASH 0x00

15

#define FPGA_REG0_BOOT_SMALL_FLASH 0x40

16

#define FPGA_REG0_ECLS_MASK 0x38 /* New for Ocotea Rev 2 */

17

#define FPGA_REG0_ECLS_0 0x20 /* New for Ocotea Rev 2 */

18

#define FPGA_REG0_ECLS_1 0x10 /* New for Ocotea Rev 2 */

19

#define FPGA_REG0_ECLS_2 0x08 /* New for Ocotea Rev 2 */

20

#define FPGA_REG0_ECLS_VER1 0x00 /* New for Ocotea Rev 2 */

21

#define FPGA_REG0_ECLS_VER3 0x08 /* New for Ocotea Rev 2 */

22

#define FPGA_REG0_ECLS_VER4 0x10 /* New for Ocotea Rev 2 */

23

#define FPGA_REG0_ECLS_VER5 0x18 /* New for Ocotea Rev 2 */

24

#define FPGA_REG0_ECLS_VER2 0x20 /* New for Ocotea Rev 2 */

25

#define FPGA_REG0_ECLS_VER6 0x28 /* New for Ocotea Rev 2 */

26

#define FPGA_REG0_ECLS_VER7 0x30 /* New for Ocotea Rev 2 */

27

#define FPGA_REG0_ECLS_VER8 0x38 /* New for Ocotea Rev 2 */

28

#define FPGA_REG0_ARBITER_MASK 0x04

29

#define FPGA_REG0_ARBITER_EXT 0x00

30

#define FPGA_REG0_ARBITER_INT 0x04

31

#define FPGA_REG0_ONBOARD_FLASH_MASK 0x02

32

#define FPGA_REG0_ONBOARD_FLASH_ENABLE 0x00

33

#define FPGA_REG0_ONBOARD_FLASH_DISABLE 0x02

34

#define FPGA_REG0_FLASH 0x01

Jean-Christophe PLAGNIOL-VILLARD

6d0f6bc

2008-10-16 15:01:15 +0200

[diff] [blame]

35

#define FPGA_REG1 (CONFIG_SYS_FPGA_BASE + 0x01)

wdenk

0e6d798

2004-03-14 00:07:33 +0000

[diff] [blame]

36

#define FPGA_REG1_9772_FSELFBX_MASK 0x80

37

#define FPGA_REG1_9772_FSELFBX_6 0x00

38

#define FPGA_REG1_9772_FSELFBX_10 0x80

39

#define FPGA_REG1_9531_SX_MASK 0x60

40

#define FPGA_REG1_9531_SX_33MHZ 0x00

41

#define FPGA_REG1_9531_SX_100MHZ 0x20

42

#define FPGA_REG1_9531_SX_66MHZ 0x40

43

#define FPGA_REG1_9531_SX_133MHZ 0x60

44

#define FPGA_REG1_9772_FSELBX_MASK 0x18

45

#define FPGA_REG1_9772_FSELBX_4 0x00

46

#define FPGA_REG1_9772_FSELBX_6 0x08

47

#define FPGA_REG1_9772_FSELBX_8 0x10

48

#define FPGA_REG1_9772_FSELBX_10 0x18

49

#define FPGA_REG1_SOURCE_MASK 0x07

50

#define FPGA_REG1_SOURCE_TC 0x00

51

#define FPGA_REG1_SOURCE_66MHZ 0x01

52

#define FPGA_REG1_SOURCE_50MHZ 0x02

53

#define FPGA_REG1_SOURCE_33MHZ 0x03

54

#define FPGA_REG1_SOURCE_25MHZ 0x04

55

#define FPGA_REG1_SOURCE_SSDIV1 0x05

56

#define FPGA_REG1_SOURCE_SSDIV2 0x06

57

#define FPGA_REG1_SOURCE_SSDIV4 0x07

Jean-Christophe PLAGNIOL-VILLARD

6d0f6bc

2008-10-16 15:01:15 +0200

[diff] [blame]

58

#define FPGA_REG2 (CONFIG_SYS_FPGA_BASE + 0x02)

wdenk

0e6d798

2004-03-14 00:07:33 +0000

[diff] [blame]

59

#define FPGA_REG2_TC0 0x80

60

#define FPGA_REG2_TC1 0x40

61

#define FPGA_REG2_TC2 0x20

62

#define FPGA_REG2_TC3 0x10

63

#define FPGA_REG2_GIGABIT_RESET_DISABLE 0x08 /*Use on Ocotea pass 2 boards*/

64

#define FPGA_REG2_EXT_INTFACE_MASK 0x04

65

#define FPGA_REG2_EXT_INTFACE_ENABLE 0x00

66

#define FPGA_REG2_EXT_INTFACE_DISABLE 0x04

Stefan Roese

57275b6

2005-11-01 10:08:03 +0100

[diff] [blame]

67

#define FPGA_REG2_SMII_RESET_DISABLE 0x02 /*Use on Ocotea pass 3 boards*/

wdenk

0e6d798

2004-03-14 00:07:33 +0000

[diff] [blame]

68

#define FPGA_REG2_DEFAULT_UART1_N 0x01

Jean-Christophe PLAGNIOL-VILLARD

6d0f6bc

2008-10-16 15:01:15 +0200

[diff] [blame]

69

#define FPGA_REG3 (CONFIG_SYS_FPGA_BASE + 0x03)

wdenk

0e6d798

2004-03-14 00:07:33 +0000

[diff] [blame]

70

#define FPGA_REG3_GIGABIT_RESET_DISABLE 0x80 /*Use on Ocotea pass 1 boards*/

71

#define FPGA_REG3_ENET_MASK1 0x70 /*Use on Ocotea pass 1 boards*/

72

#define FPGA_REG3_ENET_MASK2 0xF0 /*Use on Ocotea pass 2 boards*/

73

#define FPGA_REG3_ENET_GROUP0 0x00

74

#define FPGA_REG3_ENET_GROUP1 0x10

75

#define FPGA_REG3_ENET_GROUP2 0x20

76

#define FPGA_REG3_ENET_GROUP3 0x30

77

#define FPGA_REG3_ENET_GROUP4 0x40

78

#define FPGA_REG3_ENET_GROUP5 0x50

79

#define FPGA_REG3_ENET_GROUP6 0x60

80

#define FPGA_REG3_ENET_GROUP7 0x70

81

#define FPGA_REG3_ENET_GROUP8 0x80 /*Use on Ocotea pass 2 boards*/

82

#define FPGA_REG3_ENET_ENCODE1(n) ((((unsigned long)(n))&0x07)<<4) /*pass1*/

83

#define FPGA_REG3_ENET_DECODE1(n) ((((unsigned long)(n))>>4)&0x07) /*pass1*/

84

#define FPGA_REG3_ENET_ENCODE2(n) ((((unsigned long)(n))&0x0F)<<4) /*pass2*/

85

#define FPGA_REG3_ENET_DECODE2(n) ((((unsigned long)(n))>>4)&0x0F) /*pass2*/

86

#define FPGA_REG3_STAT_MASK 0x0F

87

#define FPGA_REG3_STAT_LED8_ENAB 0x08

88

#define FPGA_REG3_STAT_LED4_ENAB 0x04

89

#define FPGA_REG3_STAT_LED2_ENAB 0x02

90

#define FPGA_REG3_STAT_LED1_ENAB 0x01

91

#define FPGA_REG3_STAT_LED8_DISAB 0x00

92

#define FPGA_REG3_STAT_LED4_DISAB 0x00

93

#define FPGA_REG3_STAT_LED2_DISAB 0x00

94

#define FPGA_REG3_STAT_LED1_DISAB 0x00

Jean-Christophe PLAGNIOL-VILLARD

6d0f6bc

2008-10-16 15:01:15 +0200

[diff] [blame]

95

#define FPGA_REG4 (CONFIG_SYS_FPGA_BASE + 0x04)

wdenk

0e6d798

2004-03-14 00:07:33 +0000

[diff] [blame]

96

#define FPGA_REG4_GPHY_MODE10 0x80

97

#define FPGA_REG4_GPHY_MODE100 0x40

98

#define FPGA_REG4_GPHY_MODE1000 0x20

99

#define FPGA_REG4_GPHY_FRC_DPLX 0x10

100

#define FPGA_REG4_GPHY_ANEG_DIS 0x08

101

#define FPGA_REG4_CONNECT_PHYS 0x04

102

103

104

#define SDR0_CUST0_ENET3_MASK 0x00000080

105

#define SDR0_CUST0_ENET3_COPPER 0x00000000

106

#define SDR0_CUST0_ENET3_FIBER 0x00000080

107

#define SDR0_CUST0_RGMII3_MASK 0x00000070

108

#define SDR0_CUST0_RGMII3_ENCODE(n) ((((unsigned long)(n))&0x7)<<4)

109

#define SDR0_CUST0_RGMII3_DECODE(n) ((((unsigned long)(n))>>4)&0x07)

110

#define SDR0_CUST0_RGMII3_DISAB 0x00000000

111

#define SDR0_CUST0_RGMII3_RTBI 0x00000040

112

#define SDR0_CUST0_RGMII3_RGMII 0x00000050

113

#define SDR0_CUST0_RGMII3_TBI 0x00000060

114

#define SDR0_CUST0_RGMII3_GMII 0x00000070

115

#define SDR0_CUST0_ENET2_MASK 0x00000008

116

#define SDR0_CUST0_ENET2_COPPER 0x00000000

117

#define SDR0_CUST0_ENET2_FIBER 0x00000008

118

#define SDR0_CUST0_RGMII2_MASK 0x00000007

119

#define SDR0_CUST0_RGMII2_ENCODE(n) ((((unsigned long)(n))&0x7)<<0)

120

#define SDR0_CUST0_RGMII2_DECODE(n) ((((unsigned long)(n))>>0)&0x07)

121

#define SDR0_CUST0_RGMII2_DISAB 0x00000000

122

#define SDR0_CUST0_RGMII2_RTBI 0x00000004

123

#define SDR0_CUST0_RGMII2_RGMII 0x00000005

124

#define SDR0_CUST0_RGMII2_TBI 0x00000006

125

#define SDR0_CUST0_RGMII2_GMII 0x00000007