blob: f99bdaf94da2be3dc216ff05f9580105a8049163 [file] [log] [blame]
Stefan Agner72d7bea2014-09-12 13:06:35 +02001/*
Stefan Agnere24bb2b2015-10-13 22:11:42 -07002 * Copyright 2009-2015 Freescale Semiconductor, Inc. and others
Stefan Agner72d7bea2014-09-12 13:06:35 +02003 *
4 * Description: MPC5125, VF610, MCF54418 and Kinetis K70 Nand driver.
5 * Ported to U-Boot by Stefan Agner
6 * Based on RFC driver posted on Kernel Mailing list by Bill Pringlemeir
7 * Jason ported to M54418TWR and MVFA5.
8 * Authors: Stefan Agner <stefan.agner@toradex.com>
9 * Bill Pringlemeir <bpringlemeir@nbsps.com>
10 * Shaohui Xie <b21989@freescale.com>
11 * Jason Jin <Jason.jin@freescale.com>
12 *
13 * Based on original driver mpc5121_nfc.c.
14 *
Tom Rini5b8031c2016-01-14 22:05:13 -050015 * SPDX-License-Identifier: GPL-2.0+
Stefan Agner72d7bea2014-09-12 13:06:35 +020016 *
17 * Limitations:
18 * - Untested on MPC5125 and M54418.
Stefan Agnere24bb2b2015-10-13 22:11:42 -070019 * - DMA and pipelining not used.
Stefan Agner72d7bea2014-09-12 13:06:35 +020020 * - 2K pages or less.
Stefan Agnere24bb2b2015-10-13 22:11:42 -070021 * - HW ECC: Only 2K page with 64+ OOB.
22 * - HW ECC: Only 24 and 32-bit error correction implemented.
Stefan Agner72d7bea2014-09-12 13:06:35 +020023 */
24
25#include <common.h>
26#include <malloc.h>
27
28#include <linux/mtd/mtd.h>
29#include <linux/mtd/nand.h>
30#include <linux/mtd/partitions.h>
31
32#include <nand.h>
33#include <errno.h>
34#include <asm/io.h>
35
36/* Register Offsets */
37#define NFC_FLASH_CMD1 0x3F00
38#define NFC_FLASH_CMD2 0x3F04
39#define NFC_COL_ADDR 0x3F08
40#define NFC_ROW_ADDR 0x3F0c
41#define NFC_ROW_ADDR_INC 0x3F14
42#define NFC_FLASH_STATUS1 0x3F18
43#define NFC_FLASH_STATUS2 0x3F1c
44#define NFC_CACHE_SWAP 0x3F28
45#define NFC_SECTOR_SIZE 0x3F2c
46#define NFC_FLASH_CONFIG 0x3F30
47#define NFC_IRQ_STATUS 0x3F38
48
49/* Addresses for NFC MAIN RAM BUFFER areas */
50#define NFC_MAIN_AREA(n) ((n) * 0x1000)
51
52#define PAGE_2K 0x0800
53#define OOB_64 0x0040
Stefan Agnere24bb2b2015-10-13 22:11:42 -070054#define OOB_MAX 0x0100
Stefan Agner72d7bea2014-09-12 13:06:35 +020055
56/*
57 * NFC_CMD2[CODE] values. See section:
58 * - 31.4.7 Flash Command Code Description, Vybrid manual
59 * - 23.8.6 Flash Command Sequencer, MPC5125 manual
60 *
61 * Briefly these are bitmasks of controller cycles.
62 */
63#define READ_PAGE_CMD_CODE 0x7EE0
Stefan Agner8fca2d82015-05-08 19:07:13 +020064#define READ_ONFI_PARAM_CMD_CODE 0x4860
Stefan Agner72d7bea2014-09-12 13:06:35 +020065#define PROGRAM_PAGE_CMD_CODE 0x7FC0
66#define ERASE_CMD_CODE 0x4EC0
67#define READ_ID_CMD_CODE 0x4804
68#define RESET_CMD_CODE 0x4040
69#define STATUS_READ_CMD_CODE 0x4068
70
71/* NFC ECC mode define */
72#define ECC_BYPASS 0
73#define ECC_45_BYTE 6
Stefan Agner080a71e2015-05-08 19:07:12 +020074#define ECC_60_BYTE 7
Stefan Agner72d7bea2014-09-12 13:06:35 +020075
76/*** Register Mask and bit definitions */
77
78/* NFC_FLASH_CMD1 Field */
79#define CMD_BYTE2_MASK 0xFF000000
80#define CMD_BYTE2_SHIFT 24
81
82/* NFC_FLASH_CM2 Field */
83#define CMD_BYTE1_MASK 0xFF000000
84#define CMD_BYTE1_SHIFT 24
85#define CMD_CODE_MASK 0x00FFFF00
86#define CMD_CODE_SHIFT 8
87#define BUFNO_MASK 0x00000006
88#define BUFNO_SHIFT 1
89#define START_BIT (1<<0)
90
91/* NFC_COL_ADDR Field */
92#define COL_ADDR_MASK 0x0000FFFF
93#define COL_ADDR_SHIFT 0
94
95/* NFC_ROW_ADDR Field */
96#define ROW_ADDR_MASK 0x00FFFFFF
97#define ROW_ADDR_SHIFT 0
98#define ROW_ADDR_CHIP_SEL_RB_MASK 0xF0000000
99#define ROW_ADDR_CHIP_SEL_RB_SHIFT 28
100#define ROW_ADDR_CHIP_SEL_MASK 0x0F000000
101#define ROW_ADDR_CHIP_SEL_SHIFT 24
102
103/* NFC_FLASH_STATUS2 Field */
104#define STATUS_BYTE1_MASK 0x000000FF
105
106/* NFC_FLASH_CONFIG Field */
107#define CONFIG_ECC_SRAM_ADDR_MASK 0x7FC00000
108#define CONFIG_ECC_SRAM_ADDR_SHIFT 22
109#define CONFIG_ECC_SRAM_REQ_BIT (1<<21)
110#define CONFIG_DMA_REQ_BIT (1<<20)
111#define CONFIG_ECC_MODE_MASK 0x000E0000
112#define CONFIG_ECC_MODE_SHIFT 17
113#define CONFIG_FAST_FLASH_BIT (1<<16)
114#define CONFIG_16BIT (1<<7)
115#define CONFIG_BOOT_MODE_BIT (1<<6)
116#define CONFIG_ADDR_AUTO_INCR_BIT (1<<5)
117#define CONFIG_BUFNO_AUTO_INCR_BIT (1<<4)
118#define CONFIG_PAGE_CNT_MASK 0xF
119#define CONFIG_PAGE_CNT_SHIFT 0
120
121/* NFC_IRQ_STATUS Field */
122#define IDLE_IRQ_BIT (1<<29)
123#define IDLE_EN_BIT (1<<20)
124#define CMD_DONE_CLEAR_BIT (1<<18)
125#define IDLE_CLEAR_BIT (1<<17)
126
127#define NFC_TIMEOUT (1000)
128
Stefan Agner72d7bea2014-09-12 13:06:35 +0200129/*
Stefan Agnere24bb2b2015-10-13 22:11:42 -0700130 * ECC status - seems to consume 8 bytes (double word). The documented
131 * status byte is located in the lowest byte of the second word (which is
132 * the 4th or 7th byte depending on endianness).
133 * Calculate an offset to store the ECC status at the end of the buffer.
Stefan Agner72d7bea2014-09-12 13:06:35 +0200134 */
Stefan Agnere24bb2b2015-10-13 22:11:42 -0700135#define ECC_SRAM_ADDR (PAGE_2K + OOB_MAX - 8)
136
137#define ECC_STATUS 0x4
138#define ECC_STATUS_MASK 0x80
139#define ECC_STATUS_ERR_COUNT 0x3F
140
141enum vf610_nfc_alt_buf {
142 ALT_BUF_DATA = 0,
143 ALT_BUF_ID = 1,
144 ALT_BUF_STAT = 2,
145 ALT_BUF_ONFI = 3,
146};
Stefan Agner72d7bea2014-09-12 13:06:35 +0200147
148struct vf610_nfc {
Stefan Agnere24bb2b2015-10-13 22:11:42 -0700149 struct nand_chip chip;
150 void __iomem *regs;
151 uint buf_offset;
152 int write_sz;
Stefan Agner72d7bea2014-09-12 13:06:35 +0200153 /* Status and ID are in alternate locations. */
Stefan Agnere24bb2b2015-10-13 22:11:42 -0700154 enum vf610_nfc_alt_buf alt_buf;
Stefan Agner72d7bea2014-09-12 13:06:35 +0200155};
156
Scott Wood17cb4b82016-05-30 13:57:56 -0500157#define mtd_to_nfc(_mtd) nand_get_controller_data(mtd_to_nand(_mtd))
Stefan Agner72d7bea2014-09-12 13:06:35 +0200158
Stefan Agner080a71e2015-05-08 19:07:12 +0200159#if defined(CONFIG_SYS_NAND_VF610_NFC_45_ECC_BYTES)
160#define ECC_HW_MODE ECC_45_BYTE
161
162static struct nand_ecclayout vf610_nfc_ecc = {
Stefan Agner72d7bea2014-09-12 13:06:35 +0200163 .eccbytes = 45,
164 .eccpos = {19, 20, 21, 22, 23,
165 24, 25, 26, 27, 28, 29, 30, 31,
166 32, 33, 34, 35, 36, 37, 38, 39,
167 40, 41, 42, 43, 44, 45, 46, 47,
168 48, 49, 50, 51, 52, 53, 54, 55,
169 56, 57, 58, 59, 60, 61, 62, 63},
170 .oobfree = {
Stefan Agnere24bb2b2015-10-13 22:11:42 -0700171 {.offset = 2,
172 .length = 17} }
Stefan Agner72d7bea2014-09-12 13:06:35 +0200173};
Stefan Agner080a71e2015-05-08 19:07:12 +0200174#elif defined(CONFIG_SYS_NAND_VF610_NFC_60_ECC_BYTES)
175#define ECC_HW_MODE ECC_60_BYTE
176
177static struct nand_ecclayout vf610_nfc_ecc = {
178 .eccbytes = 60,
179 .eccpos = { 4, 5, 6, 7, 8, 9, 10, 11,
180 12, 13, 14, 15, 16, 17, 18, 19,
181 20, 21, 22, 23, 24, 25, 26, 27,
182 28, 29, 30, 31, 32, 33, 34, 35,
183 36, 37, 38, 39, 40, 41, 42, 43,
184 44, 45, 46, 47, 48, 49, 50, 51,
185 52, 53, 54, 55, 56, 57, 58, 59,
186 60, 61, 62, 63 },
187 .oobfree = {
188 {.offset = 2,
189 .length = 2} }
190};
191#endif
Stefan Agner72d7bea2014-09-12 13:06:35 +0200192
193static inline u32 vf610_nfc_read(struct mtd_info *mtd, uint reg)
194{
195 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
196
197 return readl(nfc->regs + reg);
198}
199
200static inline void vf610_nfc_write(struct mtd_info *mtd, uint reg, u32 val)
201{
202 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
203
204 writel(val, nfc->regs + reg);
205}
206
207static inline void vf610_nfc_set(struct mtd_info *mtd, uint reg, u32 bits)
208{
209 vf610_nfc_write(mtd, reg, vf610_nfc_read(mtd, reg) | bits);
210}
211
212static inline void vf610_nfc_clear(struct mtd_info *mtd, uint reg, u32 bits)
213{
214 vf610_nfc_write(mtd, reg, vf610_nfc_read(mtd, reg) & ~bits);
215}
216
217static inline void vf610_nfc_set_field(struct mtd_info *mtd, u32 reg,
218 u32 mask, u32 shift, u32 val)
219{
220 vf610_nfc_write(mtd, reg,
221 (vf610_nfc_read(mtd, reg) & (~mask)) | val << shift);
222}
223
224static inline void vf610_nfc_memcpy(void *dst, const void *src, size_t n)
225{
226 /*
Stefan Agnere24bb2b2015-10-13 22:11:42 -0700227 * Use this accessor for the internal SRAM buffers. On the ARM
228 * Freescale Vybrid SoC it's known that the driver can treat
229 * the SRAM buffer as if it's memory. Other platform might need
230 * to treat the buffers differently.
231 *
232 * For the time being, use memcpy
Stefan Agner72d7bea2014-09-12 13:06:35 +0200233 */
234 memcpy(dst, src, n);
235}
236
237/* Clear flags for upcoming command */
238static inline void vf610_nfc_clear_status(void __iomem *regbase)
239{
240 void __iomem *reg = regbase + NFC_IRQ_STATUS;
241 u32 tmp = __raw_readl(reg);
242 tmp |= CMD_DONE_CLEAR_BIT | IDLE_CLEAR_BIT;
243 __raw_writel(tmp, reg);
244}
245
246/* Wait for complete operation */
Stefan Agnere24bb2b2015-10-13 22:11:42 -0700247static void vf610_nfc_done(struct mtd_info *mtd)
Stefan Agner72d7bea2014-09-12 13:06:35 +0200248{
249 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
250 uint start;
251
252 /*
253 * Barrier is needed after this write. This write need
254 * to be done before reading the next register the first
255 * time.
256 * vf610_nfc_set implicates such a barrier by using writel
257 * to write to the register.
258 */
259 vf610_nfc_set(mtd, NFC_FLASH_CMD2, START_BIT);
260
261 start = get_timer(0);
262
263 while (!(vf610_nfc_read(mtd, NFC_IRQ_STATUS) & IDLE_IRQ_BIT)) {
264 if (get_timer(start) > NFC_TIMEOUT) {
Stefan Agnere24bb2b2015-10-13 22:11:42 -0700265 printf("Timeout while waiting for IDLE.\n");
Stefan Agner72d7bea2014-09-12 13:06:35 +0200266 return;
267 }
268 }
269 vf610_nfc_clear_status(nfc->regs);
270}
271
272static u8 vf610_nfc_get_id(struct mtd_info *mtd, int col)
273{
274 u32 flash_id;
275
276 if (col < 4) {
277 flash_id = vf610_nfc_read(mtd, NFC_FLASH_STATUS1);
Stefan Agnere24bb2b2015-10-13 22:11:42 -0700278 flash_id >>= (3 - col) * 8;
Stefan Agner72d7bea2014-09-12 13:06:35 +0200279 } else {
280 flash_id = vf610_nfc_read(mtd, NFC_FLASH_STATUS2);
Stefan Agnere24bb2b2015-10-13 22:11:42 -0700281 flash_id >>= 24;
Stefan Agner72d7bea2014-09-12 13:06:35 +0200282 }
Stefan Agnere24bb2b2015-10-13 22:11:42 -0700283
284 return flash_id & 0xff;
Stefan Agner72d7bea2014-09-12 13:06:35 +0200285}
286
287static u8 vf610_nfc_get_status(struct mtd_info *mtd)
288{
289 return vf610_nfc_read(mtd, NFC_FLASH_STATUS2) & STATUS_BYTE1_MASK;
290}
291
292/* Single command */
293static void vf610_nfc_send_command(void __iomem *regbase, u32 cmd_byte1,
294 u32 cmd_code)
295{
296 void __iomem *reg = regbase + NFC_FLASH_CMD2;
297 u32 tmp;
298 vf610_nfc_clear_status(regbase);
299
300 tmp = __raw_readl(reg);
301 tmp &= ~(CMD_BYTE1_MASK | CMD_CODE_MASK | BUFNO_MASK);
302 tmp |= cmd_byte1 << CMD_BYTE1_SHIFT;
303 tmp |= cmd_code << CMD_CODE_SHIFT;
304 __raw_writel(tmp, reg);
305}
306
307/* Two commands */
308static void vf610_nfc_send_commands(void __iomem *regbase, u32 cmd_byte1,
309 u32 cmd_byte2, u32 cmd_code)
310{
311 void __iomem *reg = regbase + NFC_FLASH_CMD1;
312 u32 tmp;
313 vf610_nfc_send_command(regbase, cmd_byte1, cmd_code);
314
315 tmp = __raw_readl(reg);
316 tmp &= ~CMD_BYTE2_MASK;
317 tmp |= cmd_byte2 << CMD_BYTE2_SHIFT;
318 __raw_writel(tmp, reg);
319}
320
321static void vf610_nfc_addr_cycle(struct mtd_info *mtd, int column, int page)
322{
323 if (column != -1) {
324 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
Stefan Agner5dec2862015-05-08 19:07:09 +0200325 if (nfc->chip.options & NAND_BUSWIDTH_16)
326 column = column / 2;
Stefan Agner72d7bea2014-09-12 13:06:35 +0200327 vf610_nfc_set_field(mtd, NFC_COL_ADDR, COL_ADDR_MASK,
328 COL_ADDR_SHIFT, column);
329 }
330 if (page != -1)
331 vf610_nfc_set_field(mtd, NFC_ROW_ADDR, ROW_ADDR_MASK,
332 ROW_ADDR_SHIFT, page);
333}
334
Stefan Agner5dec2862015-05-08 19:07:09 +0200335static inline void vf610_nfc_ecc_mode(struct mtd_info *mtd, int ecc_mode)
336{
337 vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG,
338 CONFIG_ECC_MODE_MASK,
339 CONFIG_ECC_MODE_SHIFT, ecc_mode);
340}
341
Stefan Agner55765b12015-03-24 17:54:20 +0100342static inline void vf610_nfc_transfer_size(void __iomem *regbase, int size)
343{
344 __raw_writel(size, regbase + NFC_SECTOR_SIZE);
345}
346
Stefan Agner72d7bea2014-09-12 13:06:35 +0200347/* Send command to NAND chip */
348static void vf610_nfc_command(struct mtd_info *mtd, unsigned command,
349 int column, int page)
350{
351 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
Stefan Agnere24bb2b2015-10-13 22:11:42 -0700352 int trfr_sz = nfc->chip.options & NAND_BUSWIDTH_16 ? 1 : 0;
Stefan Agner72d7bea2014-09-12 13:06:35 +0200353
Stefan Agnere24bb2b2015-10-13 22:11:42 -0700354 nfc->buf_offset = max(column, 0);
355 nfc->alt_buf = ALT_BUF_DATA;
Stefan Agner72d7bea2014-09-12 13:06:35 +0200356
357 switch (command) {
Stefan Agner6fcfd1e2015-05-08 19:07:07 +0200358 case NAND_CMD_SEQIN:
359 /* Use valid column/page from preread... */
360 vf610_nfc_addr_cycle(mtd, column, page);
Stefan Agnere24bb2b2015-10-13 22:11:42 -0700361 nfc->buf_offset = 0;
362
Stefan Agner6fcfd1e2015-05-08 19:07:07 +0200363 /*
364 * SEQIN => data => PAGEPROG sequence is done by the controller
365 * hence we do not need to issue the command here...
366 */
367 return;
Stefan Agner72d7bea2014-09-12 13:06:35 +0200368 case NAND_CMD_PAGEPROG:
Stefan Agnere24bb2b2015-10-13 22:11:42 -0700369 trfr_sz += nfc->write_sz;
370 vf610_nfc_ecc_mode(mtd, ECC_HW_MODE);
371 vf610_nfc_transfer_size(nfc->regs, trfr_sz);
Stefan Agner72d7bea2014-09-12 13:06:35 +0200372 vf610_nfc_send_commands(nfc->regs, NAND_CMD_SEQIN,
373 command, PROGRAM_PAGE_CMD_CODE);
Stefan Agner72d7bea2014-09-12 13:06:35 +0200374 break;
375
376 case NAND_CMD_RESET:
Stefan Agner55765b12015-03-24 17:54:20 +0100377 vf610_nfc_transfer_size(nfc->regs, 0);
Stefan Agner72d7bea2014-09-12 13:06:35 +0200378 vf610_nfc_send_command(nfc->regs, command, RESET_CMD_CODE);
379 break;
Stefan Agner5dec2862015-05-08 19:07:09 +0200380
Stefan Agner72d7bea2014-09-12 13:06:35 +0200381 case NAND_CMD_READOOB:
Stefan Agnere24bb2b2015-10-13 22:11:42 -0700382 trfr_sz += mtd->oobsize;
Stefan Agner5dec2862015-05-08 19:07:09 +0200383 column = mtd->writesize;
Stefan Agnere24bb2b2015-10-13 22:11:42 -0700384 vf610_nfc_transfer_size(nfc->regs, trfr_sz);
Stefan Agner72d7bea2014-09-12 13:06:35 +0200385 vf610_nfc_send_commands(nfc->regs, NAND_CMD_READ0,
386 NAND_CMD_READSTART, READ_PAGE_CMD_CODE);
387 vf610_nfc_addr_cycle(mtd, column, page);
Stefan Agner5dec2862015-05-08 19:07:09 +0200388 vf610_nfc_ecc_mode(mtd, ECC_BYPASS);
389 break;
390
391 case NAND_CMD_READ0:
Stefan Agnere24bb2b2015-10-13 22:11:42 -0700392 trfr_sz += mtd->writesize + mtd->oobsize;
393 vf610_nfc_transfer_size(nfc->regs, trfr_sz);
394 vf610_nfc_ecc_mode(mtd, ECC_HW_MODE);
Stefan Agner5dec2862015-05-08 19:07:09 +0200395 vf610_nfc_send_commands(nfc->regs, NAND_CMD_READ0,
396 NAND_CMD_READSTART, READ_PAGE_CMD_CODE);
397 vf610_nfc_addr_cycle(mtd, column, page);
Stefan Agner72d7bea2014-09-12 13:06:35 +0200398 break;
399
Stefan Agner8fca2d82015-05-08 19:07:13 +0200400 case NAND_CMD_PARAM:
401 nfc->alt_buf = ALT_BUF_ONFI;
Stefan Agnere24bb2b2015-10-13 22:11:42 -0700402 trfr_sz = 3 * sizeof(struct nand_onfi_params);
403 vf610_nfc_transfer_size(nfc->regs, trfr_sz);
Stefan Agner8fca2d82015-05-08 19:07:13 +0200404 vf610_nfc_send_command(nfc->regs, NAND_CMD_PARAM,
405 READ_ONFI_PARAM_CMD_CODE);
406 vf610_nfc_set_field(mtd, NFC_ROW_ADDR, ROW_ADDR_MASK,
407 ROW_ADDR_SHIFT, column);
408 vf610_nfc_ecc_mode(mtd, ECC_BYPASS);
409 break;
410
Stefan Agner72d7bea2014-09-12 13:06:35 +0200411 case NAND_CMD_ERASE1:
Stefan Agner55765b12015-03-24 17:54:20 +0100412 vf610_nfc_transfer_size(nfc->regs, 0);
Stefan Agner72d7bea2014-09-12 13:06:35 +0200413 vf610_nfc_send_commands(nfc->regs, command,
414 NAND_CMD_ERASE2, ERASE_CMD_CODE);
415 vf610_nfc_addr_cycle(mtd, column, page);
416 break;
417
418 case NAND_CMD_READID:
419 nfc->alt_buf = ALT_BUF_ID;
Stefan Agnere24bb2b2015-10-13 22:11:42 -0700420 nfc->buf_offset = 0;
Stefan Agner55765b12015-03-24 17:54:20 +0100421 vf610_nfc_transfer_size(nfc->regs, 0);
Stefan Agner72d7bea2014-09-12 13:06:35 +0200422 vf610_nfc_send_command(nfc->regs, command, READ_ID_CMD_CODE);
Stefan Agner8fca2d82015-05-08 19:07:13 +0200423 vf610_nfc_set_field(mtd, NFC_ROW_ADDR, ROW_ADDR_MASK,
424 ROW_ADDR_SHIFT, column);
Stefan Agner72d7bea2014-09-12 13:06:35 +0200425 break;
426
427 case NAND_CMD_STATUS:
428 nfc->alt_buf = ALT_BUF_STAT;
Stefan Agner55765b12015-03-24 17:54:20 +0100429 vf610_nfc_transfer_size(nfc->regs, 0);
Stefan Agnere24bb2b2015-10-13 22:11:42 -0700430 vf610_nfc_send_command(nfc->regs, command, STATUS_READ_CMD_CODE);
Stefan Agner72d7bea2014-09-12 13:06:35 +0200431 break;
432 default:
433 return;
434 }
435
436 vf610_nfc_done(mtd);
Stefan Agnere24bb2b2015-10-13 22:11:42 -0700437
438 nfc->write_sz = 0;
Stefan Agner72d7bea2014-09-12 13:06:35 +0200439}
440
Stefan Agner72d7bea2014-09-12 13:06:35 +0200441/* Read data from NFC buffers */
442static void vf610_nfc_read_buf(struct mtd_info *mtd, u_char *buf, int len)
443{
444 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
Stefan Agnere24bb2b2015-10-13 22:11:42 -0700445 uint c = nfc->buf_offset;
Stefan Agner72d7bea2014-09-12 13:06:35 +0200446
Stefan Agner8fca2d82015-05-08 19:07:13 +0200447 /* Alternate buffers are only supported through read_byte */
448 if (nfc->alt_buf)
449 return;
450
451 vf610_nfc_memcpy(buf, nfc->regs + NFC_MAIN_AREA(0) + c, len);
Stefan Agner72d7bea2014-09-12 13:06:35 +0200452
Stefan Agnere24bb2b2015-10-13 22:11:42 -0700453 nfc->buf_offset += len;
Stefan Agner72d7bea2014-09-12 13:06:35 +0200454}
455
456/* Write data to NFC buffers */
Stefan Agnere24bb2b2015-10-13 22:11:42 -0700457static void vf610_nfc_write_buf(struct mtd_info *mtd, const uint8_t *buf,
Stefan Agner72d7bea2014-09-12 13:06:35 +0200458 int len)
459{
460 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
Stefan Agnere24bb2b2015-10-13 22:11:42 -0700461 uint c = nfc->buf_offset;
Stefan Agner72d7bea2014-09-12 13:06:35 +0200462 uint l;
463
Stefan Agnere24bb2b2015-10-13 22:11:42 -0700464 l = min_t(uint, len, mtd->writesize + mtd->oobsize - c);
Stefan Agner72d7bea2014-09-12 13:06:35 +0200465 vf610_nfc_memcpy(nfc->regs + NFC_MAIN_AREA(0) + c, buf, l);
Stefan Agnere24bb2b2015-10-13 22:11:42 -0700466
467 nfc->write_sz += l;
468 nfc->buf_offset += l;
Stefan Agner72d7bea2014-09-12 13:06:35 +0200469}
470
471/* Read byte from NFC buffers */
Stefan Agnere24bb2b2015-10-13 22:11:42 -0700472static uint8_t vf610_nfc_read_byte(struct mtd_info *mtd)
Stefan Agner72d7bea2014-09-12 13:06:35 +0200473{
Stefan Agner8fca2d82015-05-08 19:07:13 +0200474 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
Stefan Agner72d7bea2014-09-12 13:06:35 +0200475 u8 tmp;
Stefan Agnere24bb2b2015-10-13 22:11:42 -0700476 uint c = nfc->buf_offset;
Stefan Agner8fca2d82015-05-08 19:07:13 +0200477
478 switch (nfc->alt_buf) {
479 case ALT_BUF_ID:
480 tmp = vf610_nfc_get_id(mtd, c);
481 break;
482 case ALT_BUF_STAT:
483 tmp = vf610_nfc_get_status(mtd);
484 break;
Stefan Agner8fca2d82015-05-08 19:07:13 +0200485#ifdef __LITTLE_ENDIAN
Stefan Agnere24bb2b2015-10-13 22:11:42 -0700486 case ALT_BUF_ONFI:
Stefan Agner8fca2d82015-05-08 19:07:13 +0200487 /* Reverse byte since the controller uses big endianness */
Stefan Agnere24bb2b2015-10-13 22:11:42 -0700488 c = nfc->buf_offset ^ 0x3;
489 /* fall-through */
Stefan Agner8fca2d82015-05-08 19:07:13 +0200490#endif
491 default:
492 tmp = *((u8 *)(nfc->regs + NFC_MAIN_AREA(0) + c));
493 break;
494 }
Stefan Agnere24bb2b2015-10-13 22:11:42 -0700495 nfc->buf_offset++;
Stefan Agner72d7bea2014-09-12 13:06:35 +0200496 return tmp;
497}
498
499/* Read word from NFC buffers */
500static u16 vf610_nfc_read_word(struct mtd_info *mtd)
501{
502 u16 tmp;
Stefan Agnere24bb2b2015-10-13 22:11:42 -0700503
Stefan Agner72d7bea2014-09-12 13:06:35 +0200504 vf610_nfc_read_buf(mtd, (u_char *)&tmp, sizeof(tmp));
505 return tmp;
506}
507
508/* If not provided, upper layers apply a fixed delay. */
509static int vf610_nfc_dev_ready(struct mtd_info *mtd)
510{
511 /* NFC handles R/B internally; always ready. */
512 return 1;
513}
514
515/*
516 * This function supports Vybrid only (MPC5125 would have full RB and four CS)
517 */
518static void vf610_nfc_select_chip(struct mtd_info *mtd, int chip)
519{
520#ifdef CONFIG_VF610
521 u32 tmp = vf610_nfc_read(mtd, NFC_ROW_ADDR);
522 tmp &= ~(ROW_ADDR_CHIP_SEL_RB_MASK | ROW_ADDR_CHIP_SEL_MASK);
Stefan Agner72d7bea2014-09-12 13:06:35 +0200523
Stefan Agnere24bb2b2015-10-13 22:11:42 -0700524 if (chip >= 0) {
525 tmp |= 1 << ROW_ADDR_CHIP_SEL_RB_SHIFT;
526 tmp |= (1 << chip) << ROW_ADDR_CHIP_SEL_SHIFT;
527 }
Stefan Agner72d7bea2014-09-12 13:06:35 +0200528
529 vf610_nfc_write(mtd, NFC_ROW_ADDR, tmp);
530#endif
531}
532
533/* Count the number of 0's in buff upto max_bits */
534static inline int count_written_bits(uint8_t *buff, int size, int max_bits)
535{
536 uint32_t *buff32 = (uint32_t *)buff;
537 int k, written_bits = 0;
538
539 for (k = 0; k < (size / 4); k++) {
540 written_bits += hweight32(~buff32[k]);
541 if (written_bits > max_bits)
542 break;
543 }
544
545 return written_bits;
546}
547
Stefan Agnere24bb2b2015-10-13 22:11:42 -0700548static inline int vf610_nfc_correct_data(struct mtd_info *mtd, uint8_t *dat,
549 uint8_t *oob, int page)
Stefan Agner72d7bea2014-09-12 13:06:35 +0200550{
551 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
Stefan Agnere24bb2b2015-10-13 22:11:42 -0700552 u32 ecc_status_off = NFC_MAIN_AREA(0) + ECC_SRAM_ADDR + ECC_STATUS;
Stefan Agner72d7bea2014-09-12 13:06:35 +0200553 u8 ecc_status;
554 u8 ecc_count;
Stefan Agnere24bb2b2015-10-13 22:11:42 -0700555 int flips;
556 int flips_threshold = nfc->chip.ecc.strength / 2;
Stefan Agner72d7bea2014-09-12 13:06:35 +0200557
Stefan Agnere24bb2b2015-10-13 22:11:42 -0700558 ecc_status = vf610_nfc_read(mtd, ecc_status_off) & 0xff;
559 ecc_count = ecc_status & ECC_STATUS_ERR_COUNT;
560
Stefan Agner72d7bea2014-09-12 13:06:35 +0200561 if (!(ecc_status & ECC_STATUS_MASK))
562 return ecc_count;
563
Stefan Agnere24bb2b2015-10-13 22:11:42 -0700564 /* Read OOB without ECC unit enabled */
565 vf610_nfc_command(mtd, NAND_CMD_READOOB, 0, page);
566 vf610_nfc_read_buf(mtd, oob, mtd->oobsize);
Stefan Agner72d7bea2014-09-12 13:06:35 +0200567
Stefan Agnere24bb2b2015-10-13 22:11:42 -0700568 /*
569 * On an erased page, bit count (including OOB) should be zero or
570 * at least less then half of the ECC strength.
571 */
572 flips = count_written_bits(dat, nfc->chip.ecc.size, flips_threshold);
573 flips += count_written_bits(oob, mtd->oobsize, flips_threshold);
574
575 if (unlikely(flips > flips_threshold))
576 return -EINVAL;
Stefan Agner72d7bea2014-09-12 13:06:35 +0200577
578 /* Erased page. */
579 memset(dat, 0xff, nfc->chip.ecc.size);
Stefan Agnere24bb2b2015-10-13 22:11:42 -0700580 memset(oob, 0xff, mtd->oobsize);
581 return flips;
Stefan Agner72d7bea2014-09-12 13:06:35 +0200582}
583
Stefan Agner72d7bea2014-09-12 13:06:35 +0200584static int vf610_nfc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
585 uint8_t *buf, int oob_required, int page)
586{
587 int eccsize = chip->ecc.size;
588 int stat;
Stefan Agner72d7bea2014-09-12 13:06:35 +0200589
Stefan Agnere24bb2b2015-10-13 22:11:42 -0700590 vf610_nfc_read_buf(mtd, buf, eccsize);
Stefan Agner72d7bea2014-09-12 13:06:35 +0200591 if (oob_required)
592 vf610_nfc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
593
Stefan Agnere24bb2b2015-10-13 22:11:42 -0700594 stat = vf610_nfc_correct_data(mtd, buf, chip->oob_poi, page);
Stefan Agner72d7bea2014-09-12 13:06:35 +0200595
Stefan Agnere24bb2b2015-10-13 22:11:42 -0700596 if (stat < 0) {
Stefan Agner72d7bea2014-09-12 13:06:35 +0200597 mtd->ecc_stats.failed++;
Stefan Agnere24bb2b2015-10-13 22:11:42 -0700598 return 0;
599 } else {
Stefan Agner72d7bea2014-09-12 13:06:35 +0200600 mtd->ecc_stats.corrected += stat;
Stefan Agnere24bb2b2015-10-13 22:11:42 -0700601 return stat;
602 }
Stefan Agner72d7bea2014-09-12 13:06:35 +0200603}
604
605/*
606 * ECC will be calculated automatically
607 */
608static int vf610_nfc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
Scott Wood81c77252016-05-30 13:57:57 -0500609 const uint8_t *buf, int oob_required, int page)
Stefan Agner72d7bea2014-09-12 13:06:35 +0200610{
Stefan Agnere24bb2b2015-10-13 22:11:42 -0700611 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
612
Stefan Agner72d7bea2014-09-12 13:06:35 +0200613 vf610_nfc_write_buf(mtd, buf, mtd->writesize);
614 if (oob_required)
615 vf610_nfc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
616
Stefan Agnere24bb2b2015-10-13 22:11:42 -0700617 /* Always write whole page including OOB due to HW ECC */
618 nfc->write_sz = mtd->writesize + mtd->oobsize;
619
Stefan Agner72d7bea2014-09-12 13:06:35 +0200620 return 0;
621}
622
623struct vf610_nfc_config {
624 int hardware_ecc;
625 int width;
626 int flash_bbt;
627};
628
629static int vf610_nfc_nand_init(int devnum, void __iomem *addr)
630{
Scott Woodb616d9b2016-05-30 13:57:55 -0500631 struct mtd_info *mtd;
Stefan Agner72d7bea2014-09-12 13:06:35 +0200632 struct nand_chip *chip;
633 struct vf610_nfc *nfc;
634 int err = 0;
Stefan Agner72d7bea2014-09-12 13:06:35 +0200635 struct vf610_nfc_config cfg = {
636 .hardware_ecc = 1,
637#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
638 .width = 16,
639#else
640 .width = 8,
641#endif
642 .flash_bbt = 1,
643 };
644
645 nfc = malloc(sizeof(*nfc));
646 if (!nfc) {
647 printf(KERN_ERR "%s: Memory exhausted!\n", __func__);
648 return -ENOMEM;
649 }
650
651 chip = &nfc->chip;
652 nfc->regs = addr;
653
Scott Wood17cb4b82016-05-30 13:57:56 -0500654 mtd = nand_to_mtd(chip);
655 nand_set_controller_data(chip, nfc);
Stefan Agner72d7bea2014-09-12 13:06:35 +0200656
Stefan Agner8fca2d82015-05-08 19:07:13 +0200657 if (cfg.width == 16)
Stefan Agner72d7bea2014-09-12 13:06:35 +0200658 chip->options |= NAND_BUSWIDTH_16;
Stefan Agner8fca2d82015-05-08 19:07:13 +0200659
Stefan Agner72d7bea2014-09-12 13:06:35 +0200660 chip->dev_ready = vf610_nfc_dev_ready;
661 chip->cmdfunc = vf610_nfc_command;
662 chip->read_byte = vf610_nfc_read_byte;
663 chip->read_word = vf610_nfc_read_word;
664 chip->read_buf = vf610_nfc_read_buf;
665 chip->write_buf = vf610_nfc_write_buf;
666 chip->select_chip = vf610_nfc_select_chip;
667
Stefan Agnere24bb2b2015-10-13 22:11:42 -0700668 chip->options |= NAND_NO_SUBPAGE_WRITE;
669
670 chip->ecc.size = PAGE_2K;
Stefan Agner72d7bea2014-09-12 13:06:35 +0200671
Stefan Agner72d7bea2014-09-12 13:06:35 +0200672 /* Set configuration register. */
Stefan Agnere24bb2b2015-10-13 22:11:42 -0700673 vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_16BIT);
Stefan Agner72d7bea2014-09-12 13:06:35 +0200674 vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_ADDR_AUTO_INCR_BIT);
675 vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_BUFNO_AUTO_INCR_BIT);
676 vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_BOOT_MODE_BIT);
677 vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_DMA_REQ_BIT);
678 vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_FAST_FLASH_BIT);
679
Stefan Agnere24bb2b2015-10-13 22:11:42 -0700680 /* Disable virtual pages, only one elementary transfer unit */
Stefan Agner72d7bea2014-09-12 13:06:35 +0200681 vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG, CONFIG_PAGE_CNT_MASK,
682 CONFIG_PAGE_CNT_SHIFT, 1);
683
Stefan Agner72d7bea2014-09-12 13:06:35 +0200684 /* first scan to find the device and get the page size */
685 if (nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_DEVICE, NULL)) {
686 err = -ENXIO;
687 goto error;
688 }
689
Stefan Agner8fca2d82015-05-08 19:07:13 +0200690 if (cfg.width == 16)
691 vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_16BIT);
692
Stefan Agnere24bb2b2015-10-13 22:11:42 -0700693 /* Bad block options. */
694 if (cfg.flash_bbt)
695 chip->bbt_options = NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB |
696 NAND_BBT_CREATE;
Stefan Agner72d7bea2014-09-12 13:06:35 +0200697
Stefan Agner72d7bea2014-09-12 13:06:35 +0200698 /* Single buffer only, max 256 OOB minus ECC status */
Stefan Agnere24bb2b2015-10-13 22:11:42 -0700699 if (mtd->writesize + mtd->oobsize > PAGE_2K + OOB_MAX - 8) {
700 dev_err(nfc->dev, "Unsupported flash page size\n");
Stefan Agner72d7bea2014-09-12 13:06:35 +0200701 err = -ENXIO;
702 goto error;
703 }
Stefan Agner72d7bea2014-09-12 13:06:35 +0200704
705 if (cfg.hardware_ecc) {
706 if (mtd->writesize != PAGE_2K && mtd->oobsize < 64) {
707 dev_err(nfc->dev, "Unsupported flash with hwecc\n");
708 err = -ENXIO;
709 goto error;
710 }
711
Stefan Agnere24bb2b2015-10-13 22:11:42 -0700712 if (chip->ecc.size != mtd->writesize) {
713 dev_err(nfc->dev, "ecc size: %d\n", chip->ecc.size);
714 dev_err(nfc->dev, "Step size needs to be page size\n");
715 err = -ENXIO;
716 goto error;
717 }
718
Stefan Agner080a71e2015-05-08 19:07:12 +0200719 /* Current HW ECC layouts only use 64 bytes of OOB */
720 if (mtd->oobsize > 64)
721 mtd->oobsize = 64;
Stefan Agner72d7bea2014-09-12 13:06:35 +0200722
723 /* propagate ecc.layout to mtd_info */
724 mtd->ecclayout = chip->ecc.layout;
725 chip->ecc.read_page = vf610_nfc_read_page;
726 chip->ecc.write_page = vf610_nfc_write_page;
727 chip->ecc.mode = NAND_ECC_HW;
728
Stefan Agner72d7bea2014-09-12 13:06:35 +0200729 chip->ecc.size = PAGE_2K;
Stefan Agner080a71e2015-05-08 19:07:12 +0200730 chip->ecc.layout = &vf610_nfc_ecc;
731#if defined(CONFIG_SYS_NAND_VF610_NFC_45_ECC_BYTES)
Stefan Agner72d7bea2014-09-12 13:06:35 +0200732 chip->ecc.strength = 24;
Stefan Agner080a71e2015-05-08 19:07:12 +0200733 chip->ecc.bytes = 45;
734#elif defined(CONFIG_SYS_NAND_VF610_NFC_60_ECC_BYTES)
735 chip->ecc.strength = 32;
736 chip->ecc.bytes = 60;
737#endif
Stefan Agner72d7bea2014-09-12 13:06:35 +0200738
Stefan Agnere24bb2b2015-10-13 22:11:42 -0700739 /* Set ECC_STATUS offset */
740 vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG,
741 CONFIG_ECC_SRAM_ADDR_MASK,
742 CONFIG_ECC_SRAM_ADDR_SHIFT,
743 ECC_SRAM_ADDR >> 3);
744
745 /* Enable ECC status in SRAM */
Stefan Agner72d7bea2014-09-12 13:06:35 +0200746 vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_ECC_SRAM_REQ_BIT);
747 }
748
749 /* second phase scan */
750 err = nand_scan_tail(mtd);
751 if (err)
752 return err;
753
Scott Woodb616d9b2016-05-30 13:57:55 -0500754 err = nand_register(devnum, mtd);
Stefan Agner72d7bea2014-09-12 13:06:35 +0200755 if (err)
756 return err;
757
758 return 0;
759
760error:
761 return err;
762}
763
764void board_nand_init(void)
765{
766 int err = vf610_nfc_nand_init(0, (void __iomem *)CONFIG_SYS_NAND_BASE);
767 if (err)
768 printf("VF610 NAND init failed (err %d)\n", err);
769}