blob: cb506589d9690e1db20b0d965665c125148f7820 [file] [log] [blame]
Wolfgang Denk52568c32009-05-16 10:47:46 +02001/*
2 * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
3 * (C) Copyright 2009, DAVE Srl <www.dave.eu>
4 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
Wolfgang Denk52568c32009-05-16 10:47:46 +02006 */
7
8/*
9 * Aria board configuration file
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15#define CONFIG_ARIA 1
Anatolij Gustschin32ff89d2014-10-21 13:47:01 +020016#define CONFIG_DISPLAY_BOARDINFO
Anatolij Gustschin32ff89d2014-10-21 13:47:01 +020017
Wolfgang Denk52568c32009-05-16 10:47:46 +020018/*
19 * Memory map for the ARIA board:
20 *
21 * 0x0000_0000-0x0FFF_FFFF DDR RAM (256 MB)
22 * 0x3000_0000-0x3001_FFFF On Chip SRAM (128 KB)
23 * 0x3010_0000-0x3011_FFFF On Board SRAM (128 KB) - CS6
24 * 0x3020_0000-0x3021_FFFF FPGA (128 KB) - CS2
25 * 0x8000_0000-0x803F_FFFF IMMR (4 MB)
26 * 0x8400_0000-0x82FF_FFFF PCI I/O space (16 MB)
27 * 0xA000_0000-0xAFFF_FFFF PCI memory space (256 MB)
28 * 0xB000_0000-0xBFFF_FFFF PCI memory mapped I/O space (256 MB)
29 * 0xFC00_0000-0xFFFF_FFFF NOR Boot FLASH (64 MB)
30 */
31
32/*
33 * High Level Configuration Options
34 */
35#define CONFIG_E300 1 /* E300 Family */
Wolfgang Denk52568c32009-05-16 10:47:46 +020036#define CONFIG_FSL_DIU_FB 1 /* FSL DIU */
Wolfgang Denk52568c32009-05-16 10:47:46 +020037
Wolfgang Denk2ae18242010-10-06 09:05:45 +020038#define CONFIG_SYS_TEXT_BASE 0xFFF00000
39
Wolfgang Denk52568c32009-05-16 10:47:46 +020040/* video */
41#undef CONFIG_VIDEO
42
43#if defined(CONFIG_VIDEO)
44#define CONFIG_CFB_CONSOLE
45#define CONFIG_VGA_AS_SINGLE_DEVICE
46#endif
47
48/* CONFIG_PCI is defined at config time */
49
50#define CONFIG_SYS_MPC512X_CLKIN 33000000 /* in Hz */
51
Wolfgang Denk52568c32009-05-16 10:47:46 +020052#define CONFIG_MISC_INIT_R
53
54#define CONFIG_SYS_IMMR 0x80000000
55#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_IMMR+0x2100)
56
57#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
58#define CONFIG_SYS_MEMTEST_END 0x00400000
59
60/*
61 * DDR Setup - manually set all parameters as there's no SPD etc.
62 */
63#define CONFIG_SYS_DDR_SIZE 256 /* MB */
64#define CONFIG_SYS_DDR_BASE 0x00000000
65#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
Anatolij Gustschinb9947bb2010-04-24 19:27:08 +020066#define CONFIG_SYS_MAX_RAM_SIZE 0x20000000
Wolfgang Denk52568c32009-05-16 10:47:46 +020067
Anatolij Gustschin5d937e82010-04-24 19:27:07 +020068#define CONFIG_SYS_IOCTRL_MUX_DDR 0x00000036
69
Wolfgang Denk52568c32009-05-16 10:47:46 +020070/* DDR Controller Configuration
71 *
72 * SYS_CFG:
73 * [31:31] MDDRC Soft Reset: Diabled
74 * [30:30] DRAM CKE pin: Enabled
75 * [29:29] DRAM CLK: Enabled
76 * [28:28] Command Mode: Enabled (For initialization only)
77 * [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10]
78 * [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10]
79 * [20:19] Read Test: DON'T USE
80 * [18:18] Self Refresh: Enabled
81 * [17:17] 16bit Mode: Disabled
82 * [16:13] Ready Delay: 2
83 * [12:12] Half DQS Delay: Disabled
84 * [11:11] Quarter DQS Delay: Disabled
85 * [10:08] Write Delay: 2
86 * [07:07] Early ODT: Disabled
87 * [06:06] On DIE Termination: Disabled
88 * [05:05] FIFO Overflow Clear: DON'T USE here
89 * [04:04] FIFO Underflow Clear: DON'T USE here
90 * [03:03] FIFO Overflow Pending: DON'T USE here
91 * [02:02] FIFO Underlfow Pending: DON'T USE here
92 * [01:01] FIFO Overlfow Enabled: Enabled
93 * [00:00] FIFO Underflow Enabled: Enabled
94 * TIME_CFG0
95 * [31:16] DRAM Refresh Time: 0 CSB clocks
96 * [15:8] DRAM Command Time: 0 CSB clocks
97 * [07:00] DRAM Precharge Time: 0 CSB clocks
98 * TIME_CFG1
99 * [31:26] DRAM tRFC:
100 * [25:21] DRAM tWR1:
101 * [20:17] DRAM tWRT1:
102 * [16:11] DRAM tDRR:
103 * [10:05] DRAM tRC:
104 * [04:00] DRAM tRAS:
105 * TIME_CFG2
106 * [31:28] DRAM tRCD:
107 * [27:23] DRAM tFAW:
108 * [22:19] DRAM tRTW1:
109 * [18:15] DRAM tCCD:
110 * [14:10] DRAM tRTP:
111 * [09:05] DRAM tRP:
112 * [04:00] DRAM tRPA
113 */
Wolfgang Denk25671c82009-06-14 20:58:48 +0200114#define CONFIG_SYS_MDDRC_SYS_CFG ( (1 << 31) | /* RST_B */ \
115 (1 << 30) | /* CKE */ \
116 (1 << 29) | /* CLK_ON */ \
Martha M Stan054197b2009-09-21 14:07:14 -0400117 (0 << 28) | /* CMD_MODE */ \
Wolfgang Denk25671c82009-06-14 20:58:48 +0200118 (4 << 25) | /* DRAM_ROW_SELECT */ \
119 (3 << 21) | /* DRAM_BANK_SELECT */ \
120 (0 << 18) | /* SELF_REF_EN */ \
121 (0 << 17) | /* 16BIT_MODE */ \
122 (2 << 13) | /* RDLY */ \
123 (0 << 12) | /* HALF_DQS_DLY */ \
124 (1 << 11) | /* QUART_DQS_DLY */ \
125 (2 << 8) | /* WDLY */ \
126 (0 << 7) | /* EARLY_ODT */ \
127 (1 << 6) | /* ON_DIE_TERMINATE */ \
128 (0 << 5) | /* FIFO_OV_CLEAR */ \
129 (0 << 4) | /* FIFO_UV_CLEAR */ \
130 (0 << 1) | /* FIFO_OV_EN */ \
131 (0 << 0) /* FIFO_UV_EN */ \
132 )
133
Martha M Stan054197b2009-09-21 14:07:14 -0400134#define CONFIG_SYS_MDDRC_TIME_CFG0 0x030C3D2E
Wolfgang Denk25671c82009-06-14 20:58:48 +0200135#define CONFIG_SYS_MDDRC_TIME_CFG1 0x55D81189
136#define CONFIG_SYS_MDDRC_TIME_CFG2 0x34790863
Wolfgang Denk52568c32009-05-16 10:47:46 +0200137
Martha M Stan054197b2009-09-21 14:07:14 -0400138#define CONFIG_SYS_DDRCMD_NOP 0x01380000
139#define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400
Wolfgang Denk25671c82009-06-14 20:58:48 +0200140#define CONFIG_SYS_MICRON_EMR ( (1 << 24) | /* CMD_REQ */ \
141 (0 << 22) | /* DRAM_CS */ \
142 (0 << 21) | /* DRAM_RAS */ \
143 (0 << 20) | /* DRAM_CAS */ \
144 (0 << 19) | /* DRAM_WEB */ \
145 (1 << 16) | /* DRAM_BS[2:0] */ \
146 (0 << 15) | /* */ \
147 (0 << 12) | /* A12->out */ \
148 (0 << 11) | /* A11->RDQS */ \
149 (0 << 10) | /* A10->DQS# */ \
150 (0 << 7) | /* OCD program */ \
151 (0 << 6) | /* Rtt1 */ \
152 (0 << 3) | /* posted CAS# */ \
153 (0 << 2) | /* Rtt0 */ \
154 (1 << 1) | /* ODS */ \
155 (0 << 0) /* DLL */ \
156 )
157#define CONFIG_SYS_MICRON_EMR2 0x01020000
158#define CONFIG_SYS_MICRON_EMR3 0x01030000
Martha M Stan054197b2009-09-21 14:07:14 -0400159#define CONFIG_SYS_DDRCMD_RFSH 0x01080000
Wolfgang Denk52568c32009-05-16 10:47:46 +0200160#define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432
Wolfgang Denk25671c82009-06-14 20:58:48 +0200161#define CONFIG_SYS_MICRON_EMR_OCD ( (1 << 24) | /* CMD_REQ */ \
162 (0 << 22) | /* DRAM_CS */ \
163 (0 << 21) | /* DRAM_RAS */ \
164 (0 << 20) | /* DRAM_CAS */ \
165 (0 << 19) | /* DRAM_WEB */ \
166 (1 << 16) | /* DRAM_BS[2:0] */ \
167 (0 << 15) | /* */ \
168 (0 << 12) | /* A12->out */ \
169 (0 << 11) | /* A11->RDQS */ \
170 (1 << 10) | /* A10->DQS# */ \
171 (7 << 7) | /* OCD program */ \
172 (0 << 6) | /* Rtt1 */ \
173 (0 << 3) | /* posted CAS# */ \
174 (1 << 2) | /* Rtt0 */ \
175 (0 << 1) | /* ODS (Output Drive Strength) */ \
176 (0 << 0) /* DLL */ \
177 )
178
179/*
180 * Backward compatible definitions,
Stefan Roesea47a12b2010-04-15 16:07:28 +0200181 * so we do not have to change arch/powerpc/cpu/mpc512x/fixed_sdram.c
Wolfgang Denk25671c82009-06-14 20:58:48 +0200182 */
Martha M Stan054197b2009-09-21 14:07:14 -0400183#define CONFIG_SYS_DDRCMD_EM2 (CONFIG_SYS_MICRON_EMR2)
184#define CONFIG_SYS_DDRCMD_EM3 (CONFIG_SYS_MICRON_EMR3)
185#define CONFIG_SYS_DDRCMD_EN_DLL (CONFIG_SYS_MICRON_EMR)
186#define CONFIG_SYS_DDRCMD_OCD_DEFAULT (CONFIG_SYS_MICRON_EMR_OCD)
Wolfgang Denk52568c32009-05-16 10:47:46 +0200187
188/* DDR Priority Manager Configuration */
189#define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777
190#define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000
191#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001
192#define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC
193#define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA
194#define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666
195#define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555
196#define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444
197#define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444
198#define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555
199#define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558
200#define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111
201#define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122
202#define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa
203#define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa
204#define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666
205#define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666
206#define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111
207#define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111
208#define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111
209#define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111
210#define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111
211#define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111
212
213/*
214 * NOR FLASH on the Local Bus
215 */
216#define CONFIG_SYS_FLASH_CFI /* use the CFI code */
217#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
218#define CONFIG_SYS_FLASH_BASE 0xF8000000 /* start of FLASH */
219#define CONFIG_SYS_FLASH_SIZE 0x08000000 /* max flash size */
220
221#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
222#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
223#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
224#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* max sectors */
225
226#undef CONFIG_SYS_FLASH_CHECKSUM
227
Wolfgang Denka6d6d462009-06-14 20:58:51 +0200228/*
229 * NAND FLASH support
230 * drivers/mtd/nand/mpc5121_nfc.c (rev 2 silicon only)
231 */
Wolfgang Denk1f1f82f2009-06-14 20:58:52 +0200232#define CONFIG_CMD_NAND /* enable NAND support */
233#define CONFIG_JFFS2_NAND /* with JFFS2 on it */
Wolfgang Denka6d6d462009-06-14 20:58:51 +0200234#define CONFIG_NAND_MPC5121_NFC
235#define CONFIG_SYS_NAND_BASE 0x40000000
Wolfgang Denka6d6d462009-06-14 20:58:51 +0200236#define CONFIG_SYS_MAX_NAND_DEVICE 1
Wolfgang Denka6d6d462009-06-14 20:58:51 +0200237
Wolfgang Denka6d6d462009-06-14 20:58:51 +0200238/*
239 * Configuration parameters for MPC5121 NAND driver
240 */
241#define CONFIG_FSL_NFC_WIDTH 1
242#define CONFIG_FSL_NFC_WRITE_SIZE 2048
243#define CONFIG_FSL_NFC_SPARE_SIZE 64
244#define CONFIG_FSL_NFC_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
245
Wolfgang Denk52568c32009-05-16 10:47:46 +0200246#define CONFIG_SYS_SRAM_BASE 0x30000000
247#define CONFIG_SYS_SRAM_SIZE 0x00020000 /* 128 KB */
248
Wolfgang Denk25671c82009-06-14 20:58:48 +0200249/* Make two SRAM regions contiguous */
250#define CONFIG_SYS_ARIA_SRAM_BASE (CONFIG_SYS_SRAM_BASE + \
251 CONFIG_SYS_SRAM_SIZE)
252#define CONFIG_SYS_ARIA_SRAM_SIZE 0x00100000 /* reserve 1MB-window */
Anatolij Gustschin676c6692013-02-08 00:03:44 +0000253#define CONFIG_SYS_CS6_START CONFIG_SYS_ARIA_SRAM_BASE
254#define CONFIG_SYS_CS6_SIZE CONFIG_SYS_ARIA_SRAM_SIZE
Wolfgang Denk52568c32009-05-16 10:47:46 +0200255
256#define CONFIG_SYS_ARIA_FPGA_BASE (CONFIG_SYS_ARIA_SRAM_BASE + \
257 CONFIG_SYS_ARIA_SRAM_SIZE)
258#define CONFIG_SYS_ARIA_FPGA_SIZE 0x20000 /* 128 KB */
259
Anatolij Gustschin676c6692013-02-08 00:03:44 +0000260#define CONFIG_SYS_CS2_START CONFIG_SYS_ARIA_FPGA_BASE
261#define CONFIG_SYS_CS2_SIZE CONFIG_SYS_ARIA_FPGA_SIZE
262
Wolfgang Denk52568c32009-05-16 10:47:46 +0200263#define CONFIG_SYS_CS0_CFG 0x05059150
264#define CONFIG_SYS_CS2_CFG ( (5 << 24) | \
265 (5 << 16) | \
266 (1 << 15) | \
267 (0 << 14) | \
268 (0 << 13) | \
269 (1 << 12) | \
270 (0 << 10) | \
271 (3 << 8) | /* 32 bit */ \
272 (0 << 7) | \
273 (1 << 6) | \
274 (1 << 4) | \
275 (0 << 3) | \
276 (0 << 2) | \
277 (0 << 1) | \
278 (0 << 0) \
279 )
280#define CONFIG_SYS_CS6_CFG 0x05059150
281
282/* Use alternative CS timing for CS0 and CS2 */
283#define CONFIG_SYS_CS_ALETIMING 0x00000005
284
285/* Use SRAM for initial stack */
286#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE
Wolfgang Denk553f0982010-10-26 13:32:32 +0200287#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_SRAM_SIZE
Wolfgang Denk52568c32009-05-16 10:47:46 +0200288
Wolfgang Denk553f0982010-10-26 13:32:32 +0200289#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200290 GENERATED_GBL_DATA_SIZE)
Wolfgang Denk52568c32009-05-16 10:47:46 +0200291#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
292
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200293#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Wolfgang Denka6d6d462009-06-14 20:58:51 +0200294#define CONFIG_SYS_MONITOR_LEN (384 * 1024)
Wolfgang Denk52568c32009-05-16 10:47:46 +0200295
296#ifdef CONFIG_FSL_DIU_FB
297#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024)
298#else
299#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
300#endif
301
302/* FPGA */
303#define CONFIG_ARIA_FPGA 1
304
305/*
306 * Serial Port
307 */
308#define CONFIG_CONS_INDEX 1
Wolfgang Denk52568c32009-05-16 10:47:46 +0200309
310/*
311 * Serial console configuration
312 */
313#define CONFIG_PSC_CONSOLE 3 /* console on PSC3 */
Marek Vasutbfb31272012-09-16 16:07:24 +0200314#define CONFIG_SYS_PSC3
Wolfgang Denk52568c32009-05-16 10:47:46 +0200315#if CONFIG_PSC_CONSOLE != 3
316#error CONFIG_PSC_CONSOLE must be 3
317#endif
318
319#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
320#define CONFIG_SYS_BAUDRATE_TABLE \
321 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
322
323#define CONSOLE_FIFO_TX_SIZE FIFOC_PSC3_TX_SIZE
324#define CONSOLE_FIFO_TX_ADDR FIFOC_PSC3_TX_ADDR
325#define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE
326#define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR
327
328#define CONFIG_CMDLINE_EDITING 1 /* command line history */
Wolfgang Denk52568c32009-05-16 10:47:46 +0200329
330/*
331 * PCI
332 */
333#ifdef CONFIG_PCI
Gabor Juhos842033e2013-05-30 07:06:12 +0000334#define CONFIG_PCI_INDIRECT_BRIDGE
Wolfgang Denk52568c32009-05-16 10:47:46 +0200335
336#define CONFIG_SYS_PCI_MEM_BASE 0xA0000000
337#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
338#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
339#define CONFIG_SYS_PCI_MMIO_BASE (CONFIG_SYS_PCI_MEM_BASE + \
340 CONFIG_SYS_PCI_MEM_SIZE)
341#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
342#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
343#define CONFIG_SYS_PCI_IO_BASE 0x00000000
344#define CONFIG_SYS_PCI_IO_PHYS 0x84000000
345#define CONFIG_SYS_PCI_IO_SIZE 0x01000000 /* 16M */
346
347#define CONFIG_PCI_PNP /* do pci plug-and-play */
348
349#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
350
351#endif
352
353/* I2C */
354#define CONFIG_HARD_I2C /* I2C with hardware support */
Wolfgang Denk52568c32009-05-16 10:47:46 +0200355#define CONFIG_I2C_MULTI_BUS
Wolfgang Denk52568c32009-05-16 10:47:46 +0200356
357/* I2C speed and slave address */
358#define CONFIG_SYS_I2C_SPEED 100000
359#define CONFIG_SYS_I2C_SLAVE 0x7F
360#if 0
361#define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */
362#endif
363
364/*
365 * IIM - IC Identification Module
366 */
Benoît Thébaudeau83306922013-04-23 10:17:42 +0000367#undef CONFIG_FSL_IIM
Wolfgang Denk52568c32009-05-16 10:47:46 +0200368
369/*
370 * EEPROM configuration for Atmel AT24C32A-10TQ-2.7:
371 * 16-bit addresses, 10ms write delay, 32-Byte Page Write Mode
372 */
373#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
374#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
375#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
376#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
377
378/*
379 * Ethernet configuration
380 */
381#define CONFIG_MPC512x_FEC 1
Wolfgang Denk52568c32009-05-16 10:47:46 +0200382#define CONFIG_PHY_ADDR 0x17
383#define CONFIG_MII 1 /* MII PHY management */
384#define CONFIG_FEC_AN_TIMEOUT 1
385#define CONFIG_HAS_ETH0
386
387/*
388 * Environment
389 */
390#define CONFIG_ENV_IS_IN_FLASH 1
391/* This has to be a multiple of the flash sector size */
392#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
393 CONFIG_SYS_MONITOR_LEN)
394#define CONFIG_ENV_SIZE 0x2000
395#define CONFIG_ENV_SECT_SIZE 0x20000 /* one sector (256K) */
396
397/* Address and size of Redundant Environment Sector */
398#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \
399 CONFIG_ENV_SECT_SIZE)
400#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
401
402#define CONFIG_LOADS_ECHO 1
403#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
404
Wolfgang Denk52568c32009-05-16 10:47:46 +0200405#define CONFIG_CMD_EEPROM
406#undef CONFIG_CMD_FUSE
Wolfgang Denk52568c32009-05-16 10:47:46 +0200407#undef CONFIG_CMD_IDE
Wolfgang Denk1f1f82f2009-06-14 20:58:52 +0200408#define CONFIG_CMD_JFFS2
Wolfgang Denk52568c32009-05-16 10:47:46 +0200409#define CONFIG_CMD_REGINFO
410
411#if defined(CONFIG_PCI)
412#define CONFIG_CMD_PCI
413#endif
414
Wolfgang Denk1f1f82f2009-06-14 20:58:52 +0200415#if defined(CONFIG_CMD_IDE) || defined(CONFIG_CMD_EXT2)
Wolfgang Denk52568c32009-05-16 10:47:46 +0200416#define CONFIG_DOS_PARTITION
417#define CONFIG_MAC_PARTITION
418#define CONFIG_ISO_PARTITION
419#endif /* defined(CONFIG_CMD_IDE) */
420
421/*
Wolfgang Denk1f1f82f2009-06-14 20:58:52 +0200422 * Dynamic MTD partition support
423 */
424#define CONFIG_CMD_MTDPARTS
425#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
426#define CONFIG_FLASH_CFI_MTD
427#define MTDIDS_DEFAULT "nor0=f8000000.flash,nand0=mpc5121.nand"
428
429/*
430 * NOR flash layout:
431 *
432 * F8000000 - FEAFFFFF 107 MiB User Data
433 * FEB00000 - FFAFFFFF 16 MiB Root File System
434 * FFB00000 - FFFEFFFF 4 MiB Linux Kernel
435 * FFF00000 - FFFBFFFF 768 KiB U-Boot (up to 512 KiB) and 2 x * env
436 * FFFC0000 - FFFFFFFF 256 KiB Device Tree
437 *
438 * NAND flash layout: one big partition
439 */
440#define MTDPARTS_DEFAULT "mtdparts=f8000000.flash:107m(user)," \
441 "16m(rootfs)," \
442 "4m(kernel)," \
443 "768k(u-boot)," \
444 "256k(dtb);" \
445 "mpc5121.nand:-(data)"
446
447/*
Wolfgang Denk52568c32009-05-16 10:47:46 +0200448 * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock.
449 * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE
450 * is set to 0xFFFF, watchdog timeouts after about 64s. For details
451 * refer to chapter 36 of the MPC5121e Reference Manual.
452 */
453/* #define CONFIG_WATCHDOG */ /* enable watchdog */
454#define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
455
456 /*
457 * Miscellaneous configurable options
458 */
459#define CONFIG_SYS_LONGHELP /* undef to save memory */
460#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Wolfgang Denk52568c32009-05-16 10:47:46 +0200461
462#ifdef CONFIG_CMD_KGDB
463# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
464#else
465# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
466#endif
467
468/* Print Buffer Size */
469#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
470 sizeof(CONFIG_SYS_PROMPT) + 16)
471/* max number of command args */
472#define CONFIG_SYS_MAXARGS 32
473/* Boot Argument Buffer Size */
474#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
475
Wolfgang Denk52568c32009-05-16 10:47:46 +0200476/*
477 * For booting Linux, the board info and command line data
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700478 * have to be in the first 256 MB of memory, since this is
Wolfgang Denk52568c32009-05-16 10:47:46 +0200479 * the maximum mapped by the Linux kernel during initialization.
480 */
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700481#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
Wolfgang Denk52568c32009-05-16 10:47:46 +0200482
483/* Cache Configuration */
484#define CONFIG_SYS_DCACHE_SIZE 32768
485#define CONFIG_SYS_CACHELINE_SIZE 32
486#ifdef CONFIG_CMD_KGDB
487#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of 32 */
488#endif
489
490#define CONFIG_SYS_HID0_INIT 0x000000000
491#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
492 HID0_ICE)
493#define CONFIG_SYS_HID2 HID2_HBE
494
495#define CONFIG_HIGH_BATS 1 /* High BATs supported */
496
Wolfgang Denk52568c32009-05-16 10:47:46 +0200497#ifdef CONFIG_CMD_KGDB
498#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
Wolfgang Denk52568c32009-05-16 10:47:46 +0200499#endif
500
501/*
502 * Environment Configuration
503 */
504#define CONFIG_ENV_OVERWRITE
505#define CONFIG_TIMESTAMP
506
507#define CONFIG_HOSTNAME aria
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000508#define CONFIG_BOOTFILE "aria/uImage"
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000509#define CONFIG_ROOTPATH "/opt/eldk/ppc_6xx"
Wolfgang Denk52568c32009-05-16 10:47:46 +0200510
511#define CONFIG_LOADADDR 400000 /* default load addr */
512
Wolfgang Denk52568c32009-05-16 10:47:46 +0200513#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
514
515#define CONFIG_BAUDRATE 115200
516
517#define CONFIG_PREBOOT "echo;" \
518 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
519 "echo"
520
521#define CONFIG_EXTRA_ENV_SETTINGS \
522 "u-boot_addr_r=200000\0" \
523 "kernel_addr_r=600000\0" \
524 "fdt_addr_r=880000\0" \
525 "ramdisk_addr_r=900000\0" \
526 "u-boot_addr=FFF00000\0" \
Wolfgang Denk1f1f82f2009-06-14 20:58:52 +0200527 "kernel_addr=FFB00000\0" \
528 "fdt_addr=FFFC0000\0" \
529 "ramdisk_addr=FEB00000\0" \
Wolfgang Denk52568c32009-05-16 10:47:46 +0200530 "ramdiskfile=aria/uRamdisk\0" \
531 "u-boot=aria/u-boot.bin\0" \
532 "fdtfile=aria/aria.dtb\0" \
533 "netdev=eth0\0" \
534 "consdev=ttyPSC0\0" \
535 "nfsargs=setenv bootargs root=/dev/nfs rw " \
536 "nfsroot=${serverip}:${rootpath}\0" \
537 "ramargs=setenv bootargs root=/dev/ram rw\0" \
538 "addip=setenv bootargs ${bootargs} " \
539 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
540 ":${hostname}:${netdev}:off panic=1\0" \
541 "addtty=setenv bootargs ${bootargs} " \
542 "console=${consdev},${baudrate}\0" \
543 "flash_nfs=run nfsargs addip addtty;" \
544 "bootm ${kernel_addr} - ${fdt_addr}\0" \
545 "flash_self=run ramargs addip addtty;" \
546 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
547 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
548 "tftp ${fdt_addr_r} ${fdtfile};" \
549 "run nfsargs addip addtty;" \
550 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
551 "net_self=tftp ${kernel_addr_r} ${bootfile};" \
552 "tftp ${ramdisk_addr_r} ${ramdiskfile};" \
553 "tftp ${fdt_addr_r} ${fdtfile};" \
554 "run ramargs addip addtty;" \
555 "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
556 "load=tftp ${u-boot_addr_r} ${u-boot}\0" \
557 "update=protect off ${u-boot_addr} +${filesize};" \
558 "era ${u-boot_addr} +${filesize};" \
559 "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0" \
560 "upd=run load update\0" \
561 ""
562
563#define CONFIG_BOOTCOMMAND "run flash_self"
564
Wolfgang Denk52568c32009-05-16 10:47:46 +0200565#define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES 1
566
567#define OF_CPU "PowerPC,5121@0"
568#define OF_SOC_COMPAT "fsl,mpc5121-immr"
569#define OF_TBCLK (bd->bi_busfreq / 4)
570#define OF_STDOUT_PATH "/soc@80000000/serial@11300"
571
572/*-----------------------------------------------------------------------
573 * IDE/ATA stuff
574 *-----------------------------------------------------------------------
575 */
576
577#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
578#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
579#undef CONFIG_IDE_LED /* LED for IDE not supported */
580
581#define CONFIG_IDE_RESET /* reset for IDE supported */
582#define CONFIG_IDE_PREINIT
583
584#define CONFIG_SYS_IDE_MAXBUS 1 /* 1 IDE bus */
585#define CONFIG_SYS_IDE_MAXDEVICE 2 /* 1 drive per IDE bus */
586
587#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
588#define CONFIG_SYS_ATA_BASE_ADDR get_pata_base()
589
590/* Offset for data I/O RefMan MPC5121EE Table 28-10 */
591#define CONFIG_SYS_ATA_DATA_OFFSET (0x00A0)
592
593/* Offset for normal register accesses */
594#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
595
596/* Offset for alternate registers RefMan MPC5121EE Table 28-23 */
597#define CONFIG_SYS_ATA_ALT_OFFSET (0x00D8)
598
599/* Interval between registers */
600#define CONFIG_SYS_ATA_STRIDE 4
601
602#define ATA_BASE_ADDR get_pata_base()
603
604/*
605 * Control register bit definitions
606 */
607#define FSL_ATA_CTRL_FIFO_RST_B 0x80000000
608#define FSL_ATA_CTRL_ATA_RST_B 0x40000000
609#define FSL_ATA_CTRL_FIFO_TX_EN 0x20000000
610#define FSL_ATA_CTRL_FIFO_RCV_EN 0x10000000
611#define FSL_ATA_CTRL_DMA_PENDING 0x08000000
612#define FSL_ATA_CTRL_DMA_ULTRA 0x04000000
613#define FSL_ATA_CTRL_DMA_WRITE 0x02000000
614#define FSL_ATA_CTRL_IORDY_EN 0x01000000
615
Anatolij Gustschine5f53862013-02-08 00:03:45 +0000616/* Clocks in use */
617#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
618 CLOCK_SCCR1_LPC_EN | \
619 CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
620 CLOCK_SCCR1_PSCFIFO_EN | \
621 CLOCK_SCCR1_DDR_EN | \
622 CLOCK_SCCR1_FEC_EN | \
623 CLOCK_SCCR1_NFC_EN | \
624 CLOCK_SCCR1_PATA_EN | \
625 CLOCK_SCCR1_PCI_EN | \
626 CLOCK_SCCR1_TPR_EN)
627
628#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \
629 CLOCK_SCCR2_SPDIF_EN | \
630 CLOCK_SCCR2_DIU_EN | \
631 CLOCK_SCCR2_I2C_EN)
632
Wolfgang Denk52568c32009-05-16 10:47:46 +0200633#endif /* __CONFIG_H */