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Stefan Roese899620c2006-08-15 14:22:35 +02001/*
2 * (C) Copyright 2006
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24
25#include <common.h>
Stefan Roese94627322008-03-19 10:23:43 +010026#include <libfdt.h>
27#include <fdt_support.h>
Stefan Roese899620c2006-08-15 14:22:35 +020028#include <spd_sdram.h>
29#include <ppc4xx_enet.h>
Stefan Roese1c2ce222006-11-27 14:12:17 +010030#include <miiphy.h>
Stefan Roese94627322008-03-19 10:23:43 +010031#include <asm/processor.h>
Stefan Roese899620c2006-08-15 14:22:35 +020032
33DECLARE_GLOBAL_DATA_PTR;
34
35extern int alpr_fpga_init(void);
36
37int board_early_init_f (void)
38{
Stefan Roese1c2ce222006-11-27 14:12:17 +010039 /*-------------------------------------------------------------------------
40 * Initialize EBC CONFIG
41 *-------------------------------------------------------------------------*/
Stefan Roese5bc528f2006-10-07 11:35:25 +020042 mtebc(xbcfg, EBC_CFG_LE_UNLOCK |
43 EBC_CFG_PTD_DISABLE | EBC_CFG_RTC_64PERCLK |
44 EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS |
45 EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT |
46 EBC_CFG_PME_DISABLE | EBC_CFG_PR_32);
Stefan Roese899620c2006-08-15 14:22:35 +020047
48 /*--------------------------------------------------------------------
49 * Setup the interrupt controller polarities, triggers, etc.
50 *-------------------------------------------------------------------*/
51 mtdcr (uic0sr, 0xffffffff); /* clear all */
52 mtdcr (uic0er, 0x00000000); /* disable all */
53 mtdcr (uic0cr, 0x00000009); /* SMI & UIC1 crit are critical */
Stefan Roese1c2ce222006-11-27 14:12:17 +010054 mtdcr (uic0pr, 0xfffffe03); /* per manual */
55 mtdcr (uic0tr, 0x01c00000); /* per manual */
Stefan Roese899620c2006-08-15 14:22:35 +020056 mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */
57 mtdcr (uic0sr, 0xffffffff); /* clear all */
58
59 mtdcr (uic1sr, 0xffffffff); /* clear all */
60 mtdcr (uic1er, 0x00000000); /* disable all */
61 mtdcr (uic1cr, 0x00000000); /* all non-critical */
62 mtdcr (uic1pr, 0xffffe0ff); /* per ref-board manual */
63 mtdcr (uic1tr, 0x00ffc000); /* per ref-board manual */
64 mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
65 mtdcr (uic1sr, 0xffffffff); /* clear all */
66
67 mtdcr (uic2sr, 0xffffffff); /* clear all */
68 mtdcr (uic2er, 0x00000000); /* disable all */
69 mtdcr (uic2cr, 0x00000000); /* all non-critical */
70 mtdcr (uic2pr, 0xffffffff); /* per ref-board manual */
71 mtdcr (uic2tr, 0x00ff8c0f); /* per ref-board manual */
72 mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */
73 mtdcr (uic2sr, 0xffffffff); /* clear all */
74
75 mtdcr (uicb0sr, 0xfc000000); /* clear all */
76 mtdcr (uicb0er, 0x00000000); /* disable all */
77 mtdcr (uicb0cr, 0x00000000); /* all non-critical */
78 mtdcr (uicb0pr, 0xfc000000); /* */
79 mtdcr (uicb0tr, 0x00000000); /* */
80 mtdcr (uicb0vr, 0x00000001); /* */
Stefan Roese1c2ce222006-11-27 14:12:17 +010081
Stefan Roesef16c1da2007-01-06 15:56:13 +010082 /* Setup shutdown/SSD empty interrupt as inputs */
83 out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CFG_GPIO_SHUTDOWN | CFG_GPIO_SSD_EMPTY));
84 out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CFG_GPIO_SHUTDOWN | CFG_GPIO_SSD_EMPTY));
85
Stefan Roese1c2ce222006-11-27 14:12:17 +010086 /* Setup GPIO/IRQ multiplexing */
Stefan Roesef16c1da2007-01-06 15:56:13 +010087 mtsdr(sdr_pfc0, 0x01a33e00);
Stefan Roese899620c2006-08-15 14:22:35 +020088
89 return 0;
90}
91
Stefan Roese1c2ce222006-11-27 14:12:17 +010092int last_stage_init(void)
93{
94 unsigned short reg;
95
96 /*
97 * Configure LED's of both Marvell 88E1111 PHY's
98 *
99 * This has to be done after the 4xx ethernet driver is loaded,
100 * so "last_stage_init()" is the right place.
101 */
102 miiphy_read("ppc_4xx_eth2", CONFIG_PHY2_ADDR, 0x18, &reg);
103 reg |= 0x0001;
104 miiphy_write("ppc_4xx_eth2", CONFIG_PHY2_ADDR, 0x18, reg);
105 miiphy_read("ppc_4xx_eth3", CONFIG_PHY3_ADDR, 0x18, &reg);
106 reg |= 0x0001;
107 miiphy_write("ppc_4xx_eth3", CONFIG_PHY3_ADDR, 0x18, reg);
108
109 return 0;
110}
111
112static int board_rev(void)
113{
Stefan Roese1c2ce222006-11-27 14:12:17 +0100114 /* Setup as input */
Stefan Roesef16c1da2007-01-06 15:56:13 +0100115 out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CFG_GPIO_REV0 | CFG_GPIO_REV1));
116 out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CFG_GPIO_REV0 | CFG_GPIO_REV1));
Stefan Roese1c2ce222006-11-27 14:12:17 +0100117
Stefan Roesef16c1da2007-01-06 15:56:13 +0100118 return (in32(GPIO0_IR) >> 16) & 0x3;
Stefan Roese1c2ce222006-11-27 14:12:17 +0100119}
120
Stefan Roese899620c2006-08-15 14:22:35 +0200121int checkboard (void)
122{
123 char *s = getenv ("serial#");
124
125 printf ("Board: ALPR");
126 if (s != NULL) {
127 puts (", serial# ");
128 puts (s);
129 }
Stefan Roese1c2ce222006-11-27 14:12:17 +0100130 printf(" (Rev. %d)\n", board_rev());
Stefan Roese899620c2006-08-15 14:22:35 +0200131
132 return (0);
133}
134
135#if defined(CFG_DRAM_TEST)
136int testdram (void)
137{
138 uint *pstart = (uint *) 0x00000000;
139 uint *pend = (uint *) 0x08000000;
140 uint *p;
141
142 for (p = pstart; p < pend; p++)
143 *p = 0xaaaaaaaa;
144
145 for (p = pstart; p < pend; p++) {
146 if (*p != 0xaaaaaaaa) {
147 printf ("SDRAM test fails at: %08x\n", (uint) p);
148 return 1;
149 }
150 }
151
152 for (p = pstart; p < pend; p++)
153 *p = 0x55555555;
154
155 for (p = pstart; p < pend; p++) {
156 if (*p != 0x55555555) {
157 printf ("SDRAM test fails at: %08x\n", (uint) p);
158 return 1;
159 }
160 }
161 return 0;
162}
163#endif
164
165/*************************************************************************
166 * pci_pre_init
167 *
168 * This routine is called just prior to registering the hose and gives
169 * the board the opportunity to check things. Returning a value of zero
170 * indicates that things are bad & PCI initialization should be aborted.
171 *
172 * Different boards may wish to customize the pci controller structure
173 * (add regions, override default access routines, etc) or perform
174 * certain pre-initialization actions.
175 *
176 ************************************************************************/
Stefan Roese466fff12007-06-25 15:57:39 +0200177#if defined(CONFIG_PCI)
Stefan Roese899620c2006-08-15 14:22:35 +0200178int pci_pre_init(struct pci_controller * hose )
179{
180 unsigned long strap;
181
182 /*--------------------------------------------------------------------------+
183 * The ocotea board is always configured as the host & requires the
184 * PCI arbiter to be enabled.
185 *--------------------------------------------------------------------------*/
186 mfsdr(sdr_sdstp1, strap);
187 if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){
188 printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
189 return 0;
190 }
191
192 /* FPGA Init */
193 alpr_fpga_init ();
194
195 return 1;
196}
Stefan Roese466fff12007-06-25 15:57:39 +0200197#endif /* defined(CONFIG_PCI) */
Stefan Roese899620c2006-08-15 14:22:35 +0200198
199/*************************************************************************
200 * pci_target_init
201 *
202 * The bootstrap configuration provides default settings for the pci
203 * inbound map (PIM). But the bootstrap config choices are limited and
204 * may not be sufficient for a given board.
205 *
206 ************************************************************************/
207#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
208void pci_target_init(struct pci_controller * hose )
209{
210 /*--------------------------------------------------------------------------+
211 * Disable everything
212 *--------------------------------------------------------------------------*/
213 out32r( PCIX0_PIM0SA, 0 ); /* disable */
214 out32r( PCIX0_PIM1SA, 0 ); /* disable */
215 out32r( PCIX0_PIM2SA, 0 ); /* disable */
216 out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
217
218 /*--------------------------------------------------------------------------+
219 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
220 * options to not support sizes such as 128/256 MB.
221 *--------------------------------------------------------------------------*/
222 out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
223 out32r( PCIX0_PIM0LAH, 0 );
224 out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
225
226 out32r( PCIX0_BAR0, 0 );
227
228 /*--------------------------------------------------------------------------+
229 * Program the board's subsystem id/vendor id
230 *--------------------------------------------------------------------------*/
231 out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
232 out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
233
234 out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
235}
236#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
237
238/*************************************************************************
239 * is_pci_host
240 *
241 * This routine is called to determine if a pci scan should be
242 * performed. With various hardware environments (especially cPCI and
243 * PPMC) it's insufficient to depend on the state of the arbiter enable
244 * bit in the strap register, or generic host/adapter assumptions.
245 *
246 * Rather than hard-code a bad assumption in the general 440 code, the
247 * 440 pci code requires the board to decide at runtime.
248 *
249 * Return 0 for adapter mode, non-zero for host (monarch) mode.
250 *
251 *
252 ************************************************************************/
253#if defined(CONFIG_PCI)
Stefan Roese1c2ce222006-11-27 14:12:17 +0100254
255static void wait_for_pci_ready(void)
256{
257 /*
258 * Configure EREADY as input
259 */
260 out32(GPIO0_TCR, in32(GPIO0_TCR) & ~CFG_GPIO_EREADY);
261 udelay(1000);
262
263 for (;;) {
264 if (in32(GPIO0_IR) & CFG_GPIO_EREADY)
265 return;
266 }
267
268}
269
Stefan Roese899620c2006-08-15 14:22:35 +0200270int is_pci_host(struct pci_controller *hose)
271{
Stefan Roese1c2ce222006-11-27 14:12:17 +0100272 wait_for_pci_ready();
273 return 1; /* return 1 for host controller */
Stefan Roese899620c2006-08-15 14:22:35 +0200274}
275#endif /* defined(CONFIG_PCI) */
276
277/*************************************************************************
278 * pci_master_init
279 *
280 ************************************************************************/
281#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
282void pci_master_init(struct pci_controller *hose)
283{
Stefan Roese899620c2006-08-15 14:22:35 +0200284 /*--------------------------------------------------------------------------+
285 | PowerPC440 PCI Master configuration.
286 | Map PLB/processor addresses to PCI memory space.
287 | PLB address 0xA0000000-0xCFFFFFFF ==> PCI address 0x80000000-0xCFFFFFFF
288 | Use byte reversed out routines to handle endianess.
289 | Make this region non-prefetchable.
290 +--------------------------------------------------------------------------*/
291 out32r( PCIX0_POM0SA, 0 ); /* disable */
292 out32r( PCIX0_POM1SA, 0 ); /* disable */
293 out32r( PCIX0_POM2SA, 0 ); /* disable */
294
295 out32r(PCIX0_POM0LAL, CFG_PCI_MEMBASE); /* PMM0 Local Address */
296 out32r(PCIX0_POM0LAH, 0x00000003); /* PMM0 Local Address */
297 out32r(PCIX0_POM0PCIAL, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
298 out32r(PCIX0_POM0PCIAH, 0x00000000); /* PMM0 PCI High Address */
299 out32r(PCIX0_POM0SA, ~(0x10000000 - 1) | 1); /* 256MB + enable region */
300
301 out32r(PCIX0_POM1LAL, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
302 out32r(PCIX0_POM1LAH, 0x00000003); /* PMM0 Local Address */
303 out32r(PCIX0_POM1PCIAL, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
304 out32r(PCIX0_POM1PCIAH, 0x00000000); /* PMM0 PCI High Address */
305 out32r(PCIX0_POM1SA, ~(0x10000000 - 1) | 1); /* 256MB + enable region */
Stefan Roese899620c2006-08-15 14:22:35 +0200306}
307#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
308
309#ifdef CONFIG_POST
310/*
311 * Returns 1 if keys pressed to start the power-on long-running tests
312 * Called from board_init_f().
313 */
314int post_hotkeys_pressed(void)
315{
316
317 return (ctrlc());
318}
319#endif
Stefan Roese94627322008-03-19 10:23:43 +0100320
321#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
322void ft_board_setup(void *blob, bd_t *bd)
323{
324 u32 val[4];
325 int rc;
326
327 ft_cpu_setup(blob, bd);
328
329 /* Fixup NOR mapping */
330 val[0] = 0; /* chip select number */
331 val[1] = 0; /* always 0 */
332 val[2] = gd->bd->bi_flashstart;
333 val[3] = gd->bd->bi_flashsize;
334 rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
335 val, sizeof(val), 1);
336 if (rc)
337 printf("Unable to update property NOR mapping, err=%s\n",
338 fdt_strerror(rc));
339}
340#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */