blob: 9659f9ebd9a44a3cc5e480c1afc850979449be86 [file] [log] [blame]
Chander Kashyap0aee53b2012-02-05 23:01:47 +00001/*
2 * Copyright (C) 2011 Samsung Electronics
3 *
4 * Configuration settings for the SAMSUNG SMDK5250 (EXYNOS5250) board.
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#ifndef __CONFIG_H
26#define __CONFIG_H
27
28/* High Level Configuration Options */
29#define CONFIG_SAMSUNG /* in a SAMSUNG core */
30#define CONFIG_S5P /* S5P Family */
31#define CONFIG_EXYNOS5 /* which is in a Exynos5 Family */
32#define CONFIG_SMDK5250 /* which is in a SMDK5250 */
33
34#include <asm/arch/cpu.h> /* get chip and board defs */
35
36#define CONFIG_ARCH_CPU_INIT
37#define CONFIG_DISPLAY_CPUINFO
38#define CONFIG_DISPLAY_BOARDINFO
39
40/* Keep L2 Cache Disabled */
41#define CONFIG_SYS_DCACHE_OFF
42
43#define CONFIG_SYS_SDRAM_BASE 0x40000000
44#define CONFIG_SYS_TEXT_BASE 0x43E00000
45
46/* input clock of PLL: SMDK5250 has 24MHz input clock */
47#define CONFIG_SYS_CLK_FREQ 24000000
48
49#define CONFIG_SETUP_MEMORY_TAGS
50#define CONFIG_CMDLINE_TAG
51#define CONFIG_INITRD_TAG
52#define CONFIG_CMDLINE_EDITING
53
54/* MACH_TYPE_SMDK5250 macro will be removed once added to mach-types */
55#define MACH_TYPE_SMDK5250 3774
56#define CONFIG_MACH_TYPE MACH_TYPE_SMDK5250
57
58/* Power Down Modes */
59#define S5P_CHECK_SLEEP 0x00000BAD
60#define S5P_CHECK_DIDLE 0xBAD00000
61#define S5P_CHECK_LPA 0xABAD0000
62
63/* Offset for inform registers */
64#define INFORM0_OFFSET 0x800
65#define INFORM1_OFFSET 0x804
66
67/* Size of malloc() pool */
68#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))
69
70/* select serial console configuration */
71#define CONFIG_SERIAL_MULTI
72#define CONFIG_SERIAL1 /* use SERIAL 1 */
73#define CONFIG_BAUDRATE 115200
74#define EXYNOS5_DEFAULT_UART_OFFSET 0x010000
75
76#define TZPC_BASE_OFFSET 0x10000
77
78/* SD/MMC configuration */
79#define CONFIG_GENERIC_MMC
80#define CONFIG_MMC
81#define CONFIG_S5P_MMC
82
83#define CONFIG_BOARD_EARLY_INIT_F
84
85/* PWM */
86#define CONFIG_PWM
87
88/* allow to overwrite serial and ethaddr */
89#define CONFIG_ENV_OVERWRITE
90
91/* Command definition*/
92#include <config_cmd_default.h>
93
94#define CONFIG_CMD_PING
95#define CONFIG_CMD_ELF
96#define CONFIG_CMD_MMC
97#define CONFIG_CMD_EXT2
98#define CONFIG_CMD_FAT
Chander Kashyapbf936212012-02-09 01:26:19 +000099#define CONFIG_CMD_NET
Chander Kashyap0aee53b2012-02-05 23:01:47 +0000100
101#define CONFIG_BOOTDELAY 3
102#define CONFIG_ZERO_BOOTDELAY_CHECK
103
Chander Kashyap81e35202012-02-05 23:01:48 +0000104/* MMC SPL */
105#define CONFIG_SPL
106#define COPY_BL2_FNPTR_ADDR 0x02020030
107
Chander Kashyap0aee53b2012-02-05 23:01:47 +0000108#define CONFIG_BOOTCOMMAND "mmc read 40007000 451 2000; bootm 40007000"
109
110/* Miscellaneous configurable options */
111#define CONFIG_SYS_LONGHELP /* undef to save memory */
112#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
113#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
114#define CONFIG_SYS_PROMPT "SMDK5250 # "
115#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
116#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
117#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
118#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
119/* Boot Argument Buffer Size */
120#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
121/* memtest works on */
122#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
123#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000)
124#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
125
126#define CONFIG_SYS_HZ 1000
127
128/* valid baudrates */
129#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
130
131#define CONFIG_RD_LVL
132
133/* Stack sizes */
134#define CONFIG_STACKSIZE (256 << 10) /* 256KB */
135
136#define CONFIG_NR_DRAM_BANKS 8
137#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
138#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
139#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
140#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
141#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
142#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
143#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
144#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
145#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
146#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
147#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE
148#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
149#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE
150#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
151#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE
152#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
153#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE
154
155#define CONFIG_SYS_MONITOR_BASE 0x00000000
156
157/* FLASH and environment organization */
158#define CONFIG_SYS_NO_FLASH
159#undef CONFIG_CMD_IMLS
160#define CONFIG_IDENT_STRING " for SMDK5250"
161
162#define CONFIG_ENV_IS_IN_MMC
163#define CONFIG_SYS_MMC_ENV_DEV 0
164
165#define CONFIG_SECURE_BL1_ONLY
166
167/* Secure FW size configuration */
168#ifdef CONFIG_SECURE_BL1_ONLY
169#define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */
170#else
171#define CONFIG_SEC_FW_SIZE 0
172#endif
173
174/* Configuration of BL1, BL2, ENV Blocks on mmc */
175#define CONFIG_RES_BLOCK_SIZE (512)
176#define CONFIG_BL1_SIZE (16 << 10) /*16 K reserved for BL1*/
177#define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */
178#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */
179
180#define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE)
181#define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE)
182#define CONFIG_ENV_OFFSET (CONFIG_BL2_OFFSET + CONFIG_BL2_SIZE)
183
Chander Kashyap81e35202012-02-05 23:01:48 +0000184/* U-boot copy size from boot Media to DRAM.*/
185#define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512)
186#define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512)
Chander Kashyap0aee53b2012-02-05 23:01:47 +0000187#define CONFIG_DOS_PARTITION
188
189#define CONFIG_IRAM_STACK 0x02050000
190
191#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000)
192
Chander Kashyapbf936212012-02-09 01:26:19 +0000193/* Ethernet Controllor Driver */
194#ifdef CONFIG_CMD_NET
195#define CONFIG_SMC911X
196#define CONFIG_SMC911X_BASE 0x5000000
197#define CONFIG_SMC911X_16_BIT
198#define CONFIG_ENV_SROM_BANK 1
199#endif /*CONFIG_CMD_NET*/
200
Chander Kashyap0aee53b2012-02-05 23:01:47 +0000201/* Enable devicetree support */
202#define CONFIG_OF_LIBFDT
203
204#endif /* __CONFIG_H */