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wdenkba56f622004-02-06 23:19:44 +00001/*
Peter Tysere0299072009-07-17 19:01:07 -05002* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
Wolfgang Denk1a459662013-07-08 09:37:19 +02003 * SPDX-License-Identifier: GPL-2.0+
wdenkba56f622004-02-06 23:19:44 +00004*/
5
6#include <ppc_asm.tmpl>
Stefan Roesecf6eb6d2010-04-14 13:57:18 +02007#include <asm/mmu.h>
wdenkba56f622004-02-06 23:19:44 +00008#include <config.h>
Stefan Roese550650d2010-09-20 16:05:31 +02009#include <asm/ppc4xx.h>
wdenkba56f622004-02-06 23:19:44 +000010
Peter Tysere0299072009-07-17 19:01:07 -050011/*
wdenkba56f622004-02-06 23:19:44 +000012 * TLB TABLE
13 *
14 * This table is used by the cpu boot code to setup the initial tlb
15 * entries. Rather than make broad assumptions in the cpu source tree,
16 * this table lets each board set things up however they like.
17 *
Peter Tysere0299072009-07-17 19:01:07 -050018 * Pointer to the table is returned in r1
19 */
wdenkba56f622004-02-06 23:19:44 +000020
21 .section .bootpg,"ax"
22 .globl tlbtab
23
24tlbtab:
25 tlbtab_start
Stefan Roesecf6eb6d2010-04-14 13:57:18 +020026 tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG)
27 tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG)
28 tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_RWX | SA_IG)
29 tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG )
30 tlbentry( CONFIG_SYS_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_RWX | SA_IG )
31 tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG )
32 tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG )
wdenkba56f622004-02-06 23:19:44 +000033 tlbtab_end