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wdenkbf9e3b32004-02-12 00:47:09 +00001/*
wdenkbf9e3b32004-02-12 00:47:09 +00002 * (C) Copyright 2000-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
TsiChungLiewa1436a82007-08-16 13:20:50 -05005 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 *
wdenkbf9e3b32004-02-12 00:47:09 +00008 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#include <common.h>
28#include <watchdog.h>
29#include <asm/processor.h>
TsiChungLiew83ec20b2007-08-15 19:21:21 -050030#include <asm/immap.h>
Zachary P. Landaueacbd312006-01-26 17:35:56 -050031
wdenkbf9e3b32004-02-12 00:47:09 +000032#ifdef CONFIG_M5272
TsiChungLiew83ec20b2007-08-15 19:21:21 -050033int interrupt_init(void)
wdenkbf9e3b32004-02-12 00:47:09 +000034{
TsiChungLiew83ec20b2007-08-15 19:21:21 -050035 volatile intctrl_t *intp = (intctrl_t *) (MMAP_INTC);
wdenkbf9e3b32004-02-12 00:47:09 +000036
37 /* disable all external interrupts */
38 intp->int_icr1 = 0x88888888;
39 intp->int_icr2 = 0x88888888;
40 intp->int_icr3 = 0x88888888;
41 intp->int_icr4 = 0x88888888;
42 intp->int_pitr = 0x00000000;
43 /* initialize vector register */
44 intp->int_pivr = 0x40;
45
TsiChungLiew83ec20b2007-08-15 19:21:21 -050046 enable_interrupts();
wdenkbf9e3b32004-02-12 00:47:09 +000047
48 return 0;
49}
TsiChungLiew83ec20b2007-08-15 19:21:21 -050050
51#if defined(CONFIG_MCFTMR)
52void dtimer_intr_setup(void)
53{
54 volatile intctrl_t *intp = (intctrl_t *) (CFG_INTR_BASE);
55
56 intp->int_icr1 &= ~INT_ICR1_TMR3MASK;
57 intp->int_icr1 |= CFG_TMRINTR_PRI;
58}
59#endif /* CONFIG_MCFTMR */
60#endif /* CONFIG_M5272 */
wdenkbf9e3b32004-02-12 00:47:09 +000061
Zachary P. Landaueacbd312006-01-26 17:35:56 -050062#if defined(CONFIG_M5282) || defined(CONFIG_M5271)
TsiChungLiew83ec20b2007-08-15 19:21:21 -050063int interrupt_init(void)
wdenkbf9e3b32004-02-12 00:47:09 +000064{
TsiChungLiew83ec20b2007-08-15 19:21:21 -050065 volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);
66
67 /* Make sure all interrupts are disabled */
68 intp->imrl0 |= 0x1;
69
70 enable_interrupts();
wdenkbf9e3b32004-02-12 00:47:09 +000071 return 0;
72}
TsiChungLiew83ec20b2007-08-15 19:21:21 -050073
74#if defined(CONFIG_MCFTMR)
75void dtimer_intr_setup(void)
76{
77 volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);
78
79 intp->icr0[CFG_TMRINTR_NO] = CFG_TMRINTR_PRI;
80 intp->imrl0 &= ~0xFFFFFFFE;
81 intp->imrl0 &= ~CFG_TMRINTR_MASK;
82}
83#endif /* CONFIG_MCFTMR */
84#endif /* CONFIG_M5282 | CONFIG_M5271 */
stroese8c725b92004-12-16 18:09:49 +000085
TsiChungLiewa1436a82007-08-16 13:20:50 -050086#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
TsiChungLiew83ec20b2007-08-15 19:21:21 -050087int interrupt_init(void)
stroese8c725b92004-12-16 18:09:49 +000088{
TsiChungLiew83ec20b2007-08-15 19:21:21 -050089 enable_interrupts();
stroese8c725b92004-12-16 18:09:49 +000090
91 return 0;
92}
TsiChungLiew83ec20b2007-08-15 19:21:21 -050093
94#if defined(CONFIG_MCFTMR)
95void dtimer_intr_setup(void)
96{
97 mbar_writeLong(MCFSIM_IMR, mbar_readLong(MCFSIM_IMR) & ~0x00000400);
TsiChungLiewa1436a82007-08-16 13:20:50 -050098 mbar_writeByte(MCFSIM_TIMER2ICR, CFG_TMRINTR_PRI);
TsiChungLiew83ec20b2007-08-15 19:21:21 -050099}
100#endif /* CONFIG_MCFTMR */
TsiChungLiewa1436a82007-08-16 13:20:50 -0500101#endif /* CONFIG_M5249 || CONFIG_M5253 */