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wdenked247f42002-10-07 21:58:02 +00001/*
Wolfgang Denk8e6f1a82005-09-25 18:59:36 +02002 * (C) Copyright 2000-2005
wdenked247f42002-10-07 21:58:02 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
wdenk2abbe072003-06-16 23:50:08 +000015 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
wdenked247f42002-10-07 21:58:02 +000016 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#ifndef _FLASH_H_
25#define _FLASH_H_
26
27#ifndef CFG_NO_FLASH
28/*-----------------------------------------------------------------------
29 * FLASH Info: contains chip specific data, per FLASH bank
30 */
31
32typedef struct {
33 ulong size; /* total bank size in bytes */
34 ushort sector_count; /* number of erase units */
35 ulong flash_id; /* combined device & manufacturer code */
wdenk2abbe072003-06-16 23:50:08 +000036 ulong start[CFG_MAX_FLASH_SECT]; /* physical sector start addresses */
wdenked247f42002-10-07 21:58:02 +000037 uchar protect[CFG_MAX_FLASH_SECT]; /* sector protection status */
38#ifdef CFG_FLASH_CFI
39 uchar portwidth; /* the width of the port */
40 uchar chipwidth; /* the width of the chip */
wdenk2abbe072003-06-16 23:50:08 +000041 ushort buffer_size; /* # of bytes in write buffer */
wdenked247f42002-10-07 21:58:02 +000042 ulong erase_blk_tout; /* maximum block erase timeout */
43 ulong write_tout; /* maximum write timeout */
wdenk2abbe072003-06-16 23:50:08 +000044 ulong buffer_write_tout; /* maximum buffer write timeout */
wdenk1eaeb582004-06-08 00:22:43 +000045 ushort vendor; /* the primary vendor id */
Stefan Roese260421a2006-11-13 13:55:24 +010046 ushort cmd_reset; /* vendor specific reset command */
wdenk1eaeb582004-06-08 00:22:43 +000047 ushort interface; /* used for x8/x16 adjustments */
Stefan Roese2662b402006-04-01 13:41:03 +020048 ushort legacy_unlock; /* support Intel legacy (un)locking */
Stefan Roese260421a2006-11-13 13:55:24 +010049 uchar manufacturer_id; /* manufacturer id */
50 ushort device_id; /* device id */
51 ushort device_id2; /* extended device id */
52 ushort ext_addr; /* extended query table address */
53 ushort cfi_version; /* cfi version */
Stefano Babicd784fdb2006-12-12 00:22:42 +010054 ushort cfi_offset; /* offset for cfi query */
Michael Schwingen81b20cc2007-12-07 23:35:02 +010055 ulong addr_unlock1; /* unlock address 1 for AMD flash roms */
56 ulong addr_unlock2; /* unlock address 2 for AMD flash roms */
57 const char *name; /* human-readable name */
wdenked247f42002-10-07 21:58:02 +000058#endif
59} flash_info_t;
60
61/*
62 * Values for the width of the port
63 */
64#define FLASH_CFI_8BIT 0x01
65#define FLASH_CFI_16BIT 0x02
66#define FLASH_CFI_32BIT 0x04
67#define FLASH_CFI_64BIT 0x08
68/*
69 * Values for the width of the chip
70 */
71#define FLASH_CFI_BY8 0x01
72#define FLASH_CFI_BY16 0x02
73#define FLASH_CFI_BY32 0x04
74#define FLASH_CFI_BY64 0x08
wdenkbf9e3b32004-02-12 00:47:09 +000075/* convert between bit value and numeric value */
wdenk1eaeb582004-06-08 00:22:43 +000076#define CFI_FLASH_SHIFT_WIDTH 3
wdenkbf9e3b32004-02-12 00:47:09 +000077/*
78 * Values for the flash device interface
79 */
80#define FLASH_CFI_X8 0x00
81#define FLASH_CFI_X16 0x01
82#define FLASH_CFI_X8X16 0x02
Bartlomiej Sieka42026c92007-12-11 13:59:57 +010083#define FLASH_CFI_X16X32 0x05
wdenked247f42002-10-07 21:58:02 +000084
wdenk5653fc32004-02-08 22:55:38 +000085/* convert between bit value and numeric value */
wdenk1eaeb582004-06-08 00:22:43 +000086#define CFI_FLASH_SHIFT_WIDTH 3
wdenked247f42002-10-07 21:58:02 +000087/* Prototypes */
88
89extern unsigned long flash_init (void);
90extern void flash_print_info (flash_info_t *);
91extern int flash_erase (flash_info_t *, int, int);
92extern int flash_sect_erase (ulong addr_first, ulong addr_last);
93extern int flash_sect_protect (int flag, ulong addr_first, ulong addr_last);
94
95/* common/flash.c */
96extern void flash_protect (int flag, ulong from, ulong to, flash_info_t *info);
Wolfgang Denk77ddac92005-10-13 16:45:02 +020097extern int flash_write (char *, ulong, ulong);
wdenked247f42002-10-07 21:58:02 +000098extern flash_info_t *addr2info (ulong);
99extern int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt);
100
101/* board/?/flash.c */
102#if defined(CFG_FLASH_PROTECTION)
103extern int flash_real_protect(flash_info_t *info, long sector, int prot);
wdenk5653fc32004-02-08 22:55:38 +0000104extern void flash_read_user_serial(flash_info_t * info, void * buffer, int offset, int len);
105extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int offset, int len);
wdenked247f42002-10-07 21:58:02 +0000106#endif /* CFG_FLASH_PROTECTION */
107
Michael Schwingen81b20cc2007-12-07 23:35:02 +0100108#ifdef CONFIG_FLASH_CFI_LEGACY
109extern ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info);
110extern int jedec_flash_match(flash_info_t *info, ulong base);
111#define CFI_CMDSET_AMD_LEGACY 0xFFF0
112#endif
113
114
wdenked247f42002-10-07 21:58:02 +0000115/*-----------------------------------------------------------------------
116 * return codes from flash_write():
117 */
118#define ERR_OK 0
119#define ERR_TIMOUT 1
120#define ERR_NOT_ERASED 2
121#define ERR_PROTECTED 4
122#define ERR_INVAL 8
123#define ERR_ALIGN 16
124#define ERR_UNKNOWN_FLASH_VENDOR 32
125#define ERR_UNKNOWN_FLASH_TYPE 64
126#define ERR_PROG_ERROR 128
127
128/*-----------------------------------------------------------------------
129 * Protection Flags for flash_protect():
130 */
131#define FLAG_PROTECT_SET 0x01
132#define FLAG_PROTECT_CLEAR 0x02
Peter Pearsed4fc6012007-08-14 10:10:52 +0100133#define FLAG_PROTECT_INVALID 0x03
134/*-----------------------------------------------------------------------
135 * Set Environment according to label:
136 */
137#define FLAG_SETENV 0x80
wdenked247f42002-10-07 21:58:02 +0000138
139/*-----------------------------------------------------------------------
140 * Device IDs
141 */
142
wdenk2abbe072003-06-16 23:50:08 +0000143#define AMD_MANUFACT 0x00010001 /* AMD manuf. ID in D23..D16, D7..D0 */
wdenked247f42002-10-07 21:58:02 +0000144#define FUJ_MANUFACT 0x00040004 /* FUJITSU manuf. ID in D23..D16, D7..D0 */
wdenk2abbe072003-06-16 23:50:08 +0000145#define ATM_MANUFACT 0x001F001F /* ATMEL */
146#define STM_MANUFACT 0x00200020 /* STM (Thomson) manuf. ID in D23.. -"- */
147#define SST_MANUFACT 0x00BF00BF /* SST manuf. ID in D23..D16, D7..D0 */
148#define MT_MANUFACT 0x00890089 /* MT manuf. ID in D23..D16, D7..D0 */
wdenked247f42002-10-07 21:58:02 +0000149#define INTEL_MANUFACT 0x00890089 /* INTEL manuf. ID in D23..D16, D7..D0 */
wdenk2abbe072003-06-16 23:50:08 +0000150#define INTEL_ALT_MANU 0x00B000B0 /* alternate INTEL namufacturer ID */
wdenked247f42002-10-07 21:58:02 +0000151#define MX_MANUFACT 0x00C200C2 /* MXIC manuf. ID in D23..D16, D7..D0 */
wdenk608c9142003-01-13 23:54:46 +0000152#define TOSH_MANUFACT 0x00980098 /* TOSHIBA manuf. ID in D23..D16, D7..D0 */
wdenk1eaeb582004-06-08 00:22:43 +0000153#define MT2_MANUFACT 0x002C002C /* alternate MICRON manufacturer ID*/
Wolfgang Denk8e6f1a82005-09-25 18:59:36 +0200154#define EXCEL_MANUFACT 0x004A004A /* Excel Semiconductor */
wdenked247f42002-10-07 21:58:02 +0000155
156 /* Micron Technologies (INTEL compat.) */
157#define MT_ID_28F400_T 0x44704470 /* 28F400B3 ID ( 4 M, top boot sector) */
wdenk2abbe072003-06-16 23:50:08 +0000158#define MT_ID_28F400_B 0x44714471 /* 28F400B3 ID ( 4 M, bottom boot sect) */
wdenked247f42002-10-07 21:58:02 +0000159
160#define AMD_ID_LV040B 0x4F /* 29LV040B ID */
161 /* 4 Mbit, 512K x 8, */
162 /* 8 64K x 8 uniform sectors */
Wolfgang Denk8e6f1a82005-09-25 18:59:36 +0200163#define AMD_ID_F033C 0xA3 /* 29LV033C ID */
164 /* 32 Mbit, 4Mbits x 8, */
165 /* 64 64K x 8 uniform sectors */
166#define AMD_ID_F065D 0x93 /* 29LV065D ID */
167 /* 64 Mbit, 8Mbits x 8, */
168 /* 126 64K x 8 uniform sectors */
169#define ATM_ID_LV040 0x13 /* 29LV040B ID */
170 /* 4 Mbit, 512K x 8, */
171 /* 8 64K x 8 uniform sectors */
wdenked247f42002-10-07 21:58:02 +0000172#define AMD_ID_F040B 0xA4 /* 29F040B ID */
173 /* 4 Mbit, 512K x 8, */
174 /* 8 64K x 8 uniform sectors */
wdenk2abbe072003-06-16 23:50:08 +0000175#define STM_ID_M29W040B 0xE3 /* M29W040B ID */
wdenked247f42002-10-07 21:58:02 +0000176 /* 4 Mbit, 512K x 8, */
177 /* 8 64K x 8 uniform sectors */
178#define AMD_ID_F080B 0xD5 /* 29F080 ID ( 1 M) */
wdenk5d232d02003-05-22 22:52:13 +0000179 /* 8 Mbit, 512K x 16, */
180 /* 8 64K x 16 uniform sectors */
wdenked247f42002-10-07 21:58:02 +0000181#define AMD_ID_F016D 0xAD /* 29F016 ID ( 2 M x 8) */
182#define AMD_ID_F032B 0x41 /* 29F032 ID ( 4 M x 8) */
183#define AMD_ID_LV116DT 0xC7 /* 29LV116DT ( 2 M x 8, top boot sect) */
Wolfgang Denk8e6f1a82005-09-25 18:59:36 +0200184#define AMD_ID_LV116DB 0x4C /* 29LV116DB ( 2 M x 8, bottom boot sect) */
wdenk7a8e9bed2003-05-31 18:35:21 +0000185#define AMD_ID_LV016B 0xc8 /* 29LV016 ID ( 2 M x 8) */
wdenked247f42002-10-07 21:58:02 +0000186
Wolfgang Denk8e6f1a82005-09-25 18:59:36 +0200187#define AMD_ID_PL160CB 0x22452245 /* 29PL160CB ID (16 M, bottom boot sect */
wdenk4e5ca3e2003-12-08 01:34:36 +0000188
wdenked247f42002-10-07 21:58:02 +0000189#define AMD_ID_LV400T 0x22B922B9 /* 29LV400T ID ( 4 M, top boot sector) */
wdenk2abbe072003-06-16 23:50:08 +0000190#define AMD_ID_LV400B 0x22BA22BA /* 29LV400B ID ( 4 M, bottom boot sect) */
wdenked247f42002-10-07 21:58:02 +0000191
wdenkd1cbe852003-06-28 17:24:46 +0000192#define AMD_ID_LV033C 0xA3 /* 29LV033C ID ( 4 M x 8) */
193#define AMD_ID_LV065D 0x93 /* 29LV065D ID ( 8 M x 8) */
wdenked247f42002-10-07 21:58:02 +0000194
195#define AMD_ID_LV800T 0x22DA22DA /* 29LV800T ID ( 8 M, top boot sector) */
wdenk2abbe072003-06-16 23:50:08 +0000196#define AMD_ID_LV800B 0x225B225B /* 29LV800B ID ( 8 M, bottom boot sect) */
wdenked247f42002-10-07 21:58:02 +0000197
198#define AMD_ID_LV160T 0x22C422C4 /* 29LV160T ID (16 M, top boot sector) */
wdenk2abbe072003-06-16 23:50:08 +0000199#define AMD_ID_LV160B 0x22492249 /* 29LV160B ID (16 M, bottom boot sect) */
wdenked247f42002-10-07 21:58:02 +0000200
wdenk3bbc8992003-12-07 22:27:15 +0000201#define AMD_ID_DL163T 0x22282228 /* 29DL163T ID (16 M, top boot sector) */
Wolfgang Denk8e6f1a82005-09-25 18:59:36 +0200202#define AMD_ID_DL163B 0x222B222B /* 29DL163B ID (16 M, bottom boot sect) */
wdenk3bbc8992003-12-07 22:27:15 +0000203
wdenked247f42002-10-07 21:58:02 +0000204#define AMD_ID_LV320T 0x22F622F6 /* 29LV320T ID (32 M, top boot sector) */
wdenkefa329c2004-03-23 20:18:25 +0000205#define MX_ID_LV320T 0x22A722A7 /* 29LV320T by Macronix, AMD compatible */
wdenk2abbe072003-06-16 23:50:08 +0000206#define AMD_ID_LV320B 0x22F922F9 /* 29LV320B ID (32 M, bottom boot sect) */
wdenkefa329c2004-03-23 20:18:25 +0000207#define MX_ID_LV320B 0x22A822A8 /* 29LV320B by Macronix, AMD compatible */
wdenked247f42002-10-07 21:58:02 +0000208
209#define AMD_ID_DL322T 0x22552255 /* 29DL322T ID (32 M, top boot sector) */
wdenk2abbe072003-06-16 23:50:08 +0000210#define AMD_ID_DL322B 0x22562256 /* 29DL322B ID (32 M, bottom boot sect) */
wdenked247f42002-10-07 21:58:02 +0000211#define AMD_ID_DL323T 0x22502250 /* 29DL323T ID (32 M, top boot sector) */
wdenk2abbe072003-06-16 23:50:08 +0000212#define AMD_ID_DL323B 0x22532253 /* 29DL323B ID (32 M, bottom boot sect) */
wdenked247f42002-10-07 21:58:02 +0000213#define AMD_ID_DL324T 0x225C225C /* 29DL324T ID (32 M, top boot sector) */
214#define AMD_ID_DL324B 0x225F225F /* 29DL324B ID (32 M, bottom boot sect) */
215
216#define AMD_ID_DL640 0x227E227E /* 29DL640D ID (64 M, dual boot sectors)*/
wdenk2abbe072003-06-16 23:50:08 +0000217#define AMD_ID_MIRROR 0x227E227E /* 1st ID word for MirrorBit family */
Wolfgang Denk8e6f1a82005-09-25 18:59:36 +0200218#define AMD_ID_DL640G_2 0x22022202 /* 2nd ID word for AM29DL640G at 0x38 */
219#define AMD_ID_DL640G_3 0x22012201 /* 3rd ID word for AM29DL640G at 0x3c */
220#define AMD_ID_LV640U_2 0x220C220C /* 2nd ID word for AM29LV640M at 0x38 */
221#define AMD_ID_LV640U_3 0x22012201 /* 3rd ID word for AM29LV640M at 0x3c */
wdenkaa5590b2004-06-09 12:42:26 +0000222#define AMD_ID_LV640MT_2 0x22102210 /* 2nd ID word for AM29LV640MT at 0x38 */
223#define AMD_ID_LV640MT_3 0x22012201 /* 3rd ID word for AM29LV640MT at 0x3c */
224#define AMD_ID_LV640MB_2 0x22102210 /* 2nd ID word for AM29LV640MB at 0x38 */
225#define AMD_ID_LV640MB_3 0x22002200 /* 3rd ID word for AM29LV640MB at 0x3c */
226#define AMD_ID_LV128U_2 0x22122212 /* 2nd ID word for AM29LV128M at 0x38 */
227#define AMD_ID_LV128U_3 0x22002200 /* 3rd ID word for AM29LV128M at 0x3c */
228#define AMD_ID_LV256U_2 0x22122212 /* 2nd ID word for AM29LV256M at 0x38 */
229#define AMD_ID_LV256U_3 0x22012201 /* 3rd ID word for AM29LV256M at 0x3c */
wdenk9d5028c2004-11-21 00:06:33 +0000230#define AMD_ID_GL064M_2 0x22132213 /* 2nd ID word for S29GL064M-R6 */
231#define AMD_ID_GL064M_3 0x22012201 /* 3rd ID word for S29GL064M-R6 */
Wolfgang Denk45237bc2005-10-05 00:03:55 +0200232#define AMD_ID_GL064MT_2 0x22102210 /* 2nd ID word for S29GL064M-R3 (top boot sector) */
233#define AMD_ID_GL064MT_3 0x22012201 /* 3rd ID word for S29GL064M-R3 (top boot sector) */
Marian Balakowicz72997122006-10-03 20:28:38 +0200234#define AMD_ID_GL128N_2 0x22212221 /* 2nd ID word for S29GL128N */
235#define AMD_ID_GL128N_3 0x22012201 /* 3rd ID word for S29GL128N */
236
wdenkd4ca31c2004-01-02 14:00:00 +0000237
Wolfgang Denk8e6f1a82005-09-25 18:59:36 +0200238#define AMD_ID_LV320B_2 0x221A221A /* 2d ID word for AM29LV320MB at 0x38 */
wdenkd4ca31c2004-01-02 14:00:00 +0000239#define AMD_ID_LV320B_3 0x22002200 /* 3d ID word for AM29LV320MB at 0x3c */
wdenk71f95112003-06-15 22:40:42 +0000240
wdenked247f42002-10-07 21:58:02 +0000241#define AMD_ID_LV640U 0x22D722D7 /* 29LV640U ID (64 M, uniform sectors) */
Wolfgang Denk8e6f1a82005-09-25 18:59:36 +0200242#define AMD_ID_LV650U 0x22D722D7 /* 29LV650U ID (64 M, uniform sectors) */
wdenked247f42002-10-07 21:58:02 +0000243
wdenk8b07a112004-07-10 21:45:47 +0000244#define ATM_ID_BV1614 0x000000C0 /* 49BV1614 ID */
wdenk2abbe072003-06-16 23:50:08 +0000245#define ATM_ID_BV1614A 0x000000C8 /* 49BV1614A ID */
wdenk8b07a112004-07-10 21:45:47 +0000246#define ATM_ID_BV6416 0x000000D6 /* 49BV6416 ID */
wdenkdc7c9a12003-03-26 06:55:25 +0000247
wdenk2abbe072003-06-16 23:50:08 +0000248#define FUJI_ID_29F800BA 0x22582258 /* MBM29F800BA ID (8M) */
249#define FUJI_ID_29F800TA 0x22D622D6 /* MBM29F800TA ID (8M) */
wdenkbf9e3b32004-02-12 00:47:09 +0000250#define FUJI_ID_29LV650UE 0x22d722d7 /* MBM29LV650UE/651UE ID (8M = 128 x 32kWord) */
wdenk56f94be2002-11-05 16:35:14 +0000251
wdenk2abbe072003-06-16 23:50:08 +0000252#define SST_ID_xF200A 0x27892789 /* 39xF200A ID ( 2M = 128K x 16 ) */
253#define SST_ID_xF400A 0x27802780 /* 39xF400A ID ( 4M = 256K x 16 ) */
254#define SST_ID_xF800A 0x27812781 /* 39xF800A ID ( 8M = 512K x 16 ) */
255#define SST_ID_xF160A 0x27822782 /* 39xF800A ID (16M = 1M x 16 ) */
stroese4d535b52004-12-16 18:01:48 +0000256#define SST_ID_xF1601 0x234B234B /* 39xF1601 ID (16M = 1M x 16 ) */
257#define SST_ID_xF1602 0x234A234A /* 39xF1602 ID (16M = 1M x 16 ) */
258#define SST_ID_xF3201 0x235B235B /* 39xF3201 ID (32M = 2M x 16 ) */
259#define SST_ID_xF3202 0x235A235A /* 39xF3202 ID (32M = 2M x 16 ) */
260#define SST_ID_xF6401 0x236B236B /* 39xF6401 ID (64M = 4M x 16 ) */
261#define SST_ID_xF6402 0x236A236A /* 39xF6402 ID (64M = 4M x 16 ) */
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200262#define SST_ID_xF020 0xBFD6BFD6 /* 39xF020 ID (256KB = 2Mbit x 8) */
wdenkd1cbe852003-06-28 17:24:46 +0000263#define SST_ID_xF040 0xBFD7BFD7 /* 39xF040 ID (512KB = 4Mbit x 8) */
wdenked247f42002-10-07 21:58:02 +0000264
wdenk2abbe072003-06-16 23:50:08 +0000265#define STM_ID_F040B 0xE2 /* M29F040B ID ( 4M = 512K x 8 ) */
wdenked247f42002-10-07 21:58:02 +0000266 /* 8 64K x 8 uniform sectors */
267
wdenk2abbe072003-06-16 23:50:08 +0000268#define STM_ID_x800AB 0x005B005B /* M29W800AB ID (8M = 512K x 16 ) */
269#define STM_ID_29W320DT 0x22CA22CA /* M29W320DT ID (32 M, top boot sector) */
270#define STM_ID_29W320DB 0x22CB22CB /* M29W320DB ID (32 M, bottom boot sect) */
Aubrey Li8e709bb2007-03-19 01:26:11 +0800271#define STM_ID_29W320ET 0x22562256 /* M29W320ET ID (32 M, top boot sector) */
272#define STM_ID_29W320EB 0x22572257 /* M29W320EB ID (32 M, bottom boot sect)*/
wdenked247f42002-10-07 21:58:02 +0000273#define STM_ID_29W040B 0x00E300E3 /* M29W040B ID (4M = 512K x 8) */
Wolfgang Denk0afe5192006-03-12 02:10:00 +0100274#define FLASH_PSD4256GV 0x00E9 /* PSD4256 Flash and CPLD combination */
wdenked247f42002-10-07 21:58:02 +0000275
276#define INTEL_ID_28F016S 0x66a066a0 /* 28F016S[VS] ID (16M = 512k x 16) */
277#define INTEL_ID_28F800B3T 0x88928892 /* 8M = 512K x 16 top boot sector */
278#define INTEL_ID_28F800B3B 0x88938893 /* 8M = 512K x 16 bottom boot sector */
279#define INTEL_ID_28F160B3T 0x88908890 /* 16M = 1M x 16 top boot sector */
280#define INTEL_ID_28F160B3B 0x88918891 /* 16M = 1M x 16 bottom boot sector */
281#define INTEL_ID_28F320B3T 0x88968896 /* 32M = 2M x 16 top boot sector */
282#define INTEL_ID_28F320B3B 0x88978897 /* 32M = 2M x 16 bottom boot sector */
283#define INTEL_ID_28F640B3T 0x88988898 /* 64M = 4M x 16 top boot sector */
284#define INTEL_ID_28F640B3B 0x88998899 /* 64M = 4M x 16 bottom boot sector */
285#define INTEL_ID_28F160F3B 0x88F488F4 /* 16M = 1M x 16 bottom boot sector */
286
287#define INTEL_ID_28F800C3T 0x88C088C0 /* 8M = 512K x 16 top boot sector */
288#define INTEL_ID_28F800C3B 0x88C188C1 /* 8M = 512K x 16 bottom boot sector */
289#define INTEL_ID_28F160C3T 0x88C288C2 /* 16M = 1M x 16 top boot sector */
290#define INTEL_ID_28F160C3B 0x88C388C3 /* 16M = 1M x 16 bottom boot sector */
291#define INTEL_ID_28F320C3T 0x88C488C4 /* 32M = 2M x 16 top boot sector */
292#define INTEL_ID_28F320C3B 0x88C588C5 /* 32M = 2M x 16 bottom boot sector */
293#define INTEL_ID_28F640C3T 0x88CC88CC /* 64M = 4M x 16 top boot sector */
294#define INTEL_ID_28F640C3B 0x88CD88CD /* 64M = 4M x 16 bottom boot sector */
295
wdenkf6e20fc2004-02-08 19:38:38 +0000296#define INTEL_ID_28F128J3 0x89188918 /* 16M = 8M x 16 x 128 */
wdenk6dd652f2003-06-19 23:40:20 +0000297#define INTEL_ID_28F320J5 0x00140014 /* 32M = 128K x 32 */
298#define INTEL_ID_28F640J5 0x00150015 /* 64M = 128K x 64 */
299#define INTEL_ID_28F320J3A 0x00160016 /* 32M = 128K x 32 */
300#define INTEL_ID_28F640J3A 0x00170017 /* 64M = 128K x 64 */
301#define INTEL_ID_28F128J3A 0x00180018 /* 128M = 128K x 128 */
Wolfgang Denk97c8d0b2005-12-22 01:50:50 +0100302#define INTEL_ID_28F256J3A 0x001D001D /* 256M = 128K x 256 */
wdenk6f213472003-08-29 22:00:43 +0000303#define INTEL_ID_28F256L18T 0x880D880D /* 256M = 128K x 255 + 32k x 4 */
wdenkb54d32b2004-06-10 21:34:36 +0000304#define INTEL_ID_28F64K3 0x88018801 /* 64M = 32K x 255 + 32k x 4 */
305#define INTEL_ID_28F128K3 0x88028802 /* 128M = 64K x 255 + 32k x 4 */
306#define INTEL_ID_28F256K3 0x88038803 /* 256M = 128K x 255 + 32k x 4 */
Stefan Roese79b4cda2006-02-28 15:29:58 +0100307#define INTEL_ID_28F64P30T 0x88178817 /* 64M = 32K x 255 + 32k x 4 */
308#define INTEL_ID_28F64P30B 0x881A881A /* 64M = 32K x 255 + 32k x 4 */
309#define INTEL_ID_28F128P30T 0x88188818 /* 128M = 64K x 255 + 32k x 4 */
310#define INTEL_ID_28F128P30B 0x881B881B /* 128M = 64K x 255 + 32k x 4 */
311#define INTEL_ID_28F256P30T 0x88198819 /* 256M = 128K x 255 + 32k x 4 */
312#define INTEL_ID_28F256P30B 0x881C881C /* 256M = 128K x 255 + 32k x 4 */
wdenked247f42002-10-07 21:58:02 +0000313
314#define INTEL_ID_28F160S3 0x00D000D0 /* 16M = 512K x 32 (64kB x 32) */
315#define INTEL_ID_28F320S3 0x00D400D4 /* 32M = 512K x 64 (64kB x 64) */
316
317/* Note that the Sharp 28F016SC is compatible with the Intel E28F016SC */
318#define SHARP_ID_28F016SCL 0xAAAAAAAA /* LH28F016SCT-L95 2Mx8, 32 64k blocks */
319#define SHARP_ID_28F016SCZ 0xA0A0A0A0 /* LH28F016SCT-Z4 2Mx8, 32 64k blocks */
320#define SHARP_ID_28F008SC 0xA6A6A6A6 /* LH28F008SCT-L12 1Mx8, 16 64k blocks */
321 /* LH28F008SCR-L85 1Mx8, 16 64k blocks */
322
wdenk2abbe072003-06-16 23:50:08 +0000323#define TOSH_ID_FVT160 0xC2 /* TC58FVT160 ID (16 M, top ) */
324#define TOSH_ID_FVB160 0x43 /* TC58FVT160 ID (16 M, bottom ) */
Gary Jennejohn6bd24472007-01-24 12:16:56 +0100325#define PHILIPS_LPC2292 0x0401FF13 /* LPC2292 internal FLASH */
wdenk608c9142003-01-13 23:54:46 +0000326
wdenked247f42002-10-07 21:58:02 +0000327/*-----------------------------------------------------------------------
328 * Internal FLASH identification codes
329 *
330 * Be careful when adding new type! Odd numbers are "bottom boot sector" types!
331 */
332
wdenk2abbe072003-06-16 23:50:08 +0000333#define FLASH_AM040 0x0001 /* AMD Am29F040B, Am29LV040B */
334 /* Bright Micro BM29F040 */
335 /* Fujitsu MBM29F040A */
336 /* STM M29W040B */
337 /* SGS Thomson M29F040B */
338 /* 8 64K x 8 uniform sectors */
wdenked247f42002-10-07 21:58:02 +0000339#define FLASH_AM400T 0x0002 /* AMD AM29LV400 */
340#define FLASH_AM400B 0x0003
341#define FLASH_AM800T 0x0004 /* AMD AM29LV800 */
342#define FLASH_AM800B 0x0005
343#define FLASH_AM116DT 0x0026 /* AMD AM29LV116DT (2Mx8bit) */
wdenk138ff602004-12-16 15:52:40 +0000344#define FLASH_AM116DB 0x0027 /* AMD AM29LV116DB (2Mx8bit) */
wdenked247f42002-10-07 21:58:02 +0000345#define FLASH_AM160T 0x0006 /* AMD AM29LV160 */
wdenk2abbe072003-06-16 23:50:08 +0000346#define FLASH_AM160LV 0x0046 /* AMD29LV160DB (2M = 2Mx8bit ) */
wdenked247f42002-10-07 21:58:02 +0000347#define FLASH_AM160B 0x0007
348#define FLASH_AM320T 0x0008 /* AMD AM29LV320 */
349#define FLASH_AM320B 0x0009
350
wdenk2abbe072003-06-16 23:50:08 +0000351#define FLASH_AM080 0x000A /* AMD Am29F080B */
352 /* 16 64K x 8 uniform sectors */
wdenk5d232d02003-05-22 22:52:13 +0000353
wdenked247f42002-10-07 21:58:02 +0000354#define FLASH_AMDL322T 0x0010 /* AMD AM29DL322 */
355#define FLASH_AMDL322B 0x0011
356#define FLASH_AMDL323T 0x0012 /* AMD AM29DL323 */
357#define FLASH_AMDL323B 0x0013
358#define FLASH_AMDL324T 0x0014 /* AMD AM29DL324 */
359#define FLASH_AMDL324B 0x0015
360
Wolfgang Denk8e6f1a82005-09-25 18:59:36 +0200361#define FLASH_AMDLV033C 0x0018
362#define FLASH_AMDLV065D 0x001A
wdenkd1cbe852003-06-28 17:24:46 +0000363
wdenked247f42002-10-07 21:58:02 +0000364#define FLASH_AMDL640 0x0016 /* AMD AM29DL640D */
365#define FLASH_AMD016 0x0018 /* AMD AM29F016D */
Wolfgang Denk8e6f1a82005-09-25 18:59:36 +0200366#define FLASH_AMDL640MB 0x0019 /* AMD AM29LV640MB (64M, bottom boot sect)*/
367#define FLASH_AMDL640MT 0x001A /* AMD AM29LV640MT (64M, top boot sect) */
wdenked247f42002-10-07 21:58:02 +0000368
369#define FLASH_SST200A 0x0040 /* SST 39xF200A ID ( 2M = 128K x 16 ) */
370#define FLASH_SST400A 0x0042 /* SST 39xF400A ID ( 4M = 256K x 16 ) */
371#define FLASH_SST800A 0x0044 /* SST 39xF800A ID ( 8M = 512K x 16 ) */
372#define FLASH_SST160A 0x0046 /* SST 39xF160A ID ( 16M = 1M x 16 ) */
stroese4d535b52004-12-16 18:01:48 +0000373#define FLASH_SST320 0x0048 /* SST 39xF160A ID ( 16M = 1M x 16 ) */
374#define FLASH_SST640 0x004A /* SST 39xF160A ID ( 16M = 1M x 16 ) */
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200375#define FLASH_SST020 0x0024 /* SST 39xF020 ID (256KB = 2Mbit x 8 ) */
wdenkd1cbe852003-06-28 17:24:46 +0000376#define FLASH_SST040 0x000E /* SST 39xF040 ID (512KB = 4Mbit x 8 ) */
wdenked247f42002-10-07 21:58:02 +0000377
378#define FLASH_STM800AB 0x0051 /* STM M29WF800AB ( 8M = 512K x 16 ) */
wdenk2abbe072003-06-16 23:50:08 +0000379#define FLASH_STMW320DT 0x0052 /* STM M29W320DT (32 M, top boot sector) */
380#define FLASH_STMW320DB 0x0053 /* STM M29W320DB (32 M, bottom boot sect)*/
wdenked247f42002-10-07 21:58:02 +0000381#define FLASH_STM320DB 0x00CB /* STM M29W320DB (4M = 64K x 64, bottom)*/
382#define FLASH_STM800DT 0x00D7 /* STM M29W800DT (1M = 64K x 16, top) */
383#define FLASH_STM800DB 0x005B /* STM M29W800DB (1M = 64K x 16, bottom)*/
384
385#define FLASH_28F400_T 0x0062 /* MT 28F400B3 ID ( 4M = 256K x 16 ) */
386#define FLASH_28F400_B 0x0063 /* MT 28F400B3 ID ( 4M = 256K x 16 ) */
387
388#define FLASH_INTEL800T 0x0074 /* INTEL 28F800B3T ( 8M = 512K x 16 ) */
389#define FLASH_INTEL800B 0x0075 /* INTEL 28F800B3B ( 8M = 512K x 16 ) */
390#define FLASH_INTEL160T 0x0076 /* INTEL 28F160B3T ( 16M = 1 M x 16 ) */
391#define FLASH_INTEL160B 0x0077 /* INTEL 28F160B3B ( 16M = 1 M x 16 ) */
392#define FLASH_INTEL320T 0x0078 /* INTEL 28F320B3T ( 32M = 2 M x 16 ) */
393#define FLASH_INTEL320B 0x0079 /* INTEL 28F320B3B ( 32M = 2 M x 16 ) */
394#define FLASH_INTEL640T 0x007A /* INTEL 28F320B3T ( 64M = 4 M x 16 ) */
395#define FLASH_INTEL640B 0x007B /* INTEL 28F320B3B ( 64M = 4 M x 16 ) */
396
wdenked247f42002-10-07 21:58:02 +0000397#define FLASH_28F008S5 0x0080 /* Intel 28F008S5 ( 1M = 64K x 16 ) */
398#define FLASH_28F016SV 0x0081 /* Intel 28F016SV ( 16M = 512k x 32 ) */
399#define FLASH_28F800_B 0x0083 /* Intel E28F800B ( 1M = ? ) */
wdenk2abbe072003-06-16 23:50:08 +0000400#define FLASH_AM29F800B 0x0084 /* AMD Am29F800BB ( 1M = ? ) */
wdenked247f42002-10-07 21:58:02 +0000401#define FLASH_28F320J5 0x0085 /* Intel 28F320J5 ( 4M = 128K x 32 ) */
402#define FLASH_28F160S3 0x0086 /* Intel 28F160S3 ( 16M = 512K x 32 ) */
403#define FLASH_28F320S3 0x0088 /* Intel 28F320S3 ( 32M = 512K x 64 ) */
404#define FLASH_AM640U 0x0090 /* AMD Am29LV640U ( 64M = 4M x 16 ) */
405#define FLASH_AM033C 0x0091 /* AMD AM29LV033 ( 32M = 4M x 8 ) */
wdenk2abbe072003-06-16 23:50:08 +0000406#define FLASH_LH28F016SCT 0x0092 /* Sharp 28F016SCT ( 8 Meg Flash SIMM ) */
407#define FLASH_28F160F3B 0x0093 /* Intel 28F160F3B ( 16M = 1M x 16 ) */
Wolfgang Denk8e6f1a82005-09-25 18:59:36 +0200408#define FLASH_AM065D 0x0093
wdenked247f42002-10-07 21:58:02 +0000409
wdenk2abbe072003-06-16 23:50:08 +0000410#define FLASH_28F640J5 0x0099 /* INTEL 28F640J5 ( 64M = 128K x 64) */
wdenked247f42002-10-07 21:58:02 +0000411
wdenk2abbe072003-06-16 23:50:08 +0000412#define FLASH_28F800C3T 0x009A /* Intel 28F800C3T ( 8M = 512K x 16 ) */
413#define FLASH_28F800C3B 0x009B /* Intel 28F800C3B ( 8M = 512K x 16 ) */
414#define FLASH_28F160C3T 0x009C /* Intel 28F160C3T ( 16M = 1M x 16 ) */
415#define FLASH_28F160C3B 0x009D /* Intel 28F160C3B ( 16M = 1M x 16 ) */
416#define FLASH_28F320C3T 0x009E /* Intel 28F320C3T ( 32M = 2M x 16 ) */
417#define FLASH_28F320C3B 0x009F /* Intel 28F320C3B ( 32M = 2M x 16 ) */
418#define FLASH_28F640C3T 0x00A0 /* Intel 28F640C3T ( 64M = 4M x 16 ) */
419#define FLASH_28F640C3B 0x00A1 /* Intel 28F640C3B ( 64M = 4M x 16 ) */
Wolfgang Denk8e6f1a82005-09-25 18:59:36 +0200420#define FLASH_AMLV320U 0x00A2 /* AMD 29LV320M ( 32M = 2M x 16 ) */
421
422#define FLASH_AM033 0x00A3 /* AMD AmL033C90V1 (32M = 4M x 8) */
423#define FLASH_AM065 0x0093 /* AMD AmL065DU12RI (64M = 8M x 8) */
424#define FLASH_AT040 0x00A5 /* Amtel AT49LV040 (4M = 512K x 8) */
425
426#define FLASH_AMLV640U 0x00A4 /* AMD 29LV640M ( 64M = 4M x 16 ) */
wdenkf12e5682003-07-07 20:07:54 +0000427#define FLASH_AMLV128U 0x00A6 /* AMD 29LV128M ( 128M = 8M x 16 ) */
Wolfgang Denk8e6f1a82005-09-25 18:59:36 +0200428#define FLASH_AMLV320B 0x00A7 /* AMD 29LV320MB ( 32M = 2M x 16 ) */
wdenkd4ca31c2004-01-02 14:00:00 +0000429#define FLASH_AMLV320T 0x00A8 /* AMD 29LV320MT ( 32M = 2M x 16 ) */
wdenk4d13cba2004-03-14 14:09:05 +0000430#define FLASH_AMLV256U 0x00AA /* AMD 29LV256M ( 256M = 16M x 16 ) */
Wolfgang Denk8e6f1a82005-09-25 18:59:36 +0200431#define FLASH_MXLV320B 0x00AB /* MX 29LV320MB ( 32M = 2M x 16 ) */
wdenkefa329c2004-03-23 20:18:25 +0000432#define FLASH_MXLV320T 0x00AC /* MX 29LV320MT ( 32M = 2M x 16 ) */
wdenkb54d32b2004-06-10 21:34:36 +0000433#define FLASH_28F256L18T 0x00B0 /* Intel 28F256L18T 256M = 128K x 255 + 32k x 4 */
wdenkd4ca31c2004-01-02 14:00:00 +0000434#define FLASH_AMDL163T 0x00B2 /* AMD AM29DL163T (2M x 16 ) */
435#define FLASH_AMDL163B 0x00B3
wdenkb54d32b2004-06-10 21:34:36 +0000436#define FLASH_28F64K3 0x00B4 /* Intel 28F64K3 ( 64M) */
Wolfgang Denk8e6f1a82005-09-25 18:59:36 +0200437#define FLASH_28F128K3 0x00B6 /* Intel 28F128K3 ( 128M = 8M x 16 ) */
438#define FLASH_28F256K3 0x00B8 /* Intel 28F256K3 ( 256M = 16M x 16 ) */
wdenked247f42002-10-07 21:58:02 +0000439
wdenkb54d32b2004-06-10 21:34:36 +0000440#define FLASH_28F320J3A 0x00C0 /* INTEL 28F320J3A ( 32M = 128K x 32) */
441#define FLASH_28F640J3A 0x00C2 /* INTEL 28F640J3A ( 64M = 128K x 64) */
442#define FLASH_28F128J3A 0x00C4 /* INTEL 28F128J3A (128M = 128K x 128) */
Wolfgang Denk97c8d0b2005-12-22 01:50:50 +0100443#define FLASH_28F256J3A 0x00C6 /* INTEL 28F256J3A (256M = 128K x 256) */
wdenkbf9e3b32004-02-12 00:47:09 +0000444
wdenkb54d32b2004-06-10 21:34:36 +0000445#define FLASH_FUJLV650 0x00D0 /* Fujitsu MBM 29LV650UE/651UE */
Wolfgang Denk8e6f1a82005-09-25 18:59:36 +0200446#define FLASH_MT28S4M16LC 0x00E1 /* Micron MT28S4M16LC */
wdenk9d5028c2004-11-21 00:06:33 +0000447#define FLASH_S29GL064M 0x00F0 /* Spansion S29GL064M-R6 */
Marian Balakowicz72997122006-10-03 20:28:38 +0200448#define FLASH_S29GL128N 0x00F1 /* Spansion S29GL128N */
wdenkb54d32b2004-06-10 21:34:36 +0000449
wdenked247f42002-10-07 21:58:02 +0000450#define FLASH_UNKNOWN 0xFFFF /* unknown flash type */
451
452
453/* manufacturer offsets
454 */
455#define FLASH_MAN_AMD 0x00000000 /* AMD */
456#define FLASH_MAN_FUJ 0x00010000 /* Fujitsu */
457#define FLASH_MAN_BM 0x00020000 /* Bright Microelectronics */
458#define FLASH_MAN_MX 0x00030000 /* MXIC */
459#define FLASH_MAN_STM 0x00040000
wdenk2abbe072003-06-16 23:50:08 +0000460#define FLASH_MAN_TOSH 0x00050000 /* Toshiba */
Wolfgang Denk8e6f1a82005-09-25 18:59:36 +0200461#define FLASH_MAN_EXCEL 0x00060000 /* Excel Semiconductor */
wdenked247f42002-10-07 21:58:02 +0000462#define FLASH_MAN_SST 0x00100000
wdenk2abbe072003-06-16 23:50:08 +0000463#define FLASH_MAN_INTEL 0x00300000
wdenked247f42002-10-07 21:58:02 +0000464#define FLASH_MAN_MT 0x00400000
wdenk2abbe072003-06-16 23:50:08 +0000465#define FLASH_MAN_SHARP 0x00500000
Wolfgang Denk8e6f1a82005-09-25 18:59:36 +0200466#define FLASH_MAN_ATM 0x00600000
Stefan Roese260421a2006-11-13 13:55:24 +0100467#define FLASH_MAN_CFI 0x01000000
wdenked247f42002-10-07 21:58:02 +0000468
469
wdenk2abbe072003-06-16 23:50:08 +0000470#define FLASH_TYPEMASK 0x0000FFFF /* extract FLASH type information */
wdenked247f42002-10-07 21:58:02 +0000471#define FLASH_VENDMASK 0xFFFF0000 /* extract FLASH vendor information */
472
473#define FLASH_AMD_COMP 0x000FFFFF /* Up to this ID, FLASH is compatible */
474 /* with AMD, Fujitsu and SST */
475 /* (JEDEC standard commands ?) */
476
477#define FLASH_BTYPE 0x0001 /* mask for bottom boot sector type */
478
479/*-----------------------------------------------------------------------
480 * Timeout constants:
481 *
482 * We can't find any specifications for maximum chip erase times,
483 * so these values are guestimates.
484 */
485#define FLASH_ERASE_TIMEOUT 120000 /* timeout for erasing in ms */
486#define FLASH_WRITE_TIMEOUT 500 /* timeout for writes in ms */
487
488#endif /* !CFG_NO_FLASH */
489
490#endif /* _FLASH_H_ */