blob: 928d58b3a732894bcf7fe143da3ef821d6caf0bb [file] [log] [blame]
Stefan Agner72d7bea2014-09-12 13:06:35 +02001/*
2 * Copyright 2009-2014 Freescale Semiconductor, Inc. and others
3 *
4 * Description: MPC5125, VF610, MCF54418 and Kinetis K70 Nand driver.
5 * Ported to U-Boot by Stefan Agner
6 * Based on RFC driver posted on Kernel Mailing list by Bill Pringlemeir
7 * Jason ported to M54418TWR and MVFA5.
8 * Authors: Stefan Agner <stefan.agner@toradex.com>
9 * Bill Pringlemeir <bpringlemeir@nbsps.com>
10 * Shaohui Xie <b21989@freescale.com>
11 * Jason Jin <Jason.jin@freescale.com>
12 *
13 * Based on original driver mpc5121_nfc.c.
14 *
15 * This is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * Limitations:
21 * - Untested on MPC5125 and M54418.
22 * - DMA not used.
23 * - 2K pages or less.
24 * - Only 2K page w. 64+OOB and hardware ECC.
25 */
26
27#include <common.h>
28#include <malloc.h>
29
30#include <linux/mtd/mtd.h>
31#include <linux/mtd/nand.h>
32#include <linux/mtd/partitions.h>
33
34#include <nand.h>
35#include <errno.h>
36#include <asm/io.h>
37
38/* Register Offsets */
39#define NFC_FLASH_CMD1 0x3F00
40#define NFC_FLASH_CMD2 0x3F04
41#define NFC_COL_ADDR 0x3F08
42#define NFC_ROW_ADDR 0x3F0c
43#define NFC_ROW_ADDR_INC 0x3F14
44#define NFC_FLASH_STATUS1 0x3F18
45#define NFC_FLASH_STATUS2 0x3F1c
46#define NFC_CACHE_SWAP 0x3F28
47#define NFC_SECTOR_SIZE 0x3F2c
48#define NFC_FLASH_CONFIG 0x3F30
49#define NFC_IRQ_STATUS 0x3F38
50
51/* Addresses for NFC MAIN RAM BUFFER areas */
52#define NFC_MAIN_AREA(n) ((n) * 0x1000)
53
54#define PAGE_2K 0x0800
55#define OOB_64 0x0040
56
57/*
58 * NFC_CMD2[CODE] values. See section:
59 * - 31.4.7 Flash Command Code Description, Vybrid manual
60 * - 23.8.6 Flash Command Sequencer, MPC5125 manual
61 *
62 * Briefly these are bitmasks of controller cycles.
63 */
64#define READ_PAGE_CMD_CODE 0x7EE0
65#define PROGRAM_PAGE_CMD_CODE 0x7FC0
66#define ERASE_CMD_CODE 0x4EC0
67#define READ_ID_CMD_CODE 0x4804
68#define RESET_CMD_CODE 0x4040
69#define STATUS_READ_CMD_CODE 0x4068
70
71/* NFC ECC mode define */
72#define ECC_BYPASS 0
73#define ECC_45_BYTE 6
74
75/*** Register Mask and bit definitions */
76
77/* NFC_FLASH_CMD1 Field */
78#define CMD_BYTE2_MASK 0xFF000000
79#define CMD_BYTE2_SHIFT 24
80
81/* NFC_FLASH_CM2 Field */
82#define CMD_BYTE1_MASK 0xFF000000
83#define CMD_BYTE1_SHIFT 24
84#define CMD_CODE_MASK 0x00FFFF00
85#define CMD_CODE_SHIFT 8
86#define BUFNO_MASK 0x00000006
87#define BUFNO_SHIFT 1
88#define START_BIT (1<<0)
89
90/* NFC_COL_ADDR Field */
91#define COL_ADDR_MASK 0x0000FFFF
92#define COL_ADDR_SHIFT 0
93
94/* NFC_ROW_ADDR Field */
95#define ROW_ADDR_MASK 0x00FFFFFF
96#define ROW_ADDR_SHIFT 0
97#define ROW_ADDR_CHIP_SEL_RB_MASK 0xF0000000
98#define ROW_ADDR_CHIP_SEL_RB_SHIFT 28
99#define ROW_ADDR_CHIP_SEL_MASK 0x0F000000
100#define ROW_ADDR_CHIP_SEL_SHIFT 24
101
102/* NFC_FLASH_STATUS2 Field */
103#define STATUS_BYTE1_MASK 0x000000FF
104
105/* NFC_FLASH_CONFIG Field */
106#define CONFIG_ECC_SRAM_ADDR_MASK 0x7FC00000
107#define CONFIG_ECC_SRAM_ADDR_SHIFT 22
108#define CONFIG_ECC_SRAM_REQ_BIT (1<<21)
109#define CONFIG_DMA_REQ_BIT (1<<20)
110#define CONFIG_ECC_MODE_MASK 0x000E0000
111#define CONFIG_ECC_MODE_SHIFT 17
112#define CONFIG_FAST_FLASH_BIT (1<<16)
113#define CONFIG_16BIT (1<<7)
114#define CONFIG_BOOT_MODE_BIT (1<<6)
115#define CONFIG_ADDR_AUTO_INCR_BIT (1<<5)
116#define CONFIG_BUFNO_AUTO_INCR_BIT (1<<4)
117#define CONFIG_PAGE_CNT_MASK 0xF
118#define CONFIG_PAGE_CNT_SHIFT 0
119
120/* NFC_IRQ_STATUS Field */
121#define IDLE_IRQ_BIT (1<<29)
122#define IDLE_EN_BIT (1<<20)
123#define CMD_DONE_CLEAR_BIT (1<<18)
124#define IDLE_CLEAR_BIT (1<<17)
125
126#define NFC_TIMEOUT (1000)
127
128/* ECC status placed at end of buffers. */
129#define ECC_SRAM_ADDR ((PAGE_2K+256-8) >> 3)
130#define ECC_STATUS_MASK 0x80
131#define ECC_ERR_COUNT 0x3F
132
133/*
134 * ECC status is stored at NFC_CFG[ECCADD] +4 for little-endian
135 * and +7 for big-endian SOC.
136 */
137#ifdef CONFIG_VF610
138#define ECC_OFFSET 4
139#else
140#define ECC_OFFSET 7
141#endif
142
143struct vf610_nfc {
144 struct mtd_info *mtd;
145 struct nand_chip chip;
146 void __iomem *regs;
147 uint column;
148 int spareonly;
149 int page;
150 /* Status and ID are in alternate locations. */
151 int alt_buf;
152#define ALT_BUF_ID 1
153#define ALT_BUF_STAT 2
154 struct clk *clk;
155};
156
157#define mtd_to_nfc(_mtd) \
158 (struct vf610_nfc *)((struct nand_chip *)_mtd->priv)->priv
159
160static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
161static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
162
163static struct nand_bbt_descr bbt_main_descr = {
164 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
165 NAND_BBT_2BIT | NAND_BBT_VERSION,
166 .offs = 11,
167 .len = 4,
168 .veroffs = 15,
169 .maxblocks = 4,
170 .pattern = bbt_pattern,
171};
172
173static struct nand_bbt_descr bbt_mirror_descr = {
174 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
175 NAND_BBT_2BIT | NAND_BBT_VERSION,
176 .offs = 11,
177 .len = 4,
178 .veroffs = 15,
179 .maxblocks = 4,
180 .pattern = mirror_pattern,
181};
182
183static struct nand_ecclayout vf610_nfc_ecc45 = {
184 .eccbytes = 45,
185 .eccpos = {19, 20, 21, 22, 23,
186 24, 25, 26, 27, 28, 29, 30, 31,
187 32, 33, 34, 35, 36, 37, 38, 39,
188 40, 41, 42, 43, 44, 45, 46, 47,
189 48, 49, 50, 51, 52, 53, 54, 55,
190 56, 57, 58, 59, 60, 61, 62, 63},
191 .oobfree = {
192 {.offset = 8,
193 .length = 11} }
194};
195
196static inline u32 vf610_nfc_read(struct mtd_info *mtd, uint reg)
197{
198 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
199
200 return readl(nfc->regs + reg);
201}
202
203static inline void vf610_nfc_write(struct mtd_info *mtd, uint reg, u32 val)
204{
205 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
206
207 writel(val, nfc->regs + reg);
208}
209
210static inline void vf610_nfc_set(struct mtd_info *mtd, uint reg, u32 bits)
211{
212 vf610_nfc_write(mtd, reg, vf610_nfc_read(mtd, reg) | bits);
213}
214
215static inline void vf610_nfc_clear(struct mtd_info *mtd, uint reg, u32 bits)
216{
217 vf610_nfc_write(mtd, reg, vf610_nfc_read(mtd, reg) & ~bits);
218}
219
220static inline void vf610_nfc_set_field(struct mtd_info *mtd, u32 reg,
221 u32 mask, u32 shift, u32 val)
222{
223 vf610_nfc_write(mtd, reg,
224 (vf610_nfc_read(mtd, reg) & (~mask)) | val << shift);
225}
226
227static inline void vf610_nfc_memcpy(void *dst, const void *src, size_t n)
228{
229 /*
230 * Use this accessor for the interal SRAM buffers. On ARM we can
231 * treat the SRAM buffer as if its memory, hence use memcpy
232 */
233 memcpy(dst, src, n);
234}
235
236/* Clear flags for upcoming command */
237static inline void vf610_nfc_clear_status(void __iomem *regbase)
238{
239 void __iomem *reg = regbase + NFC_IRQ_STATUS;
240 u32 tmp = __raw_readl(reg);
241 tmp |= CMD_DONE_CLEAR_BIT | IDLE_CLEAR_BIT;
242 __raw_writel(tmp, reg);
243}
244
245/* Wait for complete operation */
246static inline void vf610_nfc_done(struct mtd_info *mtd)
247{
248 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
249 uint start;
250
251 /*
252 * Barrier is needed after this write. This write need
253 * to be done before reading the next register the first
254 * time.
255 * vf610_nfc_set implicates such a barrier by using writel
256 * to write to the register.
257 */
258 vf610_nfc_set(mtd, NFC_FLASH_CMD2, START_BIT);
259
260 start = get_timer(0);
261
262 while (!(vf610_nfc_read(mtd, NFC_IRQ_STATUS) & IDLE_IRQ_BIT)) {
263 if (get_timer(start) > NFC_TIMEOUT) {
264 printf("Timeout while waiting for !BUSY.\n");
265 return;
266 }
267 }
268 vf610_nfc_clear_status(nfc->regs);
269}
270
271static u8 vf610_nfc_get_id(struct mtd_info *mtd, int col)
272{
273 u32 flash_id;
274
275 if (col < 4) {
276 flash_id = vf610_nfc_read(mtd, NFC_FLASH_STATUS1);
277 return (flash_id >> (3-col)*8) & 0xff;
278 } else {
279 flash_id = vf610_nfc_read(mtd, NFC_FLASH_STATUS2);
280 return flash_id >> 24;
281 }
282}
283
284static u8 vf610_nfc_get_status(struct mtd_info *mtd)
285{
286 return vf610_nfc_read(mtd, NFC_FLASH_STATUS2) & STATUS_BYTE1_MASK;
287}
288
289/* Single command */
290static void vf610_nfc_send_command(void __iomem *regbase, u32 cmd_byte1,
291 u32 cmd_code)
292{
293 void __iomem *reg = regbase + NFC_FLASH_CMD2;
294 u32 tmp;
295 vf610_nfc_clear_status(regbase);
296
297 tmp = __raw_readl(reg);
298 tmp &= ~(CMD_BYTE1_MASK | CMD_CODE_MASK | BUFNO_MASK);
299 tmp |= cmd_byte1 << CMD_BYTE1_SHIFT;
300 tmp |= cmd_code << CMD_CODE_SHIFT;
301 __raw_writel(tmp, reg);
302}
303
304/* Two commands */
305static void vf610_nfc_send_commands(void __iomem *regbase, u32 cmd_byte1,
306 u32 cmd_byte2, u32 cmd_code)
307{
308 void __iomem *reg = regbase + NFC_FLASH_CMD1;
309 u32 tmp;
310 vf610_nfc_send_command(regbase, cmd_byte1, cmd_code);
311
312 tmp = __raw_readl(reg);
313 tmp &= ~CMD_BYTE2_MASK;
314 tmp |= cmd_byte2 << CMD_BYTE2_SHIFT;
315 __raw_writel(tmp, reg);
316}
317
318static void vf610_nfc_addr_cycle(struct mtd_info *mtd, int column, int page)
319{
320 if (column != -1) {
321 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
322 if (nfc->chip.options | NAND_BUSWIDTH_16)
323 column = column/2;
324 vf610_nfc_set_field(mtd, NFC_COL_ADDR, COL_ADDR_MASK,
325 COL_ADDR_SHIFT, column);
326 }
327 if (page != -1)
328 vf610_nfc_set_field(mtd, NFC_ROW_ADDR, ROW_ADDR_MASK,
329 ROW_ADDR_SHIFT, page);
330}
331
332/* Send command to NAND chip */
333static void vf610_nfc_command(struct mtd_info *mtd, unsigned command,
334 int column, int page)
335{
336 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
337
338 nfc->column = max(column, 0);
339 nfc->spareonly = 0;
340 nfc->alt_buf = 0;
341
342 switch (command) {
343 case NAND_CMD_PAGEPROG:
344 nfc->page = -1;
345 vf610_nfc_send_commands(nfc->regs, NAND_CMD_SEQIN,
346 command, PROGRAM_PAGE_CMD_CODE);
347 vf610_nfc_addr_cycle(mtd, column, page);
348 break;
349
350 case NAND_CMD_RESET:
351 vf610_nfc_send_command(nfc->regs, command, RESET_CMD_CODE);
352 break;
353 /*
354 * NFC does not support sub-page reads and writes,
355 * so emulate them using full page transfers.
356 */
357 case NAND_CMD_READOOB:
358 nfc->spareonly = 1;
359 case NAND_CMD_SEQIN: /* Pre-read for partial writes. */
360 case NAND_CMD_READ0:
361 column = 0;
362 /* Already read? */
363 if (nfc->page == page)
364 return;
365 nfc->page = page;
366 vf610_nfc_send_commands(nfc->regs, NAND_CMD_READ0,
367 NAND_CMD_READSTART, READ_PAGE_CMD_CODE);
368 vf610_nfc_addr_cycle(mtd, column, page);
369 break;
370
371 case NAND_CMD_ERASE1:
372 if (nfc->page == page)
373 nfc->page = -1;
374 vf610_nfc_send_commands(nfc->regs, command,
375 NAND_CMD_ERASE2, ERASE_CMD_CODE);
376 vf610_nfc_addr_cycle(mtd, column, page);
377 break;
378
379 case NAND_CMD_READID:
380 nfc->alt_buf = ALT_BUF_ID;
381 vf610_nfc_send_command(nfc->regs, command, READ_ID_CMD_CODE);
382 break;
383
384 case NAND_CMD_STATUS:
385 nfc->alt_buf = ALT_BUF_STAT;
386 vf610_nfc_send_command(nfc->regs, command,
387 STATUS_READ_CMD_CODE);
388 break;
389 default:
390 return;
391 }
392
393 vf610_nfc_done(mtd);
394}
395
396static inline void vf610_nfc_read_spare(struct mtd_info *mtd, void *buf,
397 int len)
398{
399 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
400
401 len = min(mtd->oobsize, (uint)len);
402 if (len > 0)
403 vf610_nfc_memcpy(buf, nfc->regs + mtd->writesize, len);
404}
405
406/* Read data from NFC buffers */
407static void vf610_nfc_read_buf(struct mtd_info *mtd, u_char *buf, int len)
408{
409 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
410 uint c = nfc->column;
411 uint l;
412
413 /* Handle main area */
414 if (!nfc->spareonly) {
415 l = min((uint)len, mtd->writesize - c);
416 nfc->column += l;
417
418 if (!nfc->alt_buf)
419 vf610_nfc_memcpy(buf, nfc->regs + NFC_MAIN_AREA(0) + c,
420 l);
421 else
422 if (nfc->alt_buf & ALT_BUF_ID)
423 *buf = vf610_nfc_get_id(mtd, c);
424 else
425 *buf = vf610_nfc_get_status(mtd);
426
427 buf += l;
428 len -= l;
429 }
430
431 /* Handle spare area access */
432 if (len) {
433 nfc->column += len;
434 vf610_nfc_read_spare(mtd, buf, len);
435 }
436}
437
438/* Write data to NFC buffers */
439static void vf610_nfc_write_buf(struct mtd_info *mtd, const u_char *buf,
440 int len)
441{
442 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
443 uint c = nfc->column;
444 uint l;
445
446 l = min((uint)len, mtd->writesize + mtd->oobsize - c);
447 nfc->column += l;
448 vf610_nfc_memcpy(nfc->regs + NFC_MAIN_AREA(0) + c, buf, l);
449}
450
451/* Read byte from NFC buffers */
452static u8 vf610_nfc_read_byte(struct mtd_info *mtd)
453{
454 u8 tmp;
455 vf610_nfc_read_buf(mtd, &tmp, sizeof(tmp));
456 return tmp;
457}
458
459/* Read word from NFC buffers */
460static u16 vf610_nfc_read_word(struct mtd_info *mtd)
461{
462 u16 tmp;
463 vf610_nfc_read_buf(mtd, (u_char *)&tmp, sizeof(tmp));
464 return tmp;
465}
466
467/* If not provided, upper layers apply a fixed delay. */
468static int vf610_nfc_dev_ready(struct mtd_info *mtd)
469{
470 /* NFC handles R/B internally; always ready. */
471 return 1;
472}
473
474/*
475 * This function supports Vybrid only (MPC5125 would have full RB and four CS)
476 */
477static void vf610_nfc_select_chip(struct mtd_info *mtd, int chip)
478{
479#ifdef CONFIG_VF610
480 u32 tmp = vf610_nfc_read(mtd, NFC_ROW_ADDR);
481 tmp &= ~(ROW_ADDR_CHIP_SEL_RB_MASK | ROW_ADDR_CHIP_SEL_MASK);
482 tmp |= 1 << ROW_ADDR_CHIP_SEL_RB_SHIFT;
483
484 if (chip == 0)
485 tmp |= 1 << ROW_ADDR_CHIP_SEL_SHIFT;
486 else if (chip == 1)
487 tmp |= 2 << ROW_ADDR_CHIP_SEL_SHIFT;
488
489 vf610_nfc_write(mtd, NFC_ROW_ADDR, tmp);
490#endif
491}
492
493/* Count the number of 0's in buff upto max_bits */
494static inline int count_written_bits(uint8_t *buff, int size, int max_bits)
495{
496 uint32_t *buff32 = (uint32_t *)buff;
497 int k, written_bits = 0;
498
499 for (k = 0; k < (size / 4); k++) {
500 written_bits += hweight32(~buff32[k]);
501 if (written_bits > max_bits)
502 break;
503 }
504
505 return written_bits;
506}
507
508static inline int vf610_nfc_correct_data(struct mtd_info *mtd, u_char *dat)
509{
510 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
511 u8 ecc_status;
512 u8 ecc_count;
513 int flip;
514
515 ecc_status = __raw_readb(nfc->regs + ECC_SRAM_ADDR * 8 + ECC_OFFSET);
516 ecc_count = ecc_status & ECC_ERR_COUNT;
517 if (!(ecc_status & ECC_STATUS_MASK))
518 return ecc_count;
519
520 /* If 'ecc_count' zero or less then buffer is all 0xff or erased. */
521 flip = count_written_bits(dat, nfc->chip.ecc.size, ecc_count);
522
523 /* ECC failed. */
524 if (flip > ecc_count) {
525 nfc->page = -1;
526 return -1;
527 }
528
529 /* Erased page. */
530 memset(dat, 0xff, nfc->chip.ecc.size);
531 return 0;
532}
533
534
535static int vf610_nfc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
536 uint8_t *buf, int oob_required, int page)
537{
538 int eccsize = chip->ecc.size;
539 int stat;
540 uint8_t *p = buf;
541
542
543 vf610_nfc_read_buf(mtd, p, eccsize);
544
545 if (oob_required)
546 vf610_nfc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
547
548 stat = vf610_nfc_correct_data(mtd, p);
549
550 if (stat < 0)
551 mtd->ecc_stats.failed++;
552 else
553 mtd->ecc_stats.corrected += stat;
554
555 return 0;
556}
557
558/*
559 * ECC will be calculated automatically
560 */
561static int vf610_nfc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
562 const uint8_t *buf, int oob_required)
563{
564 vf610_nfc_write_buf(mtd, buf, mtd->writesize);
565 if (oob_required)
566 vf610_nfc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
567
568 return 0;
569}
570
571struct vf610_nfc_config {
572 int hardware_ecc;
573 int width;
574 int flash_bbt;
575};
576
577static int vf610_nfc_nand_init(int devnum, void __iomem *addr)
578{
579 struct mtd_info *mtd = &nand_info[devnum];
580 struct nand_chip *chip;
581 struct vf610_nfc *nfc;
582 int err = 0;
583 int page_sz;
584 struct vf610_nfc_config cfg = {
585 .hardware_ecc = 1,
586#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
587 .width = 16,
588#else
589 .width = 8,
590#endif
591 .flash_bbt = 1,
592 };
593
594 nfc = malloc(sizeof(*nfc));
595 if (!nfc) {
596 printf(KERN_ERR "%s: Memory exhausted!\n", __func__);
597 return -ENOMEM;
598 }
599
600 chip = &nfc->chip;
601 nfc->regs = addr;
602
603 mtd->priv = chip;
604 chip->priv = nfc;
605
606 if (cfg.width == 16) {
607 chip->options |= NAND_BUSWIDTH_16;
608 vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_16BIT);
609 } else {
610 chip->options &= ~NAND_BUSWIDTH_16;
611 vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_16BIT);
612 }
613
Sanchayan Maity22604572014-11-24 11:03:59 +0530614 /* Disable subpage writes as we do not provide ecc->hwctl */
615 chip->options |= NAND_NO_SUBPAGE_WRITE;
616
Stefan Agner72d7bea2014-09-12 13:06:35 +0200617 chip->dev_ready = vf610_nfc_dev_ready;
618 chip->cmdfunc = vf610_nfc_command;
619 chip->read_byte = vf610_nfc_read_byte;
620 chip->read_word = vf610_nfc_read_word;
621 chip->read_buf = vf610_nfc_read_buf;
622 chip->write_buf = vf610_nfc_write_buf;
623 chip->select_chip = vf610_nfc_select_chip;
624
625 /* Bad block options. */
626 if (cfg.flash_bbt)
627 chip->bbt_options = NAND_BBT_USE_FLASH | NAND_BBT_CREATE;
628
629 /* Default to software ECC until flash ID. */
630 vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG,
631 CONFIG_ECC_MODE_MASK,
632 CONFIG_ECC_MODE_SHIFT, ECC_BYPASS);
633
634 chip->bbt_td = &bbt_main_descr;
635 chip->bbt_md = &bbt_mirror_descr;
636
637 page_sz = PAGE_2K + OOB_64;
638 page_sz += cfg.width == 16 ? 1 : 0;
639 vf610_nfc_write(mtd, NFC_SECTOR_SIZE, page_sz);
640
641 /* Set configuration register. */
642 vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_ADDR_AUTO_INCR_BIT);
643 vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_BUFNO_AUTO_INCR_BIT);
644 vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_BOOT_MODE_BIT);
645 vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_DMA_REQ_BIT);
646 vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_FAST_FLASH_BIT);
647
648 /* Enable Idle IRQ */
649 vf610_nfc_set(mtd, NFC_IRQ_STATUS, IDLE_EN_BIT);
650
651 /* PAGE_CNT = 1 */
652 vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG, CONFIG_PAGE_CNT_MASK,
653 CONFIG_PAGE_CNT_SHIFT, 1);
654
655 /* Set ECC_STATUS offset */
656 vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG,
657 CONFIG_ECC_SRAM_ADDR_MASK,
658 CONFIG_ECC_SRAM_ADDR_SHIFT, ECC_SRAM_ADDR);
659
660 /* first scan to find the device and get the page size */
661 if (nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_DEVICE, NULL)) {
662 err = -ENXIO;
663 goto error;
664 }
665
666 chip->ecc.mode = NAND_ECC_SOFT; /* default */
667
668 page_sz = mtd->writesize + mtd->oobsize;
669
670 /* Single buffer only, max 256 OOB minus ECC status */
671 if (page_sz > PAGE_2K + 256 - 8) {
672 dev_err(nfc->dev, "Unsupported flash size\n");
673 err = -ENXIO;
674 goto error;
675 }
676 page_sz += cfg.width == 16 ? 1 : 0;
677 vf610_nfc_write(mtd, NFC_SECTOR_SIZE, page_sz);
678
679 if (cfg.hardware_ecc) {
680 if (mtd->writesize != PAGE_2K && mtd->oobsize < 64) {
681 dev_err(nfc->dev, "Unsupported flash with hwecc\n");
682 err = -ENXIO;
683 goto error;
684 }
685
686 chip->ecc.layout = &vf610_nfc_ecc45;
687
688 /* propagate ecc.layout to mtd_info */
689 mtd->ecclayout = chip->ecc.layout;
690 chip->ecc.read_page = vf610_nfc_read_page;
691 chip->ecc.write_page = vf610_nfc_write_page;
692 chip->ecc.mode = NAND_ECC_HW;
693
694 chip->ecc.bytes = 45;
695 chip->ecc.size = PAGE_2K;
696 chip->ecc.strength = 24;
697
698 /* set ECC mode to 45 bytes OOB with 24 bits correction */
699 vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG,
700 CONFIG_ECC_MODE_MASK,
701 CONFIG_ECC_MODE_SHIFT, ECC_45_BYTE);
702
703 /* Enable ECC_STATUS */
704 vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_ECC_SRAM_REQ_BIT);
705 }
706
707 /* second phase scan */
708 err = nand_scan_tail(mtd);
709 if (err)
710 return err;
711
712 err = nand_register(devnum);
713 if (err)
714 return err;
715
716 return 0;
717
718error:
719 return err;
720}
721
722void board_nand_init(void)
723{
724 int err = vf610_nfc_nand_init(0, (void __iomem *)CONFIG_SYS_NAND_BASE);
725 if (err)
726 printf("VF610 NAND init failed (err %d)\n", err);
727}