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Yusuke Godac133c1f2008-03-11 12:55:12 +09001/*
2 * Configuation settings for the Renesas R7780MP board
3 *
Nobuhiro Iwamatsuec39d472008-06-17 16:28:01 +09004 * Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Yusuke Godac133c1f2008-03-11 12:55:12 +09005 * Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#ifndef __R7780RP_H
27#define __R7780RP_H
28
29#undef DEBUG
30#define CONFIG_SH 1
31#define CONFIG_SH4A 1
32#define CONFIG_CPU_SH7780 1
33#define CONFIG_R7780MP 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020034#define CONFIG_SYS_R7780MP_OLD_FLASH 1
Nobuhiro Iwamatsuec39d472008-06-17 16:28:01 +090035#define __LITTLE_ENDIAN__ 1
Yusuke Godac133c1f2008-03-11 12:55:12 +090036
37/*
38 * Command line configuration.
39 */
40#define CONFIG_CMD_SDRAM
41#define CONFIG_CMD_FLASH
42#define CONFIG_CMD_MEMORY
43#define CONFIG_CMD_PCI
44#define CONFIG_CMD_NET
45#define CONFIG_CMD_PING
46#define CONFIG_CMD_ENV
47#define CONFIG_CMD_NFS
48#define CONFIG_CMD_IDE
49#define CONFIG_CMD_EXT2
50#define CONFIG_DOS_PARTITION
51
Jean-Christophe PLAGNIOL-VILLARD6c58a032008-08-13 01:40:38 +020052#define CONFIG_SCIF_CONSOLE 1
Yusuke Godac133c1f2008-03-11 12:55:12 +090053#define CONFIG_BAUDRATE 115200
54#define CONFIG_CONS_SCIF0 1
55
56#define CONFIG_BOOTDELAY 3
57#define CONFIG_BOOTARGS "console=ttySC0,115200"
58#define CONFIG_ENV_OVERWRITE 1
59
60/* check for keypress on bootdelay==0 */
61/*#define CONFIG_ZERO_BOOTDELAY_CHECK*/
62
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020063#define CONFIG_SYS_SDRAM_BASE (0x08000000)
64#define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024)
Yusuke Godac133c1f2008-03-11 12:55:12 +090065
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020066#define CONFIG_SYS_LONGHELP
67#define CONFIG_SYS_PROMPT "=> "
68#define CONFIG_SYS_CBSIZE 256
69#define CONFIG_SYS_PBSIZE 256
70#define CONFIG_SYS_MAXARGS 16
71#define CONFIG_SYS_BARGSIZE 512
Yusuke Godac133c1f2008-03-11 12:55:12 +090072/* List of legal baudrate settings for this board */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020073#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 }
Yusuke Godac133c1f2008-03-11 12:55:12 +090074
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020075#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
76#define CONFIG_SYS_MEMTEST_END (TEXT_BASE - 0x100000)
Yusuke Godac133c1f2008-03-11 12:55:12 +090077
Nobuhiro Iwamatsuec39d472008-06-17 16:28:01 +090078/* Flash board support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020079#define CONFIG_SYS_FLASH_BASE (0xA0000000)
80#ifdef CONFIG_SYS_R7780MP_OLD_FLASH
Nobuhiro Iwamatsuec39d472008-06-17 16:28:01 +090081/* NOR Flash (S29PL127J60TFI130) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020082# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
83# define CONFIG_SYS_MAX_FLASH_BANKS (2)
84# define CONFIG_SYS_MAX_FLASH_SECT 270
85# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
86 CONFIG_SYS_FLASH_BASE + 0x100000,\
87 CONFIG_SYS_FLASH_BASE + 0x400000,\
88 CONFIG_SYS_FLASH_BASE + 0x700000, }
89#else /* CONFIG_SYS_R7780MP_OLD_FLASH */
Nobuhiro Iwamatsuec39d472008-06-17 16:28:01 +090090/* NOR Flash (Spantion S29GL256P) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020091# define CONFIG_SYS_MAX_FLASH_BANKS (1)
92# define CONFIG_SYS_MAX_FLASH_SECT 256
93# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
94#endif /* CONFIG_SYS_R7780MP_OLD_FLASH */
Yusuke Godac133c1f2008-03-11 12:55:12 +090095
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020096#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
Yusuke Godac133c1f2008-03-11 12:55:12 +090097/* Address of u-boot image in Flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020098#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE)
99#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
Yusuke Godac133c1f2008-03-11 12:55:12 +0900100/* Size of DRAM reserved for malloc() use */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101#define CONFIG_SYS_MALLOC_LEN (1204 * 1024)
Yusuke Godac133c1f2008-03-11 12:55:12 +0900102
103/* size in bytes reserved for initial data */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104#define CONFIG_SYS_GBL_DATA_SIZE (256)
105#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
106#define CONFIG_SYS_RX_ETH_BUFFER (8)
Yusuke Godac133c1f2008-03-11 12:55:12 +0900107
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200108#define CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200109#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#undef CONFIG_SYS_FLASH_CFI_BROKEN_TABLE
111#undef CONFIG_SYS_FLASH_QUIET_TEST
Yusuke Godac133c1f2008-03-11 12:55:12 +0900112/* print 'E' for empty sector on flinfo */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113#define CONFIG_SYS_FLASH_EMPTY_INFO
Yusuke Godac133c1f2008-03-11 12:55:12 +0900114
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200115#define CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200116#define CONFIG_ENV_SECT_SIZE (256 * 1024)
117#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
119#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
120#define CONFIG_SYS_FLASH_WRITE_TOUT 500
Yusuke Godac133c1f2008-03-11 12:55:12 +0900121
122/* Board Clock */
123#define CONFIG_SYS_CLK_FREQ 33333333
124#define TMU_CLK_DIVIDER 4
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
Yusuke Godac133c1f2008-03-11 12:55:12 +0900126
127/* PCI Controller */
128#if defined(CONFIG_CMD_PCI)
129#define CONFIG_PCI
130#define CONFIG_SH4_PCI
Nobuhiro Iwamatsuab8f4d42008-03-24 02:11:26 +0900131#define CONFIG_SH7780_PCI
Yusuke Godac133c1f2008-03-11 12:55:12 +0900132#define CONFIG_PCI_PNP
133#define CONFIG_PCI_SCAN_SHOW 1
134#define __io
135#define __mem_pci
136
137#define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */
138#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
139#define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
140
141#define CONFIG_PCI_IO_BUS 0xFE200000 /* IO space base address */
142#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
143#define CONFIG_PCI_IO_SIZE 0x00200000 /* Size of IO window */
144#endif /* CONFIG_CMD_PCI */
145
146#if defined(CONFIG_CMD_NET)
Nobuhiro Iwamatsuec39d472008-06-17 16:28:01 +0900147/*
148#define CONFIG_NET_MULTI
149#define CONFIG_RTL8169
150*/
Yusuke Godac133c1f2008-03-11 12:55:12 +0900151/* AX88696L Support(NE2000 base chip) */
152#define CONFIG_DRIVER_NE2000
153#define CONFIG_DRIVER_AX88796L
154#define CONFIG_DRIVER_NE2000_BASE 0xA4100000
155#endif
156
157/* Compact flash Support */
158#if defined(CONFIG_CMD_IDE)
159#define CONFIG_IDE_RESET 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200160#define CONFIG_SYS_PIO_MODE 1
161#define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */
162#define CONFIG_SYS_IDE_MAXDEVICE 1
163#define CONFIG_SYS_ATA_BASE_ADDR 0xb4000000
164#define CONFIG_SYS_ATA_STRIDE 2 /* 1bit shift */
165#define CONFIG_SYS_ATA_DATA_OFFSET 0x1000 /* data reg offset */
166#define CONFIG_SYS_ATA_REG_OFFSET 0x1000 /* reg offset */
167#define CONFIG_SYS_ATA_ALT_OFFSET 0x800 /* alternate register offset */
Yusuke Godac133c1f2008-03-11 12:55:12 +0900168#endif /* CONFIG_CMD_IDE */
169
170#endif /* __R7780RP_H */