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Vipin KUMAR62db1c02010-01-15 19:15:47 +05301/*
2 * (C) Copyright 2009
3 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
Vipin KUMAR27215512012-03-06 23:39:37 +000024#ifndef __DW_UDC_H
25#define __DW_UDC_H
Vipin KUMAR62db1c02010-01-15 19:15:47 +053026
27/*
28 * Defines for USBD
29 *
30 * The udc_ahb controller has three AHB slaves:
31 *
32 * 1. THe UDC registers
33 * 2. The plug detect
34 * 3. The RX/TX FIFO
35 */
36
37#define MAX_ENDPOINTS 16
38
39struct udc_endp_regs {
40 u32 endp_cntl;
41 u32 endp_status;
42 u32 endp_bsorfn;
43 u32 endp_maxpacksize;
44 u32 reserved_1;
45 u32 endp_desc_point;
46 u32 reserved_2;
47 u32 write_done;
48};
49
50/* Endpoint Control Register definitions */
51
52#define ENDP_CNTL_STALL 0x00000001
53#define ENDP_CNTL_FLUSH 0x00000002
54#define ENDP_CNTL_SNOOP 0x00000004
55#define ENDP_CNTL_POLL 0x00000008
56#define ENDP_CNTL_CONTROL 0x00000000
57#define ENDP_CNTL_ISO 0x00000010
58#define ENDP_CNTL_BULK 0x00000020
59#define ENDP_CNTL_INT 0x00000030
60#define ENDP_CNTL_NAK 0x00000040
61#define ENDP_CNTL_SNAK 0x00000080
62#define ENDP_CNTL_CNAK 0x00000100
63#define ENDP_CNTL_RRDY 0x00000200
64
65/* Endpoint Satus Register definitions */
66
67#define ENDP_STATUS_PIDMSK 0x0000000f
68#define ENDP_STATUS_OUTMSK 0x00000030
69#define ENDP_STATUS_OUT_NONE 0x00000000
70#define ENDP_STATUS_OUT_DATA 0x00000010
71#define ENDP_STATUS_OUT_SETUP 0x00000020
72#define ENDP_STATUS_IN 0x00000040
73#define ENDP_STATUS_BUFFNAV 0x00000080
74#define ENDP_STATUS_FATERR 0x00000100
75#define ENDP_STATUS_HOSTBUSERR 0x00000200
76#define ENDP_STATUS_TDC 0x00000400
77#define ENDP_STATUS_RXPKTMSK 0x003ff800
78
79struct udc_regs {
80 struct udc_endp_regs in_regs[MAX_ENDPOINTS];
81 struct udc_endp_regs out_regs[MAX_ENDPOINTS];
82 u32 dev_conf;
83 u32 dev_cntl;
84 u32 dev_stat;
85 u32 dev_int;
86 u32 dev_int_mask;
87 u32 endp_int;
88 u32 endp_int_mask;
89 u32 reserved_3[0x39];
90 u32 reserved_4; /* offset 0x500 */
91 u32 udc_endp_reg[MAX_ENDPOINTS];
92};
93
94/* Device Configuration Register definitions */
95
96#define DEV_CONF_HS_SPEED 0x00000000
97#define DEV_CONF_LS_SPEED 0x00000002
98#define DEV_CONF_FS_SPEED 0x00000003
99#define DEV_CONF_REMWAKEUP 0x00000004
100#define DEV_CONF_SELFPOW 0x00000008
101#define DEV_CONF_SYNCFRAME 0x00000010
102#define DEV_CONF_PHYINT_8 0x00000020
103#define DEV_CONF_PHYINT_16 0x00000000
104#define DEV_CONF_UTMI_BIDIR 0x00000040
105#define DEV_CONF_STATUS_STALL 0x00000080
106
107/* Device Control Register definitions */
108
109#define DEV_CNTL_RESUME 0x00000001
110#define DEV_CNTL_TFFLUSH 0x00000002
111#define DEV_CNTL_RXDMAEN 0x00000004
112#define DEV_CNTL_TXDMAEN 0x00000008
113#define DEV_CNTL_DESCRUPD 0x00000010
114#define DEV_CNTL_BIGEND 0x00000020
115#define DEV_CNTL_BUFFILL 0x00000040
116#define DEV_CNTL_TSHLDEN 0x00000080
117#define DEV_CNTL_BURSTEN 0x00000100
118#define DEV_CNTL_DMAMODE 0x00000200
119#define DEV_CNTL_SOFTDISCONNECT 0x00000400
120#define DEV_CNTL_SCALEDOWN 0x00000800
121#define DEV_CNTL_BURSTLENU 0x00010000
122#define DEV_CNTL_BURSTLENMSK 0x00ff0000
123#define DEV_CNTL_TSHLDLENU 0x01000000
124#define DEV_CNTL_TSHLDLENMSK 0xff000000
125
126/* Device Status Register definitions */
127
128#define DEV_STAT_CFG 0x0000000f
129#define DEV_STAT_INTF 0x000000f0
130#define DEV_STAT_ALT 0x00000f00
131#define DEV_STAT_SUSP 0x00001000
132#define DEV_STAT_ENUM 0x00006000
133#define DEV_STAT_ENUM_SPEED_HS 0x00000000
134#define DEV_STAT_ENUM_SPEED_FS 0x00002000
135#define DEV_STAT_ENUM_SPEED_LS 0x00004000
136#define DEV_STAT_RXFIFO_EMPTY 0x00008000
137#define DEV_STAT_PHY_ERR 0x00010000
138#define DEV_STAT_TS 0xf0000000
139
140/* Device Interrupt Register definitions */
141
142#define DEV_INT_MSK 0x0000007f
143#define DEV_INT_SETCFG 0x00000001
144#define DEV_INT_SETINTF 0x00000002
145#define DEV_INT_INACTIVE 0x00000004
146#define DEV_INT_USBRESET 0x00000008
147#define DEV_INT_SUSPUSB 0x00000010
148#define DEV_INT_SOF 0x00000020
149#define DEV_INT_ENUM 0x00000040
150
151/* Endpoint Interrupt Register definitions */
152
153#define ENDP0_INT_CTRLIN 0x00000001
154#define ENDP1_INT_BULKIN 0x00000002
155#define ENDP_INT_NONISOIN_MSK 0x0000AAAA
156#define ENDP2_INT_BULKIN 0x00000004
157#define ENDP0_INT_CTRLOUT 0x00010000
158#define ENDP1_INT_BULKOUT 0x00020000
159#define ENDP2_INT_BULKOUT 0x00040000
160#define ENDP_INT_NONISOOUT_MSK 0x55540000
161
162/* Endpoint Register definitions */
163#define ENDP_EPDIR_OUT 0x00000000
164#define ENDP_EPDIR_IN 0x00000010
165#define ENDP_EPTYPE_CNTL 0x0
166#define ENDP_EPTYPE_ISO 0x1
167#define ENDP_EPTYPE_BULK 0x2
168#define ENDP_EPTYPE_INT 0x3
169
170/*
171 * Defines for Plug Detect
172 */
173
174struct plug_regs {
175 u32 plug_state;
176 u32 plug_pending;
177};
178
179/* Plug State Register definitions */
180#define PLUG_STATUS_EN 0x1
181#define PLUG_STATUS_ATTACHED 0x2
182#define PLUG_STATUS_PHY_RESET 0x4
183#define PLUG_STATUS_PHY_MODE 0x8
184
185/*
186 * Defines for UDC FIFO (Slave Mode)
187 */
188struct udcfifo_regs {
189 u32 *fifo_p;
190};
191
192/*
193 * USBTTY definitions
194 */
195#define EP0_MAX_PACKET_SIZE 64
196#define UDC_INT_ENDPOINT 1
197#define UDC_INT_PACKET_SIZE 64
198#define UDC_OUT_ENDPOINT 2
199#define UDC_BULK_PACKET_SIZE 64
Vipin KUMAR23b0e692012-03-06 23:39:39 +0000200#define UDC_BULK_HS_PACKET_SIZE 512
Vipin KUMAR62db1c02010-01-15 19:15:47 +0530201#define UDC_IN_ENDPOINT 3
202#define UDC_OUT_PACKET_SIZE 64
203#define UDC_IN_PACKET_SIZE 64
204
205/*
206 * UDC endpoint definitions
207 */
208#define UDC_EP0 0
209#define UDC_EP1 1
210#define UDC_EP2 2
211#define UDC_EP3 3
212
213/*
214 * Function declarations
215 */
216
217void udc_irq(void);
218
219void udc_set_nak(int epid);
220void udc_unset_nak(int epid);
221int udc_endpoint_write(struct usb_endpoint_instance *endpoint);
222int udc_init(void);
223void udc_enable(struct usb_device_instance *device);
224void udc_disable(void);
225void udc_connect(void);
226void udc_disconnect(void);
227void udc_startup_events(struct usb_device_instance *device);
228void udc_setup_ep(struct usb_device_instance *device, unsigned int ep,
229 struct usb_endpoint_instance *endpoint);
230
Vipin KUMAR27215512012-03-06 23:39:37 +0000231#endif /* __DW_UDC_H */