blob: 571bc9e0ab0d49ba3ab6c1ef621adff2f038441e [file] [log] [blame]
Ian Campbell58358232014-05-05 11:52:28 +01001#include <common.h>
2#include <netdev.h>
3#include <miiphy.h>
4#include <asm/gpio.h>
5#include <asm/io.h>
6#include <asm/arch/clock.h>
7#include <asm/arch/gpio.h>
8
9int sunxi_gmac_initialize(bd_t *bis)
10{
11 int pin;
12 struct sunxi_ccm_reg *const ccm =
13 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
14
15 /* Set up clock gating */
Hans de Goedeeafec322014-11-21 17:19:45 +010016#ifndef CONFIG_MACH_SUN6I
Ian Campbell58358232014-05-05 11:52:28 +010017 setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC);
Hans de Goedeeafec322014-11-21 17:19:45 +010018#else
19 setbits_le32(&ccm->ahb_reset0_cfg, 0x1 << AHB_RESET_OFFSET_GMAC);
20 setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_GMAC);
21#endif
Ian Campbell58358232014-05-05 11:52:28 +010022
23 /* Set MII clock */
Chen-Yu Tsaief7e7232014-06-09 11:37:01 +020024#ifdef CONFIG_RGMII
Ian Campbell58358232014-05-05 11:52:28 +010025 setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
26 CCM_GMAC_CTRL_GPIT_RGMII);
Chen-Yu Tsaief7e7232014-06-09 11:37:01 +020027#else
28 setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_MII |
29 CCM_GMAC_CTRL_GPIT_MII);
30#endif
Ian Campbell58358232014-05-05 11:52:28 +010031
Hans de Goedef885b842014-09-30 18:45:32 +020032 /*
33 * In order for the gmac nic to work reliable on the Bananapi, we
34 * need to set bits 10-12 GTXDC "GMAC Transmit Clock Delay Chain"
35 * of the GMAC clk register to 3.
36 */
Zoltan HERPAI64a97592014-11-11 13:21:26 +010037#ifdef CONFIG_TARGET_BANANAPI
Hans de Goedef885b842014-09-30 18:45:32 +020038 setbits_le32(&ccm->gmac_clk_cfg, 0x3 << 10);
39#endif
40
Hans de Goedeeafec322014-11-21 17:19:45 +010041#ifndef CONFIG_MACH_SUN6I
Ian Campbell58358232014-05-05 11:52:28 +010042 /* Configure pin mux settings for GMAC */
43 for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) {
Chen-Yu Tsaief7e7232014-06-09 11:37:01 +020044#ifdef CONFIG_RGMII
Ian Campbell58358232014-05-05 11:52:28 +010045 /* skip unused pins in RGMII mode */
46 if (pin == SUNXI_GPA(9) || pin == SUNXI_GPA(14))
47 continue;
Chen-Yu Tsaief7e7232014-06-09 11:37:01 +020048#endif
Ian Campbell58358232014-05-05 11:52:28 +010049 sunxi_gpio_set_cfgpin(pin, SUN7I_GPA0_GMAC);
50 sunxi_gpio_set_drv(pin, 3);
51 }
Hans de Goedeeafec322014-11-21 17:19:45 +010052#elif defined CONFIG_RGMII
53 /* Configure sun6i RGMII mode pin mux settings */
54 for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++) {
55 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
56 sunxi_gpio_set_drv(pin, 3);
57 }
58 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
59 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
60 sunxi_gpio_set_drv(pin, 3);
61 }
62 for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(20); pin++) {
63 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
64 sunxi_gpio_set_drv(pin, 3);
65 }
66 for (pin = SUNXI_GPA(25); pin <= SUNXI_GPA(27); pin++) {
67 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
68 sunxi_gpio_set_drv(pin, 3);
69 }
70#elif defined CONFIG_GMII
71 /* Configure sun6i GMII mode pin mux settings */
72 for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(27); pin++) {
73 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
74 sunxi_gpio_set_drv(pin, 2);
75 }
76#else
77 /* Configure sun6i MII mode pin mux settings */
78 for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++)
79 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
80 for (pin = SUNXI_GPA(8); pin <= SUNXI_GPA(9); pin++)
81 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
82 for (pin = SUNXI_GPA(11); pin <= SUNXI_GPA(14); pin++)
83 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
84 for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(24); pin++)
85 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
86 for (pin = SUNXI_GPA(26); pin <= SUNXI_GPA(27); pin++)
87 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
88#endif
Ian Campbell58358232014-05-05 11:52:28 +010089
Chen-Yu Tsaief7e7232014-06-09 11:37:01 +020090#ifdef CONFIG_RGMII
Ian Campbell58358232014-05-05 11:52:28 +010091 return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_RGMII);
Hans de Goedeeafec322014-11-21 17:19:45 +010092#elif defined CONFIG_GMII
93 return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_GMII);
Chen-Yu Tsaief7e7232014-06-09 11:37:01 +020094#else
95 return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_MII);
96#endif
Ian Campbell58358232014-05-05 11:52:28 +010097}