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Stelian Pop2118ebb2008-05-08 18:52:25 +02001/*
2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian.pop@leadtechdesign.com>
4 * Lead Tech Design <www.leadtechdesign.com>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <common.h>
26#include <asm/arch/at91sam9rl.h>
27#include <asm/arch/at91sam9rl_matrix.h>
28#include <asm/arch/at91sam9_smc.h>
Jean-Christophe PLAGNIOL-VILLARD1332a2a2009-03-21 21:07:59 +010029#include <asm/arch/at91_common.h>
Stelian Pop2118ebb2008-05-08 18:52:25 +020030#include <asm/arch/at91_pmc.h>
31#include <asm/arch/at91_rstc.h>
Jean-Christophe PLAGNIOL-VILLARDdc39ae92009-04-16 21:30:44 +020032#include <asm/arch/clk.h>
Stelian Pop2118ebb2008-05-08 18:52:25 +020033#include <asm/arch/gpio.h>
34#include <asm/arch/io.h>
Stelian Pop761c70b2008-05-08 14:52:32 +020035#include <lcd.h>
36#include <atmel_lcdc.h>
Stelian Pop2118ebb2008-05-08 18:52:25 +020037#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
38#include <net.h>
39#endif
40
41DECLARE_GLOBAL_DATA_PTR;
42
43/* ------------------------------------------------------------------------- */
44/*
45 * Miscelaneous platform dependent initialisations
46 */
47
Stelian Pop2118ebb2008-05-08 18:52:25 +020048#ifdef CONFIG_CMD_NAND
49static void at91sam9rlek_nand_hw_init(void)
50{
51 unsigned long csa;
52
53 /* Enable CS3 */
54 csa = at91_sys_read(AT91_MATRIX_EBICSA);
55 at91_sys_write(AT91_MATRIX_EBICSA,
56 csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
57
58 /* Configure SMC CS3 for NAND/SmartMedia */
59 at91_sys_write(AT91_SMC_SETUP(3),
Patrice Vilchezd3bcdf82008-05-27 11:15:29 +020060 AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
61 AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
Stelian Pop2118ebb2008-05-08 18:52:25 +020062 at91_sys_write(AT91_SMC_PULSE(3),
Patrice Vilchezd3bcdf82008-05-27 11:15:29 +020063 AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
64 AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
Stelian Pop2118ebb2008-05-08 18:52:25 +020065 at91_sys_write(AT91_SMC_CYCLE(3),
Patrice Vilchezd3bcdf82008-05-27 11:15:29 +020066 AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
Stelian Pop2118ebb2008-05-08 18:52:25 +020067 at91_sys_write(AT91_SMC_MODE(3),
68 AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
69 AT91_SMC_EXNWMODE_DISABLE |
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020070#ifdef CONFIG_SYS_NAND_DBW_16
Stelian Pop2118ebb2008-05-08 18:52:25 +020071 AT91_SMC_DBW_16 |
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020072#else /* CONFIG_SYS_NAND_DBW_8 */
Stelian Pop2118ebb2008-05-08 18:52:25 +020073 AT91_SMC_DBW_8 |
74#endif
Patrice Vilchezd3bcdf82008-05-27 11:15:29 +020075 AT91_SMC_TDF_(2));
Stelian Pop2118ebb2008-05-08 18:52:25 +020076
77 at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_PIOD);
78
79 /* Configure RDY/BSY */
Jean-Christophe PLAGNIOL-VILLARD74c076d2009-03-22 10:22:34 +010080 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
Stelian Pop2118ebb2008-05-08 18:52:25 +020081
82 /* Enable NandFlash */
Jean-Christophe PLAGNIOL-VILLARD74c076d2009-03-22 10:22:34 +010083 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
Stelian Pop2118ebb2008-05-08 18:52:25 +020084
85 at91_set_A_periph(AT91_PIN_PB4, 0); /* NANDOE */
86 at91_set_A_periph(AT91_PIN_PB5, 0); /* NANDWE */
87}
88#endif
89
Stelian Pop761c70b2008-05-08 14:52:32 +020090#ifdef CONFIG_LCD
91vidinfo_t panel_info = {
92 vl_col: 240,
93 vl_row: 320,
94 vl_clk: 4965000,
95 vl_sync: ATMEL_LCDC_INVLINE_INVERTED |
96 ATMEL_LCDC_INVFRAME_INVERTED,
97 vl_bpix: 3,
98 vl_tft: 1,
99 vl_hsync_len: 5,
100 vl_left_margin: 1,
101 vl_right_margin:33,
102 vl_vsync_len: 1,
103 vl_upper_margin:1,
104 vl_lower_margin:0,
105 mmio: AT91SAM9RL_LCDC_BASE,
106};
107
108void lcd_enable(void)
109{
110 at91_set_gpio_value(AT91_PIN_PA30, 0); /* power up */
111}
112
113void lcd_disable(void)
114{
115 at91_set_gpio_value(AT91_PIN_PA30, 1); /* power down */
116}
117static void at91sam9rlek_lcd_hw_init(void)
118{
119 at91_set_B_periph(AT91_PIN_PC1, 0); /* LCDPWR */
120 at91_set_A_periph(AT91_PIN_PC5, 0); /* LCDHSYNC */
121 at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDDOTCK */
122 at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDDEN */
123 at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDCC */
124 at91_set_B_periph(AT91_PIN_PC9, 0); /* LCDD3 */
125 at91_set_B_periph(AT91_PIN_PC10, 0); /* LCDD4 */
126 at91_set_B_periph(AT91_PIN_PC11, 0); /* LCDD5 */
127 at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD6 */
128 at91_set_B_periph(AT91_PIN_PC13, 0); /* LCDD7 */
129 at91_set_B_periph(AT91_PIN_PC15, 0); /* LCDD11 */
130 at91_set_B_periph(AT91_PIN_PC16, 0); /* LCDD12 */
131 at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD13 */
132 at91_set_B_periph(AT91_PIN_PC18, 0); /* LCDD14 */
133 at91_set_B_periph(AT91_PIN_PC19, 0); /* LCDD15 */
134 at91_set_B_periph(AT91_PIN_PC20, 0); /* LCDD18 */
135 at91_set_B_periph(AT91_PIN_PC21, 0); /* LCDD19 */
136 at91_set_B_periph(AT91_PIN_PC22, 0); /* LCDD20 */
137 at91_set_B_periph(AT91_PIN_PC23, 0); /* LCDD21 */
138 at91_set_B_periph(AT91_PIN_PC24, 0); /* LCDD22 */
139 at91_set_B_periph(AT91_PIN_PC25, 0); /* LCDD23 */
140
141 at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_LCDC);
142
143 gd->fb_base = 0;
144}
Haavard Skinnemoen6b59e032008-09-01 16:21:22 +0200145
146#ifdef CONFIG_LCD_INFO
147#include <nand.h>
148#include <version.h>
149
150void lcd_show_board_info(void)
151{
152 ulong dram_size, nand_size;
153 int i;
154 char temp[32];
155
156 lcd_printf ("%s\n", U_BOOT_VERSION);
157 lcd_printf ("(C) 2008 ATMEL Corp\n");
158 lcd_printf ("at91support@atmel.com\n");
159 lcd_printf ("%s CPU at %s MHz\n",
160 AT91_CPU_NAME,
Jean-Christophe PLAGNIOL-VILLARDdc39ae92009-04-16 21:30:44 +0200161 strmhz(temp, get_cpu_clk_rate()));
Haavard Skinnemoen6b59e032008-09-01 16:21:22 +0200162
163 dram_size = 0;
164 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
165 dram_size += gd->bd->bi_dram[i].size;
166 nand_size = 0;
167 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
168 nand_size += nand_info[i].size;
169 lcd_printf (" %ld MB SDRAM, %ld MB NAND\n",
170 dram_size >> 20,
171 nand_size >> 20 );
172}
173#endif /* CONFIG_LCD_INFO */
Stelian Pop761c70b2008-05-08 14:52:32 +0200174#endif
175
176
Stelian Pop2118ebb2008-05-08 18:52:25 +0200177int board_init(void)
178{
179 /* Enable Ctrlc */
180 console_init_f();
181
182 /* arch number of AT91SAM9RLEK-Board */
183 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9RLEK;
184 /* adress of boot parameters */
185 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
186
Jean-Christophe PLAGNIOL-VILLARD1332a2a2009-03-21 21:07:59 +0100187 at91_serial_hw_init();
Stelian Pop2118ebb2008-05-08 18:52:25 +0200188#ifdef CONFIG_CMD_NAND
189 at91sam9rlek_nand_hw_init();
190#endif
191#ifdef CONFIG_HAS_DATAFLASH
Jean-Christophe PLAGNIOL-VILLARD7ebafb72009-03-21 21:07:59 +0100192 at91_spi0_hw_init(1 << 0);
Stelian Pop2118ebb2008-05-08 18:52:25 +0200193#endif
Stelian Pop761c70b2008-05-08 14:52:32 +0200194#ifdef CONFIG_LCD
195 at91sam9rlek_lcd_hw_init();
196#endif
Stelian Pop2118ebb2008-05-08 18:52:25 +0200197 return 0;
198}
199
200int dram_init(void)
201{
202 gd->bd->bi_dram[0].start = PHYS_SDRAM;
203 gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
204 return 0;
205}