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Mingkai Hudd029362016-09-07 18:47:28 +08001/*
2 * Device Tree Include file for Freescale Layerscape-1046A family SoC.
3 *
4 * Copyright (C) 2016, Freescale Semiconductor
5 *
6 * Mingkai Hu <mingkai.hu@nxp.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13/include/ "skeleton64.dtsi"
14
15/ {
16 compatible = "fsl,ls1046a";
17 interrupt-parent = <&gic>;
18
19 sysclk: sysclk {
20 compatible = "fixed-clock";
21 #clock-cells = <0>;
22 clock-frequency = <100000000>;
23 clock-output-names = "sysclk";
24 };
25
26 gic: interrupt-controller@1400000 {
27 compatible = "arm,gic-400";
28 #interrupt-cells = <3>;
29 interrupt-controller;
30 reg = <0x0 0x1410000 0 0x10000>, /* GICD */
31 <0x0 0x1420000 0 0x10000>, /* GICC */
32 <0x0 0x1440000 0 0x20000>, /* GICH */
33 <0x0 0x1460000 0 0x20000>; /* GICV */
34 interrupts = <1 9 0xf08>;
35 };
36
37 soc {
38 compatible = "simple-bus";
39 #address-cells = <2>;
40 #size-cells = <2>;
41 ranges;
42
43 clockgen: clocking@1ee1000 {
44 compatible = "fsl,ls1046a-clockgen";
45 reg = <0x0 0x1ee1000 0x0 0x1000>;
46 #clock-cells = <2>;
47 clocks = <&sysclk>;
48 };
49
50 dspi0: dspi@2100000 {
51 compatible = "fsl,vf610-dspi";
52 #address-cells = <1>;
53 #size-cells = <0>;
54 reg = <0x0 0x2100000 0x0 0x10000>;
55 interrupts = <0 64 0x4>;
56 clock-names = "dspi";
57 clocks = <&clockgen 4 0>;
58 num-cs = <6>;
59 big-endian;
60 status = "disabled";
61 };
62
63 dspi1: dspi@2110000 {
64 compatible = "fsl,vf610-dspi";
65 #address-cells = <1>;
66 #size-cells = <0>;
67 reg = <0x0 0x2110000 0x0 0x10000>;
68 interrupts = <0 65 0x4>;
69 clock-names = "dspi";
70 clocks = <&clockgen 4 0>;
71 num-cs = <6>;
72 big-endian;
73 status = "disabled";
74 };
75
76 ifc: ifc@1530000 {
77 compatible = "fsl,ifc", "simple-bus";
78 reg = <0x0 0x1530000 0x0 0x10000>;
79 interrupts = <0 43 0x4>;
80 };
81
82 i2c0: i2c@2180000 {
83 compatible = "fsl,vf610-i2c";
84 #address-cells = <1>;
85 #size-cells = <0>;
86 reg = <0x0 0x2180000 0x0 0x10000>;
87 interrupts = <0 56 0x4>;
88 clock-names = "i2c";
89 clocks = <&clockgen 4 0>;
90 status = "disabled";
91 };
92
93 i2c1: i2c@2190000 {
94 compatible = "fsl,vf610-i2c";
95 #address-cells = <1>;
96 #size-cells = <0>;
97 reg = <0x0 0x2190000 0x0 0x10000>;
98 interrupts = <0 57 0x4>;
99 clock-names = "i2c";
100 clocks = <&clockgen 4 0>;
101 status = "disabled";
102 };
103
104 i2c2: i2c@21a0000 {
105 compatible = "fsl,vf610-i2c";
106 #address-cells = <1>;
107 #size-cells = <0>;
108 reg = <0x0 0x21a0000 0x0 0x10000>;
109 interrupts = <0 58 0x4>;
110 clock-names = "i2c";
111 clocks = <&clockgen 4 0>;
112 status = "disabled";
113 };
114
115 i2c3: i2c@21b0000 {
116 compatible = "fsl,vf610-i2c";
117 #address-cells = <1>;
118 #size-cells = <0>;
119 reg = <0x0 0x21b0000 0x0 0x10000>;
120 interrupts = <0 59 0x4>;
121 clock-names = "i2c";
122 clocks = <&clockgen 4 0>;
123 status = "disabled";
124 };
125
126 duart0: serial@21c0500 {
127 compatible = "fsl,ns16550", "ns16550a";
128 reg = <0x00 0x21c0500 0x0 0x100>;
129 interrupts = <0 54 0x4>;
130 clocks = <&clockgen 4 0>;
131 };
132
133 duart1: serial@21c0600 {
134 compatible = "fsl,ns16550", "ns16550a";
135 reg = <0x00 0x21c0600 0x0 0x100>;
136 interrupts = <0 54 0x4>;
137 clocks = <&clockgen 4 0>;
138 };
139
140 duart2: serial@21d0500 {
141 compatible = "fsl,ns16550", "ns16550a";
142 reg = <0x0 0x21d0500 0x0 0x100>;
143 interrupts = <0 55 0x4>;
144 clocks = <&clockgen 4 0>;
145 };
146
147 duart3: serial@21d0600 {
148 compatible = "fsl,ns16550", "ns16550a";
149 reg = <0x0 0x21d0600 0x0 0x100>;
150 interrupts = <0 55 0x4>;
151 clocks = <&clockgen 4 0>;
152 };
153
Shaohui Xiefdc2b542016-10-28 14:24:02 +0800154 lpuart0: serial@2950000 {
155 compatible = "fsl,ls1021a-lpuart";
156 reg = <0x0 0x2950000 0x0 0x1000>;
157 interrupts = <0 48 0x4>;
158 clocks = <&clockgen 4 0>;
159 clock-names = "ipg";
160 status = "disabled";
161 };
162
163 lpuart1: serial@2960000 {
164 compatible = "fsl,ls1021a-lpuart";
165 reg = <0x0 0x2960000 0x0 0x1000>;
166 interrupts = <0 49 0x4>;
167 clocks = <&clockgen 4 1>;
168 clock-names = "ipg";
169 status = "disabled";
170 };
171
172 lpuart2: serial@2970000 {
173 compatible = "fsl,ls1021a-lpuart";
174 reg = <0x0 0x2970000 0x0 0x1000>;
175 interrupts = <0 50 0x4>;
176 clocks = <&clockgen 4 1>;
177 clock-names = "ipg";
178 status = "disabled";
179 };
180
181 lpuart3: serial@2980000 {
182 compatible = "fsl,ls1021a-lpuart";
183 reg = <0x0 0x2980000 0x0 0x1000>;
184 interrupts = <0 51 0x4>;
185 clocks = <&clockgen 4 1>;
186 clock-names = "ipg";
187 status = "disabled";
188 };
189
190 lpuart4: serial@2990000 {
191 compatible = "fsl,ls1021a-lpuart";
192 reg = <0x0 0x2990000 0x0 0x1000>;
193 interrupts = <0 52 0x4>;
194 clocks = <&clockgen 4 1>;
195 clock-names = "ipg";
196 status = "disabled";
197 };
198
199 lpuart5: serial@29a0000 {
200 compatible = "fsl,ls1021a-lpuart";
201 reg = <0x0 0x29a0000 0x0 0x1000>;
202 interrupts = <0 53 0x4>;
203 clocks = <&clockgen 4 1>;
204 clock-names = "ipg";
205 status = "disabled";
206 };
207
Mingkai Hudd029362016-09-07 18:47:28 +0800208 qspi: quadspi@1550000 {
209 compatible = "fsl,vf610-qspi";
210 #address-cells = <1>;
211 #size-cells = <0>;
212 reg = <0x0 0x1550000 0x0 0x10000>,
213 <0x0 0x40000000 0x0 0x10000000>;
214 reg-names = "QuadSPI", "QuadSPI-memory";
215 num-cs = <4>;
216 big-endian;
217 status = "disabled";
218 };
Minghuan Lianb948a162016-12-13 14:54:14 +0800219
Tang Yuantian272a24f2017-01-20 17:12:48 +0800220 usb0: usb@2f00000 {
221 compatible = "fsl,layerscape-dwc3";
222 reg = <0x0 0x2f00000 0x0 0x10000>;
223 interrupts = <0 60 4>;
224 dr_mode = "host";
225 };
226
227 usb1: usb@3000000 {
228 compatible = "fsl,layerscape-dwc3";
229 reg = <0x0 0x3000000 0x0 0x10000>;
230 interrupts = <0 61 4>;
231 dr_mode = "host";
232 };
233
234 usb2: usb@3100000 {
235 compatible = "fsl,layerscape-dwc3";
236 reg = <0x0 0x3100000 0x0 0x10000>;
237 interrupts = <0 63 4>;
238 dr_mode = "host";
239 };
240
Minghuan Lianb948a162016-12-13 14:54:14 +0800241 pcie@3400000 {
242 compatible = "fsl,ls-pcie", "snps,dw-pcie";
243 reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */
244 0x00 0x03480000 0x0 0x40000 /* lut registers */
245 0x00 0x034c0000 0x0 0x40000 /* pf controls registers */
246 0x40 0x00000000 0x0 0x20000>; /* configuration space */
247 reg-names = "dbi", "lut", "ctrl", "config";
248 big-endian;
249 #address-cells = <3>;
250 #size-cells = <2>;
251 device_type = "pci";
252 bus-range = <0x0 0xff>;
253 ranges = <0x81000000 0x0 0x00000000 0x40 0x00020000 0x0 0x00010000 /* downstream I/O */
254 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
255 };
256
257 pcie@3500000 {
258 compatible = "fsl,ls-pcie", "snps,dw-pcie";
259 reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */
260 0x00 0x03580000 0x0 0x40000 /* lut registers */
261 0x00 0x035c0000 0x0 0x40000 /* pf controls registers */
262 0x48 0x00000000 0x0 0x20000>; /* configuration space */
263 reg-names = "dbi", "lut", "ctrl", "config";
264 big-endian;
265 #address-cells = <3>;
266 #size-cells = <2>;
267 device_type = "pci";
268 num-lanes = <2>;
269 bus-range = <0x0 0xff>;
270 ranges = <0x81000000 0x0 0x00000000 0x48 0x00020000 0x0 0x00010000 /* downstream I/O */
271 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
272 };
273
274 pcie@3600000 {
275 compatible = "fsl,ls-pcie", "snps,dw-pcie";
276 reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */
277 0x00 0x03680000 0x0 0x40000 /* lut registers */
278 0x00 0x036c0000 0x0 0x40000 /* pf controls registers */
279 0x50 0x00000000 0x0 0x20000>; /* configuration space */
280 reg-names = "dbi", "lut", "ctrl", "config";
281 big-endian;
282 #address-cells = <3>;
283 #size-cells = <2>;
284 device_type = "pci";
285 bus-range = <0x0 0xff>;
286 ranges = <0x81000000 0x0 0x00000000 0x50 0x00020000 0x0 0x00010000 /* downstream I/O */
287 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
288 };
Mingkai Hudd029362016-09-07 18:47:28 +0800289 };
290};