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Ruchika Gupta48ef0d22014-09-09 11:50:30 +05301/*
2 * Common internal memory map for some Freescale SoCs
3 *
4 * Copyright 2014 Freescale Semiconductor, Inc.
5 *
6 */
7
8#ifndef __FSL_SEC_H
9#define __FSL_SEC_H
10
11#include <common.h>
12#include <asm/io.h>
13
Ruchika Gupta028dbb82014-09-09 11:50:31 +053014#ifdef CONFIG_SYS_FSL_SEC_LE
15#define sec_in32(a) in_le32(a)
16#define sec_out32(a, v) out_le32(a, v)
17#define sec_in16(a) in_le16(a)
18#define sec_clrbits32 clrbits_le32
19#define sec_setbits32 setbits_le32
20#elif defined(CONFIG_SYS_FSL_SEC_BE)
21#define sec_in32(a) in_be32(a)
22#define sec_out32(a, v) out_be32(a, v)
23#define sec_in16(a) in_be16(a)
24#define sec_clrbits32 clrbits_be32
25#define sec_setbits32 setbits_be32
26#else
27#error Neither CONFIG_SYS_FSL_SEC_LE nor CONFIG_SYS_FSL_SEC_BE is defined
28#endif
29
Ruchika Gupta48ef0d22014-09-09 11:50:30 +053030/* Security Engine Block (MS = Most Sig., LS = Least Sig.) */
31#if CONFIG_SYS_FSL_SEC_COMPAT >= 4
Ruchika Guptac5de15c2014-10-07 15:46:20 +053032/* RNG4 TRNG test registers */
33struct rng4tst {
34#define RTMCTL_PRGM 0x00010000 /* 1 -> program mode, 0 -> run mode */
Alex Porosanuc4065512015-05-05 16:48:35 +030035#define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_SC 0 /* use von Neumann data in
36 both entropy shifter and
37 statistical checker */
38#define RTMCTL_SAMP_MODE_RAW_ES_SC 1 /* use raw data in both
39 entropy shifter and
40 statistical checker */
41#define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_RAW_SC 2 /* use von Neumann data in
42 entropy shifter, raw data
43 in statistical checker */
44#define RTMCTL_SAMP_MODE_INVALID 3 /* invalid combination */
Ruchika Guptac5de15c2014-10-07 15:46:20 +053045 u32 rtmctl; /* misc. control register */
46 u32 rtscmisc; /* statistical check misc. register */
47 u32 rtpkrrng; /* poker range register */
Alex Porosanu17649e12015-05-05 16:48:34 +030048#define RTSDCTL_ENT_DLY_MIN 3200
Ruchika Guptac5de15c2014-10-07 15:46:20 +053049#define RTSDCTL_ENT_DLY_MAX 12800
50 union {
51 u32 rtpkrmax; /* PRGM=1: poker max. limit register */
52 u32 rtpkrsq; /* PRGM=0: poker square calc. result register */
53 };
54#define RTSDCTL_ENT_DLY_SHIFT 16
55#define RTSDCTL_ENT_DLY_MASK (0xffff << RTSDCTL_ENT_DLY_SHIFT)
56 u32 rtsdctl; /* seed control register */
57 union {
58 u32 rtsblim; /* PRGM=1: sparse bit limit register */
59 u32 rttotsam; /* PRGM=0: total samples register */
60 };
61 u32 rtfreqmin; /* frequency count min. limit register */
Alex Porosanu026a3f12015-05-05 16:48:33 +030062#define RTFRQMAX_DISABLE (1 << 20)
Ruchika Guptac5de15c2014-10-07 15:46:20 +053063 union {
64 u32 rtfreqmax; /* PRGM=1: freq. count max. limit register */
65 u32 rtfreqcnt; /* PRGM=0: freq. count register */
66 };
67 u32 rsvd1[40];
68#define RNG_STATE0_HANDLE_INSTANTIATED 0x00000001
69 u32 rdsta; /*RNG DRNG Status Register*/
70 u32 rsvd2[15];
71};
72
Ruchika Gupta48ef0d22014-09-09 11:50:30 +053073typedef struct ccsr_sec {
74 u32 res0;
75 u32 mcfgr; /* Master CFG Register */
76 u8 res1[0x4];
77 u32 scfgr;
78 struct {
79 u32 ms; /* Job Ring LIODN Register, MS */
80 u32 ls; /* Job Ring LIODN Register, LS */
81 } jrliodnr[4];
82 u8 res2[0x2c];
83 u32 jrstartr; /* Job Ring Start Register */
84 struct {
85 u32 ms; /* RTIC LIODN Register, MS */
86 u32 ls; /* RTIC LIODN Register, LS */
87 } rticliodnr[4];
88 u8 res3[0x1c];
89 u32 decorr; /* DECO Request Register */
90 struct {
91 u32 ms; /* DECO LIODN Register, MS */
92 u32 ls; /* DECO LIODN Register, LS */
93 } decoliodnr[8];
94 u8 res4[0x40];
95 u32 dar; /* DECO Avail Register */
96 u32 drr; /* DECO Reset Register */
Ruchika Guptac5de15c2014-10-07 15:46:20 +053097 u8 res5[0x4d8];
98 struct rng4tst rng; /* RNG Registers */
99 u8 res11[0x8a0];
Ruchika Gupta48ef0d22014-09-09 11:50:30 +0530100 u32 crnr_ms; /* CHA Revision Number Register, MS */
101 u32 crnr_ls; /* CHA Revision Number Register, LS */
102 u32 ctpr_ms; /* Compile Time Parameters Register, MS */
103 u32 ctpr_ls; /* Compile Time Parameters Register, LS */
104 u8 res6[0x10];
105 u32 far_ms; /* Fault Address Register, MS */
106 u32 far_ls; /* Fault Address Register, LS */
107 u32 falr; /* Fault Address LIODN Register */
108 u32 fadr; /* Fault Address Detail Register */
109 u8 res7[0x4];
110 u32 csta; /* CAAM Status Register */
111 u8 res8[0x8];
112 u32 rvid; /* Run Time Integrity Checking Version ID Reg.*/
113 u32 ccbvid; /* CHA Cluster Block Version ID Register */
114 u32 chavid_ms; /* CHA Version ID Register, MS */
115 u32 chavid_ls; /* CHA Version ID Register, LS */
116 u32 chanum_ms; /* CHA Number Register, MS */
117 u32 chanum_ls; /* CHA Number Register, LS */
118 u32 secvid_ms; /* SEC Version ID Register, MS */
119 u32 secvid_ls; /* SEC Version ID Register, LS */
120 u8 res9[0x6020];
121 u32 qilcr_ms; /* Queue Interface LIODN CFG Register, MS */
122 u32 qilcr_ls; /* Queue Interface LIODN CFG Register, LS */
123 u8 res10[0x8fd8];
124} ccsr_sec_t;
125
126#define SEC_CTPR_MS_AXI_LIODN 0x08000000
127#define SEC_CTPR_MS_QI 0x02000000
128#define SEC_CTPR_MS_VIRT_EN_INCL 0x00000001
129#define SEC_CTPR_MS_VIRT_EN_POR 0x00000002
130#define SEC_RVID_MA 0x0f000000
131#define SEC_CHANUM_MS_JRNUM_MASK 0xf0000000
132#define SEC_CHANUM_MS_JRNUM_SHIFT 28
133#define SEC_CHANUM_MS_DECONUM_MASK 0x0f000000
134#define SEC_CHANUM_MS_DECONUM_SHIFT 24
135#define SEC_SECVID_MS_IPID_MASK 0xffff0000
136#define SEC_SECVID_MS_IPID_SHIFT 16
137#define SEC_SECVID_MS_MAJ_REV_MASK 0x0000ff00
138#define SEC_SECVID_MS_MAJ_REV_SHIFT 8
139#define SEC_CCBVID_ERA_MASK 0xff000000
140#define SEC_CCBVID_ERA_SHIFT 24
141#define SEC_SCFGR_RDBENABLE 0x00000400
142#define SEC_SCFGR_VIRT_EN 0x00008000
143#define SEC_CHAVID_LS_RNG_SHIFT 16
144#define SEC_CHAVID_RNG_LS_MASK 0x000f0000
Ruchika Guptab9eebfa2014-10-15 11:35:30 +0530145
146#define CONFIG_JRSTARTR_JR0 0x00000001
147
148struct jr_regs {
Raul Cardenas02000202015-02-27 11:22:06 -0600149#if defined(CONFIG_SYS_FSL_SEC_LE) && !defined(CONFIG_MX6)
Ruchika Guptab9eebfa2014-10-15 11:35:30 +0530150 u32 irba_l;
151 u32 irba_h;
152#else
153 u32 irba_h;
154 u32 irba_l;
155#endif
156 u32 rsvd1;
157 u32 irs;
158 u32 rsvd2;
159 u32 irsa;
160 u32 rsvd3;
161 u32 irja;
Raul Cardenas02000202015-02-27 11:22:06 -0600162#if defined(CONFIG_SYS_FSL_SEC_LE) && !defined(CONFIG_MX6)
Ruchika Guptab9eebfa2014-10-15 11:35:30 +0530163 u32 orba_l;
164 u32 orba_h;
165#else
166 u32 orba_h;
167 u32 orba_l;
168#endif
169 u32 rsvd4;
170 u32 ors;
171 u32 rsvd5;
172 u32 orjr;
173 u32 rsvd6;
174 u32 orsf;
175 u32 rsvd7;
176 u32 jrsta;
177 u32 rsvd8;
178 u32 jrint;
179 u32 jrcfg0;
180 u32 jrcfg1;
181 u32 rsvd9;
182 u32 irri;
183 u32 rsvd10;
184 u32 orwi;
185 u32 rsvd11;
186 u32 jrcr;
187};
188
gaurav rana94e3c8c2015-02-20 12:51:46 +0530189/*
190 * Scatter Gather Entry - Specifies the the Scatter Gather Format
191 * related information
192 */
193struct sg_entry {
Tom Rini33d51562015-03-05 08:56:39 -0500194#if defined(CONFIG_SYS_FSL_SEC_LE) && !defined(CONFIG_MX6)
gaurav rana94e3c8c2015-02-20 12:51:46 +0530195 uint32_t addr_lo; /* Memory Address - lo */
196 uint16_t addr_hi; /* Memory Address of start of buffer - hi */
197 uint16_t reserved_zero;
198#else
199 uint16_t reserved_zero;
200 uint16_t addr_hi; /* Memory Address of start of buffer - hi */
201 uint32_t addr_lo; /* Memory Address - lo */
202#endif
203
204 uint32_t len_flag; /* Length of the data in the frame */
205#define SG_ENTRY_LENGTH_MASK 0x3FFFFFFF
206#define SG_ENTRY_EXTENSION_BIT 0x80000000
207#define SG_ENTRY_FINAL_BIT 0x40000000
208 uint32_t bpid_offset;
209#define SG_ENTRY_BPID_MASK 0x00FF0000
210#define SG_ENTRY_BPID_SHIFT 16
211#define SG_ENTRY_OFFSET_MASK 0x00001FFF
212#define SG_ENTRY_OFFSET_SHIFT 0
213};
214
Raul Cardenas02000202015-02-27 11:22:06 -0600215#ifdef CONFIG_MX6
216/* CAAM Job Ring 0 Registers */
217/* Secure Memory Partition Owner register */
218#define SMCSJR_PO (3 << 6)
219/* JR Allocation Error */
220#define SMCSJR_AERR (3 << 12)
221/* Secure memory partition 0 page 0 owner register */
222#define CAAM_SMPO_0 CONFIG_SYS_FSL_SEC_ADDR + 0x1FBC
223/* Secure memory command register */
224#define CAAM_SMCJR0 CONFIG_SYS_FSL_SEC_ADDR + 0x10f4
225/* Secure memory command status register */
226#define CAAM_SMCSJR0 CONFIG_SYS_FSL_SEC_ADDR + 0x10fc
227/* Secure memory access permissions register */
228#define CAAM_SMAPJR0(y) (CONFIG_SYS_FSL_SEC_ADDR + 0x1104 + y*16)
229/* Secure memory access group 2 register */
230#define CAAM_SMAG2JR0(y) (CONFIG_SYS_FSL_SEC_ADDR + 0x1108 + y*16)
231/* Secure memory access group 1 register */
232#define CAAM_SMAG1JR0(y) (CONFIG_SYS_FSL_SEC_ADDR + 0x110C + y*16)
233
234/* Commands and macros for secure memory */
235#define CMD_PAGE_ALLOC 0x1
236#define CMD_PAGE_DEALLOC 0x2
237#define CMD_PART_DEALLOC 0x3
238#define CMD_INQUIRY 0x5
239#define CMD_COMPLETE (3 << 14)
240#define PAGE_AVAILABLE 0
241#define PAGE_OWNED (3 << 6)
242#define PAGE(x) (x << 16)
243#define PARTITION(x) (x << 8)
244#define PARTITION_OWNER(x) (0x3 << (x*2))
245
246/* Address of secure 4kbyte pages */
247#define SEC_MEM_PAGE0 CAAM_ARB_BASE_ADDR
248#define SEC_MEM_PAGE1 (CAAM_ARB_BASE_ADDR + 0x1000)
249#define SEC_MEM_PAGE2 (CAAM_ARB_BASE_ADDR + 0x2000)
250#define SEC_MEM_PAGE3 (CAAM_ARB_BASE_ADDR + 0x3000)
251
252#define JR_MID 2 /* Matches ROM configuration */
253#define KS_G1 (1 << JR_MID) /* CAAM only */
254#define PERM 0x0000B008 /* Clear on release, lock SMAP
255 * lock SMAG group 1 Blob */
256
257#define BLOB_SIZE(x) (x + 32 + 16) /* Blob buffer size */
258
259/* HAB WRAPPED KEY header */
260#define WRP_HDR_SIZE 0x08
261#define HDR_TAG 0x81
262#define HDR_PAR 0x41
263/* HAB WRAPPED KEY Data */
264#define HAB_MOD 0x66
265#define HAB_ALG 0x55
266#define HAB_FLG 0x00
267
268/* Partition and Page IDs */
269#define PARTITION_1 1
270#define PAGE_1 1
271
272#define ERROR_IN_PAGE_ALLOC 1
273#define ECONSTRJDESC -1
274
275#endif
276
Ruchika Guptab9eebfa2014-10-15 11:35:30 +0530277int sec_init(void);
Raul Cardenas02000202015-02-27 11:22:06 -0600278
279/* blob_dek:
280 * Encapsulates the src in a secure blob and stores it dst
281 * @src: reference to the plaintext
282 * @dst: reference to the output adrress
283 * @len: size in bytes of src
284 * @return: 0 on success, error otherwise
285 */
286int blob_dek(const u8 *src, u8 *dst, u8 len);
287
Ruchika Gupta48ef0d22014-09-09 11:50:30 +0530288#endif
289
290#endif /* __FSL_SEC_H */