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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 28afb716463919c261cffc6fddd594fac87557bb / . / board / nvidia / jetson-tk1 / pinmux-config-jetson-tk1.h
blob: fc5cdd1eb1194baf93a38bab00d2f3e9ae4c07d0 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]2/*
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]3 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]4 */
5
Stephen Warren95486f82015-07-30 14:34:09 -0600[diff] [blame]6/*
7 * THIS FILE IS AUTO-GENERATED - DO NOT EDIT!
8 *
9 * To generate this file, use the tegra-pinmux-scripts tool available from
10 * https://github.com/NVIDIA/tegra-pinmux-scripts
11 * Run "board-to-uboot.py jetson-tk1".
12 */
13
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]14#ifndef _PINMUX_CONFIG_JETSON_TK1_H_
15#define _PINMUX_CONFIG_JETSON_TK1_H_
16
Stephen Warren01a97a12016-05-12 12:07:39 -0600[diff] [blame]17#define GPIO_INIT(_port, _gpio, _init) \
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]18 { \
Stephen Warren01a97a12016-05-12 12:07:39 -0600[diff] [blame]19 .gpio = TEGRA_GPIO(_port, _gpio), \
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]20 .init = TEGRA_GPIO_INIT_##_init, \
21 }
22
23static const struct tegra_gpio_config jetson_tk1_gpio_inits[] = {
Stephen Warren01a97a12016-05-12 12:07:39 -0600[diff] [blame]24 /* port, pin, init_val */
25 GPIO_INIT(G, 0, IN),
26 GPIO_INIT(G, 1, IN),
27 GPIO_INIT(G, 2, IN),
28 GPIO_INIT(G, 3, IN),
29 GPIO_INIT(G, 4, IN),
30 GPIO_INIT(H, 2, OUT0),
31 GPIO_INIT(H, 4, IN),
32 GPIO_INIT(H, 7, IN),
33 GPIO_INIT(I, 0, OUT0),
34 GPIO_INIT(I, 1, IN),
35 GPIO_INIT(I, 6, IN),
36 GPIO_INIT(J, 0, IN),
37 GPIO_INIT(K, 1, OUT0),
38 GPIO_INIT(K, 2, IN),
39 GPIO_INIT(K, 4, OUT0),
40 GPIO_INIT(K, 6, OUT0),
41 GPIO_INIT(N, 7, IN),
42 GPIO_INIT(O, 1, IN),
43 GPIO_INIT(O, 4, IN),
44 GPIO_INIT(P, 2, OUT0),
45 GPIO_INIT(Q, 0, IN),
46 GPIO_INIT(Q, 3, IN),
47 GPIO_INIT(Q, 5, IN),
48 GPIO_INIT(R, 0, OUT0),
49 GPIO_INIT(R, 2, OUT0),
50 GPIO_INIT(R, 4, IN),
51 GPIO_INIT(R, 7, IN),
52 GPIO_INIT(S, 7, IN),
53 GPIO_INIT(T, 0, OUT0),
54 GPIO_INIT(T, 1, IN),
55 GPIO_INIT(U, 0, IN),
56 GPIO_INIT(U, 1, IN),
57 GPIO_INIT(U, 2, IN),
58 GPIO_INIT(U, 3, IN),
59 GPIO_INIT(U, 4, IN),
60 GPIO_INIT(U, 5, IN),
61 GPIO_INIT(U, 6, IN),
62 GPIO_INIT(V, 0, IN),
63 GPIO_INIT(V, 1, IN),
64 GPIO_INIT(X, 1, IN),
65 GPIO_INIT(X, 4, IN),
66 GPIO_INIT(X, 7, OUT0),
67 GPIO_INIT(BB, 3, OUT0),
68 GPIO_INIT(BB, 5, OUT0),
69 GPIO_INIT(BB, 6, OUT0),
70 GPIO_INIT(BB, 7, OUT0),
71 GPIO_INIT(CC, 1, IN),
72 GPIO_INIT(CC, 2, IN),
73 GPIO_INIT(EE, 2, OUT1),
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]74};
75
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]76#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel) \
77 { \
78 .pingrp = PMUX_PINGRP_##_pingrp, \
79 .func = PMUX_FUNC_##_mux, \
80 .pull = PMUX_PULL_##_pull, \
81 .tristate = PMUX_TRI_##_tri, \
82 .io = PMUX_PIN_##_io, \
83 .od = PMUX_PIN_OD_##_od, \
84 .rcv_sel = PMUX_PIN_RCV_SEL_##_rcv_sel, \
85 .lock = PMUX_PIN_LOCK_DEFAULT, \
86 .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
87 }
88
89static const struct pmux_pingrp_config jetson_tk1_pingrps[] = {
90 /* pingrp, mux, pull, tri, e_input, od, rcv_sel */
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]91 PINCFG(CLK_32K_OUT_PA0, SOC, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
92 PINCFG(UART3_CTS_N_PA1, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
93 PINCFG(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
94 PINCFG(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
95 PINCFG(DAP2_DIN_PA4, I2S1, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
96 PINCFG(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
97 PINCFG(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]98 PINCFG(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]99 PINCFG(PB0, UARTD, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
100 PINCFG(PB1, UARTD, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]101 PINCFG(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
102 PINCFG(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
103 PINCFG(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
104 PINCFG(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]105 PINCFG(UART3_RTS_N_PC0, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]106 PINCFG(UART2_TXD_PC2, IRDA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]107 PINCFG(UART2_RXD_PC3, IRDA, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]108 PINCFG(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
109 PINCFG(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]110 PINCFG(PC7, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
111 PINCFG(PG0, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
112 PINCFG(PG1, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
113 PINCFG(PG2, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
114 PINCFG(PG3, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
115 PINCFG(PG4, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]116 PINCFG(PG5, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
117 PINCFG(PG6, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]118 PINCFG(PG7, SPI4, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]119 PINCFG(PH0, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
120 PINCFG(PH1, PWM1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]121 PINCFG(PH2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]122 PINCFG(PH3, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
123 PINCFG(PH4, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
124 PINCFG(PH5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
125 PINCFG(PH6, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
126 PINCFG(PH7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]127 PINCFG(PI0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]128 PINCFG(PI1, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
129 PINCFG(PI2, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]130 PINCFG(PI3, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]131 PINCFG(PI4, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
132 PINCFG(PI5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
133 PINCFG(PI6, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]134 PINCFG(PI7, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]135 PINCFG(PJ0, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
136 PINCFG(PJ2, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
137 PINCFG(UART2_CTS_N_PJ5, UARTB, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]138 PINCFG(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
139 PINCFG(PJ7, UARTD, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]140 PINCFG(PK0, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]141 PINCFG(PK1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]142 PINCFG(PK2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
143 PINCFG(PK3, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]144 PINCFG(PK4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]145 PINCFG(SPDIF_OUT_PK5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]146 PINCFG(SPDIF_IN_PK6, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]147 PINCFG(PK7, UARTD, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]148 PINCFG(DAP1_FS_PN0, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
149 PINCFG(DAP1_DIN_PN1, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]150 PINCFG(DAP1_DOUT_PN2, SATA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]151 PINCFG(DAP1_SCLK_PN3, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
152 PINCFG(USB_VBUS_EN0_PN4, USB, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
153 PINCFG(USB_VBUS_EN1_PN5, USB, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
154 PINCFG(HDMI_INT_PN7, DEFAULT, DOWN, TRISTATE, INPUT, DEFAULT, NORMAL),
155 PINCFG(ULPI_DATA7_PO0, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
156 PINCFG(ULPI_DATA0_PO1, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
157 PINCFG(ULPI_DATA1_PO2, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
158 PINCFG(ULPI_DATA2_PO3, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
159 PINCFG(ULPI_DATA3_PO4, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
160 PINCFG(ULPI_DATA4_PO5, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
161 PINCFG(ULPI_DATA5_PO6, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
162 PINCFG(ULPI_DATA6_PO7, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
163 PINCFG(DAP3_FS_PP0, I2S2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
164 PINCFG(DAP3_DIN_PP1, I2S2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]165 PINCFG(DAP3_DOUT_PP2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]166 PINCFG(DAP3_SCLK_PP3, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]167 PINCFG(DAP4_FS_PP4, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
168 PINCFG(DAP4_DIN_PP5, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
169 PINCFG(DAP4_DOUT_PP6, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
170 PINCFG(DAP4_SCLK_PP7, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
171 PINCFG(KB_COL0_PQ0, DEFAULT, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
172 PINCFG(KB_COL1_PQ1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
173 PINCFG(KB_COL2_PQ2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
174 PINCFG(KB_COL3_PQ3, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
175 PINCFG(KB_COL4_PQ4, SDMMC3, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
176 PINCFG(KB_COL5_PQ5, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
177 PINCFG(KB_COL6_PQ6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
178 PINCFG(KB_COL7_PQ7, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]179 PINCFG(KB_ROW0_PR0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]180 PINCFG(KB_ROW1_PR1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]181 PINCFG(KB_ROW2_PR2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]182 PINCFG(KB_ROW3_PR3, KBC, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
183 PINCFG(KB_ROW4_PR4, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
184 PINCFG(KB_ROW5_PR5, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
185 PINCFG(KB_ROW6_PR6, DISPLAYA_ALT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
186 PINCFG(KB_ROW7_PR7, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
187 PINCFG(KB_ROW8_PS0, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
188 PINCFG(KB_ROW9_PS1, UARTA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
189 PINCFG(KB_ROW10_PS2, UARTA, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
190 PINCFG(KB_ROW11_PS3, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
191 PINCFG(KB_ROW12_PS4, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
192 PINCFG(KB_ROW13_PS5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
193 PINCFG(KB_ROW14_PS6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
194 PINCFG(KB_ROW15_PS7, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]195 PINCFG(KB_ROW16_PT0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]196 PINCFG(KB_ROW17_PT1, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]197 PINCFG(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
198 PINCFG(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
199 PINCFG(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]200 PINCFG(PU0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
201 PINCFG(PU1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
202 PINCFG(PU2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
203 PINCFG(PU3, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
204 PINCFG(PU4, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
205 PINCFG(PU5, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
206 PINCFG(PU6, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
207 PINCFG(PV0, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
208 PINCFG(PV1, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
209 PINCFG(SDMMC3_CD_N_PV2, SDMMC3, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]210 PINCFG(SDMMC1_WP_N_PV3, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
211 PINCFG(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL),
212 PINCFG(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]213 PINCFG(GPIO_W2_AUD_PW2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
214 PINCFG(GPIO_W3_AUD_PW3, SPI6, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]215 PINCFG(DAP_MCLK1_PW4, EXTPERIPH1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
216 PINCFG(CLK2_OUT_PW5, EXTPERIPH2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]217 PINCFG(UART3_TXD_PW6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
218 PINCFG(UART3_RXD_PW7, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]219 PINCFG(DVFS_PWM_PX0, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]220 PINCFG(GPIO_X1_AUD_PX1, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]221 PINCFG(DVFS_CLK_PX2, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]222 PINCFG(GPIO_X3_AUD_PX3, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
223 PINCFG(GPIO_X4_AUD_PX4, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
224 PINCFG(GPIO_X5_AUD_PX5, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
225 PINCFG(GPIO_X6_AUD_PX6, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]226 PINCFG(GPIO_X7_AUD_PX7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]227 PINCFG(ULPI_CLK_PY0, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]228 PINCFG(ULPI_DIR_PY1, SPI1, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]229 PINCFG(ULPI_NXT_PY2, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
230 PINCFG(ULPI_STP_PY3, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]231 PINCFG(SDMMC1_DAT3_PY4, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
232 PINCFG(SDMMC1_DAT2_PY5, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
233 PINCFG(SDMMC1_DAT1_PY6, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
234 PINCFG(SDMMC1_DAT0_PY7, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
235 PINCFG(SDMMC1_CLK_PZ0, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
236 PINCFG(SDMMC1_CMD_PZ1, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]237 PINCFG(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
238 PINCFG(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
239 PINCFG(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
240 PINCFG(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
241 PINCFG(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
242 PINCFG(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
243 PINCFG(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
244 PINCFG(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
245 PINCFG(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
246 PINCFG(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
247 PINCFG(PBB0, VIMCLK2_ALT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
248 PINCFG(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
249 PINCFG(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]250 PINCFG(PBB3, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]251 PINCFG(PBB4, VGP4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]252 PINCFG(PBB5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
253 PINCFG(PBB6, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
254 PINCFG(PBB7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]255 PINCFG(CAM_MCLK_PCC0, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]256 PINCFG(PCC1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
257 PINCFG(PCC2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]258 PINCFG(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]259 PINCFG(CLK2_REQ_PCC5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
Stephen Warren606f5bc2014-08-22 15:04:08 -0600[diff] [blame]260 PINCFG(PEX_L0_RST_N_PDD1, PE0, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]261 PINCFG(PEX_L0_CLKREQ_N_PDD2, PE0, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
262 PINCFG(PEX_WAKE_N_PDD3, PE, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
Stephen Warren606f5bc2014-08-22 15:04:08 -0600[diff] [blame]263 PINCFG(PEX_L1_RST_N_PDD5, PE1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]264 PINCFG(PEX_L1_CLKREQ_N_PDD6, PE1, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]265 PINCFG(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]266 PINCFG(CLK3_REQ_PEE1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
267 PINCFG(DAP_MCLK1_REQ_PEE2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
268 PINCFG(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]269 PINCFG(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
270 PINCFG(SDMMC3_CLK_LB_IN_PEE5, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]271 PINCFG(DP_HPD_PFF0, DP, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
272 PINCFG(USB_VBUS_EN2_PFF1, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
273 PINCFG(PFF2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]274 PINCFG(CORE_PWR_REQ, PWRON, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]275 PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
276 PINCFG(PWR_INT_N, PMI, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
277 PINCFG(RESET_OUT_N, RESET_OUT_N, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]278 PINCFG(CLK_32K_IN, CLK, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]279 PINCFG(JTAG_RTCK, RTCK, UP, NORMAL, OUTPUT, DEFAULT, DEFAULT),
280};
281
282#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
283 { \
284 .drvgrp = PMUX_DRVGRP_##_drvgrp, \
285 .slwf = _slwf, \
286 .slwr = _slwr, \
287 .drvup = _drvup, \
288 .drvdn = _drvdn, \
289 .lpmd = PMUX_LPMD_##_lpmd, \
290 .schmt = PMUX_SCHMT_##_schmt, \
291 .hsm = PMUX_HSM_##_hsm, \
292 }
293
294static const struct pmux_drvgrp_config jetson_tk1_drvgrps[] = {
295};
296
Stephen Warrenbbca7102016-04-21 16:03:37 -0600[diff] [blame]297#define MIPIPADCTRLCFG(_grp, _mux) \
298 { \
299 .grp = PMUX_MIPIPADCTRLGRP_##_grp, \
300 .func = PMUX_FUNC_##_mux, \
301 }
302
303static const struct pmux_mipipadctrlgrp_config jetson_tk1_mipipadctrlgrps[] = {
304 /* grp, mux */
305 MIPIPADCTRLCFG(DSI_B, DSI_B),
306};
307
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]308#endif /* PINMUX_CONFIG_JETSON_TK1_H */