blob: 07719e9265fde526677ee0a4ad275ac75908ac84 [file] [log] [blame]
Scott Wood96b8a052007-04-16 14:54:15 -05001/*
Scott Woode8d3ca82010-08-30 18:04:52 -05002 * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010.
Scott Wood96b8a052007-04-16 14:54:15 -05003 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02004 * SPDX-License-Identifier: GPL-2.0+
Scott Wood96b8a052007-04-16 14:54:15 -05005 */
6/*
7 * mpc8313epb board configuration file
8 */
9
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13/*
14 * High Level Configuration Options
15 */
16#define CONFIG_E300 1
Peter Tyser0f898602009-05-22 17:23:24 -050017#define CONFIG_MPC83xx 1
Peter Tyser2c7920a2009-05-22 17:23:25 -050018#define CONFIG_MPC831x 1
Scott Wood96b8a052007-04-16 14:54:15 -050019#define CONFIG_MPC8313 1
20#define CONFIG_MPC8313ERDB 1
21
Scott Wood22f44422012-12-06 13:33:18 +000022#ifdef CONFIG_NAND
23#define CONFIG_SPL
24#define CONFIG_SPL_INIT_MINIMAL
25#define CONFIG_SPL_SERIAL_SUPPORT
26#define CONFIG_SPL_NAND_SUPPORT
Scott Wood22f44422012-12-06 13:33:18 +000027#define CONFIG_SPL_FLUSH_IMAGE
28#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
29#define CONFIG_SPL_MPC83XX_WAIT_FOR_NAND
30
31#ifdef CONFIG_SPL_BUILD
32#define CONFIG_NS16550_MIN_FUNCTIONS
33#endif
34
35#define CONFIG_SYS_TEXT_BASE 0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */
36#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
37#define CONFIG_SPL_MAX_SIZE (4 * 1024)
Benoît Thébaudeau6113d3f2013-04-11 09:35:49 +000038#define CONFIG_SPL_PAD_TO 0x4000
Scott Wood22f44422012-12-06 13:33:18 +000039
Scott Woodf1c574d2010-11-24 13:28:40 +000040#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
41#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
42#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
43#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
44#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
45#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
46
Scott Wood22f44422012-12-06 13:33:18 +000047#ifdef CONFIG_SPL_BUILD
Scott Woodf1c574d2010-11-24 13:28:40 +000048#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
Scott Wood22f44422012-12-06 13:33:18 +000049#endif
50
51#endif /* CONFIG_NAND */
Scott Woodf1c574d2010-11-24 13:28:40 +000052
Wolfgang Denk2ae18242010-10-06 09:05:45 +020053#ifndef CONFIG_SYS_TEXT_BASE
54#define CONFIG_SYS_TEXT_BASE 0xFE000000
55#endif
56
Scott Woodf1c574d2010-11-24 13:28:40 +000057#ifndef CONFIG_SYS_MONITOR_BASE
58#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
59#endif
60
Scott Wood96b8a052007-04-16 14:54:15 -050061#define CONFIG_PCI
Gabor Juhos842033e2013-05-30 07:06:12 +000062#define CONFIG_PCI_INDIRECT_BRIDGE
Becky Bruce0914f482010-06-17 11:37:18 -050063#define CONFIG_FSL_ELBC 1
Scott Wood96b8a052007-04-16 14:54:15 -050064
Timur Tabi89c77842008-02-08 13:15:55 -060065#define CONFIG_MISC_INIT_R
66
67/*
68 * On-board devices
York Sun4ce1e232008-05-15 15:26:27 -050069 *
70 * TSEC1 is VSC switch
71 * TSEC2 is SoC TSEC
Timur Tabi89c77842008-02-08 13:15:55 -060072 */
73#define CONFIG_VSC7385_ENET
York Sun4ce1e232008-05-15 15:26:27 -050074#define CONFIG_TSEC2
Timur Tabi89c77842008-02-08 13:15:55 -060075
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020076#ifdef CONFIG_SYS_66MHZ
Kim Phillips5c5d3242007-04-25 12:34:38 -050077#define CONFIG_83XX_CLKIN 66666667 /* in Hz */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020078#elif defined(CONFIG_SYS_33MHZ)
Kim Phillips5c5d3242007-04-25 12:34:38 -050079#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
Scott Wood96b8a052007-04-16 14:54:15 -050080#else
81#error Unknown oscillator frequency.
82#endif
83
84#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
85
Joe Hershberger0eaf8f92011-11-11 15:55:38 -060086#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f */
87#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r */
Scott Wood96b8a052007-04-16 14:54:15 -050088
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020089#define CONFIG_SYS_IMMR 0xE0000000
Scott Wood96b8a052007-04-16 14:54:15 -050090
Scott Wood22f44422012-12-06 13:33:18 +000091#if defined(CONFIG_NAND) && !defined(CONFIG_SPL_BUILD)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020092#define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR
Scott Woode4c09502008-06-30 14:13:28 -050093#endif
94
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020095#define CONFIG_SYS_MEMTEST_START 0x00001000
96#define CONFIG_SYS_MEMTEST_END 0x07f00000
Scott Wood96b8a052007-04-16 14:54:15 -050097
98/* Early revs of this board will lock up hard when attempting
99 * to access the PMC registers, unless a JTAG debugger is
100 * connected, or some resistor modifications are made.
101 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200102#define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
Scott Wood96b8a052007-04-16 14:54:15 -0500103
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
105#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
Scott Wood96b8a052007-04-16 14:54:15 -0500106
107/*
Timur Tabi89c77842008-02-08 13:15:55 -0600108 * Device configurations
109 */
110
111/* Vitesse 7385 */
112
113#ifdef CONFIG_VSC7385_ENET
114
York Sun4ce1e232008-05-15 15:26:27 -0500115#define CONFIG_TSEC1
Timur Tabi89c77842008-02-08 13:15:55 -0600116
117/* The flash address and size of the VSC7385 firmware image */
118#define CONFIG_VSC7385_IMAGE 0xFE7FE000
119#define CONFIG_VSC7385_IMAGE_SIZE 8192
120
121#endif
122
123/*
Scott Wood96b8a052007-04-16 14:54:15 -0500124 * DDR Setup
125 */
Joe Hershberger261c07b2011-10-11 23:57:10 -0500126#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
128#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
Scott Wood96b8a052007-04-16 14:54:15 -0500129
130/*
131 * Manually set up DDR parameters, as this board does not
132 * seem to have the SPD connected to I2C.
133 */
Joe Hershberger261c07b2011-10-11 23:57:10 -0500134#define CONFIG_SYS_DDR_SIZE 128 /* MB */
Joe Hershberger2e651b22011-10-11 23:57:31 -0500135#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
Joe Hershberger2fef4022011-10-11 23:57:29 -0500136 | CSCONFIG_ODT_RD_NEVER \
137 | CSCONFIG_ODT_WR_ONLY_CURRENT \
Joe Hershberger261c07b2011-10-11 23:57:10 -0500138 | CSCONFIG_ROW_BIT_13 \
139 | CSCONFIG_COL_BIT_10)
Poonam Aggrwale1d8ed22008-01-14 09:41:14 +0530140 /* 0x80010102 */
Scott Wood96b8a052007-04-16 14:54:15 -0500141
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#define CONFIG_SYS_DDR_TIMING_3 0x00000000
Joe Hershberger261c07b2011-10-11 23:57:10 -0500143#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
144 | (0 << TIMING_CFG0_WRT_SHIFT) \
145 | (0 << TIMING_CFG0_RRT_SHIFT) \
146 | (0 << TIMING_CFG0_WWT_SHIFT) \
147 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
148 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
149 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
150 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
Scott Wood96b8a052007-04-16 14:54:15 -0500151 /* 0x00220802 */
Joe Hershberger261c07b2011-10-11 23:57:10 -0500152#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
153 | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \
154 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
155 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
156 | (10 << TIMING_CFG1_REFREC_SHIFT) \
157 | (3 << TIMING_CFG1_WRREC_SHIFT) \
158 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
159 | (2 << TIMING_CFG1_WRTORD_SHIFT))
Poonam Aggrwale1d8ed22008-01-14 09:41:14 +0530160 /* 0x3835a322 */
Joe Hershberger261c07b2011-10-11 23:57:10 -0500161#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
162 | (5 << TIMING_CFG2_CPO_SHIFT) \
163 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
164 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
165 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
166 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
167 | (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
Poonam Aggrwale1d8ed22008-01-14 09:41:14 +0530168 /* 0x129048c6 */ /* P9-45,may need tuning */
Joe Hershberger261c07b2011-10-11 23:57:10 -0500169#define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \
170 | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
Poonam Aggrwale1d8ed22008-01-14 09:41:14 +0530171 /* 0x05100500 */
Scott Wood96b8a052007-04-16 14:54:15 -0500172#if defined(CONFIG_DDR_2T_TIMING)
Joe Hershberger261c07b2011-10-11 23:57:10 -0500173#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
Kim Phillipsbbea46f2007-08-16 22:52:48 -0500174 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
Joe Hershberger2fef4022011-10-11 23:57:29 -0500175 | SDRAM_CFG_DBW_32 \
176 | SDRAM_CFG_2T_EN)
177 /* 0x43088000 */
Scott Wood96b8a052007-04-16 14:54:15 -0500178#else
Joe Hershberger261c07b2011-10-11 23:57:10 -0500179#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
Kim Phillipsbbea46f2007-08-16 22:52:48 -0500180 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
Joe Hershberger2fef4022011-10-11 23:57:29 -0500181 | SDRAM_CFG_DBW_32)
Scott Wood96b8a052007-04-16 14:54:15 -0500182 /* 0x43080000 */
183#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184#define CONFIG_SYS_SDRAM_CFG2 0x00401000
Scott Wood96b8a052007-04-16 14:54:15 -0500185/* set burst length to 8 for 32-bit data path */
Joe Hershberger261c07b2011-10-11 23:57:10 -0500186#define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
187 | (0x0632 << SDRAM_MODE_SD_SHIFT))
Poonam Aggrwale1d8ed22008-01-14 09:41:14 +0530188 /* 0x44480632 */
Joe Hershberger261c07b2011-10-11 23:57:10 -0500189#define CONFIG_SYS_DDR_MODE_2 0x8000C000
Scott Wood96b8a052007-04-16 14:54:15 -0500190
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200191#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
Scott Wood96b8a052007-04-16 14:54:15 -0500192 /*0x02000000*/
Joe Hershberger261c07b2011-10-11 23:57:10 -0500193#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
Scott Wood96b8a052007-04-16 14:54:15 -0500194 | DDRCDR_PZ_NOMZ \
195 | DDRCDR_NZ_NOMZ \
Joe Hershberger261c07b2011-10-11 23:57:10 -0500196 | DDRCDR_M_ODR)
Scott Wood96b8a052007-04-16 14:54:15 -0500197
198/*
199 * FLASH on the Local Bus
200 */
Joe Hershberger261c07b2011-10-11 23:57:10 -0500201#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
202#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
Joe Hershberger261c07b2011-10-11 23:57:10 -0500204#define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */
205#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
206#define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
207#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */
Scott Wood96b8a052007-04-16 14:54:15 -0500208
Joe Hershberger261c07b2011-10-11 23:57:10 -0500209#define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500210 | BR_PS_16 /* 16 bit port */ \
211 | BR_MS_GPCM /* MSEL = GPCM */ \
212 | BR_V) /* valid */
213#define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
Scott Wood96b8a052007-04-16 14:54:15 -0500214 | OR_GPCM_XACS \
215 | OR_GPCM_SCY_9 \
216 | OR_GPCM_EHTR \
Joe Hershberger261c07b2011-10-11 23:57:10 -0500217 | OR_GPCM_EAD)
Scott Wood96b8a052007-04-16 14:54:15 -0500218 /* 0xFF006FF7 TODO SLOW 16 MB flash size */
Joe Hershberger261c07b2011-10-11 23:57:10 -0500219 /* window base at flash base */
220#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500221 /* 16 MB window size */
222#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB)
Scott Wood96b8a052007-04-16 14:54:15 -0500223
Joe Hershberger261c07b2011-10-11 23:57:10 -0500224#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
225#define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */
Scott Wood96b8a052007-04-16 14:54:15 -0500226
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
228#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Scott Wood96b8a052007-04-16 14:54:15 -0500229
Joe Hershberger261c07b2011-10-11 23:57:10 -0500230#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \
Scott Wood22f44422012-12-06 13:33:18 +0000231 !defined(CONFIG_SPL_BUILD)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232#define CONFIG_SYS_RAMBOOT
Scott Wood96b8a052007-04-16 14:54:15 -0500233#endif
234
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200235#define CONFIG_SYS_INIT_RAM_LOCK 1
Joe Hershberger261c07b2011-10-11 23:57:10 -0500236#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
237#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
Scott Wood96b8a052007-04-16 14:54:15 -0500238
Joe Hershberger261c07b2011-10-11 23:57:10 -0500239#define CONFIG_SYS_GBL_DATA_OFFSET \
240 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Scott Wood96b8a052007-04-16 14:54:15 -0500242
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
Joe Hershberger261c07b2011-10-11 23:57:10 -0500244#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
245#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
Scott Wood96b8a052007-04-16 14:54:15 -0500246
247/*
248 * Local Bus LCRR and LBCR regs
249 */
Kim Phillipsc7190f02009-09-25 18:19:44 -0500250#define CONFIG_SYS_LCRR_EADC LCRR_EADC_1
251#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
Joe Hershberger261c07b2011-10-11 23:57:10 -0500252#define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \
253 | (0xFF << LBCR_BMT_SHIFT) \
254 | 0xF) /* 0x0004ff0f */
Scott Wood96b8a052007-04-16 14:54:15 -0500255
Joe Hershberger261c07b2011-10-11 23:57:10 -0500256 /* LB refresh timer prescal, 266MHz/32 */
257#define CONFIG_SYS_LBC_MRTPR 0x20000000 /*TODO */
Scott Wood96b8a052007-04-16 14:54:15 -0500258
Marcel Ziswiler7817cb22007-12-30 03:30:46 +0100259/* drivers/mtd/nand/nand.c */
Scott Wood22f44422012-12-06 13:33:18 +0000260#if defined(CONFIG_NAND) && defined(CONFIG_SPL_BUILD)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200261#define CONFIG_SYS_NAND_BASE 0xFFF00000
Scott Woode4c09502008-06-30 14:13:28 -0500262#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200263#define CONFIG_SYS_NAND_BASE 0xE2800000
Scott Woode4c09502008-06-30 14:13:28 -0500264#endif
265
Scott Woode8d3ca82010-08-30 18:04:52 -0500266#define CONFIG_MTD_DEVICE
267#define CONFIG_MTD_PARTITION
268#define CONFIG_CMD_MTDPARTS
269#define MTDIDS_DEFAULT "nand0=e2800000.flash"
Joe Hershberger261c07b2011-10-11 23:57:10 -0500270#define MTDPARTS_DEFAULT \
Scott Woodc947c122012-01-04 16:48:26 -0600271 "mtdparts=e2800000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)"
Scott Woode8d3ca82010-08-30 18:04:52 -0500272
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200273#define CONFIG_SYS_MAX_NAND_DEVICE 1
Scott Wood96b8a052007-04-16 14:54:15 -0500274#define CONFIG_MTD_NAND_VERIFY_WRITE
Scott Woodacdab5c2008-06-26 14:06:52 -0500275#define CONFIG_CMD_NAND 1
276#define CONFIG_NAND_FSL_ELBC 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200277#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500278#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
Scott Wood96b8a052007-04-16 14:54:15 -0500279
Scott Woode4c09502008-06-30 14:13:28 -0500280
Joe Hershberger261c07b2011-10-11 23:57:10 -0500281#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500282 | BR_DECC_CHK_GEN /* Use HW ECC */ \
Joe Hershberger261c07b2011-10-11 23:57:10 -0500283 | BR_PS_8 /* 8 bit port */ \
Wolfgang Denka7676ea2007-05-16 01:16:53 +0200284 | BR_MS_FCM /* MSEL = FCM */ \
Joe Hershberger261c07b2011-10-11 23:57:10 -0500285 | BR_V) /* valid */
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500286#define CONFIG_SYS_NAND_OR_PRELIM \
287 (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
Scott Wood96b8a052007-04-16 14:54:15 -0500288 | OR_FCM_CSCT \
289 | OR_FCM_CST \
290 | OR_FCM_CHT \
291 | OR_FCM_SCY_1 \
292 | OR_FCM_TRLX \
Joe Hershberger261c07b2011-10-11 23:57:10 -0500293 | OR_FCM_EHTR)
Scott Wood96b8a052007-04-16 14:54:15 -0500294 /* 0xFFFF8396 */
Scott Woode4c09502008-06-30 14:13:28 -0500295
Scott Wood22f44422012-12-06 13:33:18 +0000296#ifdef CONFIG_NAND
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200297#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
298#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
299#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM
300#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM
Scott Woode4c09502008-06-30 14:13:28 -0500301#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200302#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
303#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
304#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
305#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
Scott Woode4c09502008-06-30 14:13:28 -0500306#endif
307
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200308#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500309#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
Scott Wood96b8a052007-04-16 14:54:15 -0500310
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200311#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
312#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
Scott Woode4c09502008-06-30 14:13:28 -0500313
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500314/* local bus write LED / read status buffer (BCSR) mapping */
315#define CONFIG_SYS_BCSR_ADDR 0xFA000000
316#define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */
317 /* map at 0xFA000000 on LCS3 */
318#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_BCSR_ADDR \
319 | BR_PS_8 /* 8 bit port */ \
320 | BR_MS_GPCM /* MSEL = GPCM */ \
321 | BR_V) /* valid */
322 /* 0xFA000801 */
323#define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BCSR_SIZE) \
324 | OR_GPCM_CSNT \
325 | OR_GPCM_ACS_DIV2 \
326 | OR_GPCM_XACS \
327 | OR_GPCM_SCY_15 \
328 | OR_GPCM_TRLX_SET \
329 | OR_GPCM_EHTR_SET \
330 | OR_GPCM_EAD)
331 /* 0xFFFF8FF7 */
332#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_BCSR_ADDR
333#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
Scott Wood96b8a052007-04-16 14:54:15 -0500334
Timur Tabi89c77842008-02-08 13:15:55 -0600335/* Vitesse 7385 */
336
Timur Tabi89c77842008-02-08 13:15:55 -0600337#ifdef CONFIG_VSC7385_ENET
338
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500339 /* VSC7385 Base address on LCS2 */
340#define CONFIG_SYS_VSC7385_BASE 0xF0000000
341#define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */
342
343#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \
344 | BR_PS_8 /* 8 bit port */ \
345 | BR_MS_GPCM /* MSEL = GPCM */ \
346 | BR_V) /* valid */
347#define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \
348 | OR_GPCM_CSNT \
349 | OR_GPCM_XACS \
350 | OR_GPCM_SCY_15 \
351 | OR_GPCM_SETA \
352 | OR_GPCM_TRLX_SET \
353 | OR_GPCM_EHTR_SET \
354 | OR_GPCM_EAD)
355 /* 0xFFFE09FF */
356
Joe Hershberger261c07b2011-10-11 23:57:10 -0500357 /* Access window base at VSC7385 base */
358#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500359#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB)
Timur Tabi89c77842008-02-08 13:15:55 -0600360
361#endif
362
Scott Wood96b8a052007-04-16 14:54:15 -0500363/* pass open firmware flat tree */
Kim Phillips35cc4e42007-08-15 22:30:39 -0500364#define CONFIG_OF_LIBFDT 1
Scott Wood96b8a052007-04-16 14:54:15 -0500365#define CONFIG_OF_BOARD_SETUP 1
Kim Phillips5b8bc602007-12-20 14:09:22 -0600366#define CONFIG_OF_STDOUT_VIA_ALIAS 1
Scott Wood96b8a052007-04-16 14:54:15 -0500367
Joe Hershberger0eaf8f92011-11-11 15:55:38 -0600368#define CONFIG_MPC83XX_GPIO 1
369#define CONFIG_CMD_GPIO 1
370
Scott Wood96b8a052007-04-16 14:54:15 -0500371/*
372 * Serial Port
373 */
374#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200375#define CONFIG_SYS_NS16550
376#define CONFIG_SYS_NS16550_SERIAL
377#define CONFIG_SYS_NS16550_REG_SIZE 1
Scott Wood96b8a052007-04-16 14:54:15 -0500378
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200379#define CONFIG_SYS_BAUDRATE_TABLE \
Scott Wood96b8a052007-04-16 14:54:15 -0500380 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
381
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200382#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
383#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
Scott Wood96b8a052007-04-16 14:54:15 -0500384
385/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200386#define CONFIG_SYS_HUSH_PARSER
Scott Wood96b8a052007-04-16 14:54:15 -0500387
388/* I2C */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200389#define CONFIG_SYS_I2C
390#define CONFIG_SYS_I2C_FSL
391#define CONFIG_SYS_FSL_I2C_SPEED 400000
392#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
393#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
394#define CONFIG_SYS_FSL_I2C2_SPEED 400000
395#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
396#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
397#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
Scott Wood96b8a052007-04-16 14:54:15 -0500398
Scott Wood96b8a052007-04-16 14:54:15 -0500399/*
400 * General PCI
401 * Addresses are mapped 1-1.
402 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200403#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
404#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
405#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
406#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
407#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
408#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
409#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
410#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
411#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
Scott Wood96b8a052007-04-16 14:54:15 -0500412
413#define CONFIG_PCI_PNP /* do pci plug-and-play */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200414#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
Scott Wood96b8a052007-04-16 14:54:15 -0500415
416/*
Timur Tabi89c77842008-02-08 13:15:55 -0600417 * TSEC
Scott Wood96b8a052007-04-16 14:54:15 -0500418 */
419#define CONFIG_TSEC_ENET /* TSEC ethernet support */
420
Timur Tabi89c77842008-02-08 13:15:55 -0600421#define CONFIG_GMII /* MII PHY management */
422
423#ifdef CONFIG_TSEC1
424#define CONFIG_HAS_ETH0
425#define CONFIG_TSEC1_NAME "TSEC0"
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200426#define CONFIG_SYS_TSEC1_OFFSET 0x24000
Timur Tabi89c77842008-02-08 13:15:55 -0600427#define TSEC1_PHY_ADDR 0x1c
428#define TSEC1_FLAGS TSEC_GIGABIT
429#define TSEC1_PHYIDX 0
Scott Wood96b8a052007-04-16 14:54:15 -0500430#endif
431
Timur Tabi89c77842008-02-08 13:15:55 -0600432#ifdef CONFIG_TSEC2
433#define CONFIG_HAS_ETH1
Kim Phillips255a35772007-05-16 16:52:19 -0500434#define CONFIG_TSEC2_NAME "TSEC1"
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200435#define CONFIG_SYS_TSEC2_OFFSET 0x25000
Timur Tabi89c77842008-02-08 13:15:55 -0600436#define TSEC2_PHY_ADDR 4
437#define TSEC2_FLAGS TSEC_GIGABIT
438#define TSEC2_PHYIDX 0
439#endif
440
Scott Wood96b8a052007-04-16 14:54:15 -0500441
442/* Options are: TSEC[0-1] */
443#define CONFIG_ETHPRIME "TSEC1"
444
445/*
446 * Configure on-board RTC
447 */
448#define CONFIG_RTC_DS1337
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200449#define CONFIG_SYS_I2C_RTC_ADDR 0x68
Scott Wood96b8a052007-04-16 14:54:15 -0500450
451/*
452 * Environment
453 */
Scott Wood22f44422012-12-06 13:33:18 +0000454#if defined(CONFIG_NAND)
Jean-Christophe PLAGNIOL-VILLARD51bfee12008-09-10 22:47:58 +0200455 #define CONFIG_ENV_IS_IN_NAND 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200456 #define CONFIG_ENV_OFFSET (512 * 1024)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200457 #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200458 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
459 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
460 #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4)
Joe Hershberger261c07b2011-10-11 23:57:10 -0500461 #define CONFIG_ENV_OFFSET_REDUND \
462 (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200463#elif !defined(CONFIG_SYS_RAMBOOT)
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200464 #define CONFIG_ENV_IS_IN_FLASH 1
Joe Hershberger261c07b2011-10-11 23:57:10 -0500465 #define CONFIG_ENV_ADDR \
466 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200467 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
468 #define CONFIG_ENV_SIZE 0x2000
Scott Wood96b8a052007-04-16 14:54:15 -0500469
470/* Address and size of Redundant Environment Sector */
471#else
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200472 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200473 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200474 #define CONFIG_ENV_SIZE 0x2000
Scott Wood96b8a052007-04-16 14:54:15 -0500475#endif
476
477#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200478#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Scott Wood96b8a052007-04-16 14:54:15 -0500479
Jon Loeliger8ea54992007-07-04 22:30:06 -0500480/*
Jon Loeliger079a1362007-07-10 10:12:10 -0500481 * BOOTP options
482 */
483#define CONFIG_BOOTP_BOOTFILESIZE
484#define CONFIG_BOOTP_BOOTPATH
485#define CONFIG_BOOTP_GATEWAY
486#define CONFIG_BOOTP_HOSTNAME
487
488
489/*
Jon Loeliger8ea54992007-07-04 22:30:06 -0500490 * Command line configuration.
491 */
492#include <config_cmd_default.h>
493
494#define CONFIG_CMD_PING
495#define CONFIG_CMD_DHCP
496#define CONFIG_CMD_I2C
497#define CONFIG_CMD_MII
498#define CONFIG_CMD_DATE
499#define CONFIG_CMD_PCI
500
Scott Wood22f44422012-12-06 13:33:18 +0000501#if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND)
Mike Frysingerbdab39d2009-01-28 19:08:14 -0500502 #undef CONFIG_CMD_SAVEENV
Jon Loeliger8ea54992007-07-04 22:30:06 -0500503 #undef CONFIG_CMD_LOADS
504#endif
Scott Wood96b8a052007-04-16 14:54:15 -0500505
506#define CONFIG_CMDLINE_EDITING 1
Kim Phillipsa059e902010-04-15 17:36:05 -0500507#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Scott Wood96b8a052007-04-16 14:54:15 -0500508
509/*
510 * Miscellaneous configurable options
511 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200512#define CONFIG_SYS_LONGHELP /* undef to save memory */
513#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200514#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Scott Wood96b8a052007-04-16 14:54:15 -0500515
Joe Hershberger261c07b2011-10-11 23:57:10 -0500516 /* Print Buffer Size */
517#define CONFIG_SYS_PBSIZE \
518 (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
519#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
520 /* Boot Argument Buffer Size */
521#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
Scott Wood96b8a052007-04-16 14:54:15 -0500522
523/*
524 * For booting Linux, the board info and command line data
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700525 * have to be in the first 256 MB of memory, since this is
Scott Wood96b8a052007-04-16 14:54:15 -0500526 * the maximum mapped by the Linux kernel during initialization.
527 */
Joe Hershberger261c07b2011-10-11 23:57:10 -0500528 /* Initial Memory map for Linux*/
529#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
Scott Wood96b8a052007-04-16 14:54:15 -0500530
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200531#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
Scott Wood96b8a052007-04-16 14:54:15 -0500532
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200533#ifdef CONFIG_SYS_66MHZ
Scott Wood96b8a052007-04-16 14:54:15 -0500534
535/* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */
536/* 0x62040000 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200537#define CONFIG_SYS_HRCW_LOW (\
Scott Wood96b8a052007-04-16 14:54:15 -0500538 0x20000000 /* reserved, must be set */ |\
539 HRCWL_DDRCM |\
540 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
541 HRCWL_DDR_TO_SCB_CLK_2X1 |\
542 HRCWL_CSB_TO_CLKIN_2X1 |\
543 HRCWL_CORE_TO_CSB_2X1)
544
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200545#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
Scott Woode4c09502008-06-30 14:13:28 -0500546
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200547#elif defined(CONFIG_SYS_33MHZ)
Scott Wood96b8a052007-04-16 14:54:15 -0500548
549/* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */
550/* 0x65040000 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200551#define CONFIG_SYS_HRCW_LOW (\
Scott Wood96b8a052007-04-16 14:54:15 -0500552 0x20000000 /* reserved, must be set */ |\
553 HRCWL_DDRCM |\
554 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
555 HRCWL_DDR_TO_SCB_CLK_2X1 |\
556 HRCWL_CSB_TO_CLKIN_5X1 |\
557 HRCWL_CORE_TO_CSB_2X1)
558
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200559#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5)
Scott Woode4c09502008-06-30 14:13:28 -0500560
Scott Wood96b8a052007-04-16 14:54:15 -0500561#endif
562
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200563#define CONFIG_SYS_HRCW_HIGH_BASE (\
Scott Wood96b8a052007-04-16 14:54:15 -0500564 HRCWH_PCI_HOST |\
565 HRCWH_PCI1_ARBITER_ENABLE |\
566 HRCWH_CORE_ENABLE |\
Scott Wood96b8a052007-04-16 14:54:15 -0500567 HRCWH_BOOTSEQ_DISABLE |\
568 HRCWH_SW_WATCHDOG_DISABLE |\
Scott Wood96b8a052007-04-16 14:54:15 -0500569 HRCWH_TSEC1M_IN_RGMII |\
570 HRCWH_TSEC2M_IN_RGMII |\
Scott Woode4c09502008-06-30 14:13:28 -0500571 HRCWH_BIG_ENDIAN)
572
Scott Wood22f44422012-12-06 13:33:18 +0000573#ifdef CONFIG_NAND
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200574#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
Wolfgang Denk4b070802008-08-14 14:41:06 +0200575 HRCWH_FROM_0XFFF00100 |\
576 HRCWH_ROM_LOC_NAND_SP_8BIT |\
577 HRCWH_RL_EXT_NAND)
Scott Woode4c09502008-06-30 14:13:28 -0500578#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200579#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
Wolfgang Denk4b070802008-08-14 14:41:06 +0200580 HRCWH_FROM_0X00000100 |\
581 HRCWH_ROM_LOC_LOCAL_16BIT |\
582 HRCWH_RL_EXT_LEGACY)
Scott Woode4c09502008-06-30 14:13:28 -0500583#endif
Scott Wood96b8a052007-04-16 14:54:15 -0500584
585/* System IO Config */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200586#define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */
Joe Hershberger0eaf8f92011-11-11 15:55:38 -0600587 /* Enable Internal USB Phy and GPIO on LCD Connector */
588#define CONFIG_SYS_SICRL (SICRL_USBDR_10 | SICRL_LBC)
Scott Wood96b8a052007-04-16 14:54:15 -0500589
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200590#define CONFIG_SYS_HID0_INIT 0x000000000
591#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
Kim Phillips1a2e2032010-04-20 19:37:54 -0500592 HID0_ENABLE_INSTRUCTION_CACHE | \
593 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
Scott Wood96b8a052007-04-16 14:54:15 -0500594
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200595#define CONFIG_SYS_HID2 HID2_HBE
Scott Wood96b8a052007-04-16 14:54:15 -0500596
Becky Bruce31d82672008-05-08 19:02:12 -0500597#define CONFIG_HIGH_BATS 1 /* High BATs supported */
598
Scott Wood96b8a052007-04-16 14:54:15 -0500599/* DDR @ 0x00000000 */
Joe Hershberger72cd4082011-10-11 23:57:28 -0500600#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW)
Joe Hershberger261c07b2011-10-11 23:57:10 -0500601#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
602 | BATU_BL_256M \
603 | BATU_VS \
604 | BATU_VP)
Scott Wood96b8a052007-04-16 14:54:15 -0500605
606/* PCI @ 0x80000000 */
Joe Hershberger72cd4082011-10-11 23:57:28 -0500607#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW)
Joe Hershberger261c07b2011-10-11 23:57:10 -0500608#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
609 | BATU_BL_256M \
610 | BATU_VS \
611 | BATU_VP)
612#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500613 | BATL_PP_RW \
Joe Hershberger261c07b2011-10-11 23:57:10 -0500614 | BATL_CACHEINHIBIT \
615 | BATL_GUARDEDSTORAGE)
616#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
617 | BATU_BL_256M \
618 | BATU_VS \
619 | BATU_VP)
Scott Wood96b8a052007-04-16 14:54:15 -0500620
621/* PCI2 not supported on 8313 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200622#define CONFIG_SYS_IBAT3L (0)
623#define CONFIG_SYS_IBAT3U (0)
624#define CONFIG_SYS_IBAT4L (0)
625#define CONFIG_SYS_IBAT4U (0)
Scott Wood96b8a052007-04-16 14:54:15 -0500626
627/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
Joe Hershberger261c07b2011-10-11 23:57:10 -0500628#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500629 | BATL_PP_RW \
Joe Hershberger261c07b2011-10-11 23:57:10 -0500630 | BATL_CACHEINHIBIT \
631 | BATL_GUARDEDSTORAGE)
632#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
633 | BATU_BL_256M \
634 | BATU_VS \
635 | BATU_VP)
Scott Wood96b8a052007-04-16 14:54:15 -0500636
637/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
Joe Hershberger72cd4082011-10-11 23:57:28 -0500638#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200639#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
Scott Wood96b8a052007-04-16 14:54:15 -0500640
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200641#define CONFIG_SYS_IBAT7L (0)
642#define CONFIG_SYS_IBAT7U (0)
Scott Wood96b8a052007-04-16 14:54:15 -0500643
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200644#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
645#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
646#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
647#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
648#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
649#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
650#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
651#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
652#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
653#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
654#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
655#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
656#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
657#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
658#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
659#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Scott Wood96b8a052007-04-16 14:54:15 -0500660
661/*
Scott Wood96b8a052007-04-16 14:54:15 -0500662 * Environment Configuration
663 */
664#define CONFIG_ENV_OVERWRITE
665
Joe Hershberger261c07b2011-10-11 23:57:10 -0500666#define CONFIG_NETDEV "eth1"
Scott Wood96b8a052007-04-16 14:54:15 -0500667
668#define CONFIG_HOSTNAME mpc8313erdb
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000669#define CONFIG_ROOTPATH "/nfs/root/path"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000670#define CONFIG_BOOTFILE "uImage"
Joe Hershberger261c07b2011-10-11 23:57:10 -0500671 /* U-Boot image on TFTP server */
672#define CONFIG_UBOOTPATH "u-boot.bin"
673#define CONFIG_FDTFILE "mpc8313erdb.dtb"
Scott Wood96b8a052007-04-16 14:54:15 -0500674
Joe Hershberger261c07b2011-10-11 23:57:10 -0500675 /* default location for tftp and bootm */
676#define CONFIG_LOADADDR 800000
Kim Phillips7fd0bea2008-09-24 08:46:25 -0500677#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
Scott Wood96b8a052007-04-16 14:54:15 -0500678#define CONFIG_BAUDRATE 115200
679
Scott Wood96b8a052007-04-16 14:54:15 -0500680#define CONFIG_EXTRA_ENV_SETTINGS \
Joe Hershberger261c07b2011-10-11 23:57:10 -0500681 "netdev=" CONFIG_NETDEV "\0" \
Scott Wood96b8a052007-04-16 14:54:15 -0500682 "ethprime=TSEC1\0" \
Joe Hershberger261c07b2011-10-11 23:57:10 -0500683 "uboot=" CONFIG_UBOOTPATH "\0" \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200684 "tftpflash=tftpboot $loadaddr $uboot; " \
Marek Vasut5368c552012-09-23 17:41:24 +0200685 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
686 " +$filesize; " \
687 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
688 " +$filesize; " \
689 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
690 " $filesize; " \
691 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
692 " +$filesize; " \
693 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
694 " $filesize\0" \
Kim Phillips79f516b2009-08-21 16:34:38 -0500695 "fdtaddr=780000\0" \
Joe Hershberger261c07b2011-10-11 23:57:10 -0500696 "fdtfile=" CONFIG_FDTFILE "\0" \
Scott Wood96b8a052007-04-16 14:54:15 -0500697 "console=ttyS0\0" \
698 "setbootargs=setenv bootargs " \
699 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200700 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
Joe Hershberger261c07b2011-10-11 23:57:10 -0500701 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
702 "$netdev:off " \
Scott Wood96b8a052007-04-16 14:54:15 -0500703 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
704
705#define CONFIG_NFSBOOTCOMMAND \
706 "setenv rootdev /dev/nfs;" \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200707 "run setbootargs;" \
708 "run setipargs;" \
Scott Wood96b8a052007-04-16 14:54:15 -0500709 "tftp $loadaddr $bootfile;" \
710 "tftp $fdtaddr $fdtfile;" \
711 "bootm $loadaddr - $fdtaddr"
712
713#define CONFIG_RAMBOOTCOMMAND \
714 "setenv rootdev /dev/ram;" \
715 "run setbootargs;" \
716 "tftp $ramdiskaddr $ramdiskfile;" \
717 "tftp $loadaddr $bootfile;" \
718 "tftp $fdtaddr $fdtfile;" \
719 "bootm $loadaddr $ramdiskaddr $fdtaddr"
720
Scott Wood96b8a052007-04-16 14:54:15 -0500721#endif /* __CONFIG_H */