blob: 92b4fa503efedda4ca4a79ad84ce84ee524092be [file] [log] [blame]
Wolfgang Denkb87dfd22006-07-19 13:50:38 +02001/*
2 * (C) Copyright 2003-2006
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2004-2006
6 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
30/*
31 * High Level Configuration Options
32 * (easy to change)
33 */
34
35#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
36#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
37#define CONFIG_TQM5200 1 /* ... on TQM5200 module */
38#define CONFIG_TB5200 1 /* ... on a TB5200 base board */
39
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020040#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
Wolfgang Denkb87dfd22006-07-19 13:50:38 +020041
42#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
43#define BOOTFLAG_WARM 0x02 /* Software reboot */
44
Becky Bruce31d82672008-05-08 19:02:12 -050045#define CONFIG_HIGH_BATS 1 /* High BATs supported */
46
Wolfgang Denkb87dfd22006-07-19 13:50:38 +020047/*
48 * Serial console configuration
49 */
50#define CONFIG_PSC_CONSOLE 1 /* default console is on PSC1 */
51#define CONFIG_SERIAL_MULTI 1 /* support multiple consoles */
52#define CONFIG_PSC_CONSOLE2 6 /* second console is on PSC6 */
53#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020054#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
Wolfgang Denkb87dfd22006-07-19 13:50:38 +020055
56/*
57 * Video console
58 */
59#if 1
60#define CONFIG_VIDEO
61#define CONFIG_VIDEO_SM501
62#define CONFIG_VIDEO_SM501_32BPP
63#define CONFIG_CFB_CONSOLE
64#define CONFIG_VIDEO_LOGO
65#define CONFIG_VGA_AS_SINGLE_DEVICE
66#define CONFIG_CONSOLE_EXTRA_INFO
67#define CONFIG_VIDEO_SW_CURSOR
68#define CONFIG_SPLASH_SCREEN
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020069#define CONFIG_SYS_CONSOLE_IS_IN_ENV
Wolfgang Denkb87dfd22006-07-19 13:50:38 +020070#endif
71
Wolfgang Denkb87dfd22006-07-19 13:50:38 +020072/* Partitions */
73#define CONFIG_MAC_PARTITION
74#define CONFIG_DOS_PARTITION
75#define CONFIG_ISO_PARTITION
76
77/* USB */
78#define CONFIG_USB_OHCI
Wolfgang Denkb87dfd22006-07-19 13:50:38 +020079#define CONFIG_USB_STORAGE
80
81/* POST support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020082#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
83 CONFIG_SYS_POST_CPU | \
84 CONFIG_SYS_POST_I2C)
Wolfgang Denkb87dfd22006-07-19 13:50:38 +020085
86#ifdef CONFIG_POST
Wolfgang Denkb87dfd22006-07-19 13:50:38 +020087/* preserve space for the post_word at end of on-chip SRAM */
88#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
Wolfgang Denkb87dfd22006-07-19 13:50:38 +020089#endif
90
Wolfgang Denkb87dfd22006-07-19 13:50:38 +020091
92/*
Jon Loeligera1aa0bb2007-07-10 09:22:23 -050093 * BOOTP options
94 */
95#define CONFIG_BOOTP_BOOTFILESIZE
96#define CONFIG_BOOTP_BOOTPATH
97#define CONFIG_BOOTP_GATEWAY
98#define CONFIG_BOOTP_HOSTNAME
99
100
101/*
Jon Loeligerd794cfe2007-07-04 22:31:15 -0500102 * Command line configuration.
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200103 */
Jon Loeligerd794cfe2007-07-04 22:31:15 -0500104#include <config_cmd_default.h>
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200105
Jon Loeligerd794cfe2007-07-04 22:31:15 -0500106#define CONFIG_CMD_ASKENV
107#define CONFIG_CMD_DATE
108#define CONFIG_CMD_DHCP
109#define CONFIG_CMD_ECHO
110#define CONFIG_CMD_EEPROM
111#define CONFIG_CMD_EXT2
112#define CONFIG_CMD_FAT
113#define CONFIG_CMD_I2C
114#define CONFIG_CMD_IDE
115#define CONFIG_CMD_JFFS2
116#define CONFIG_CMD_MII
117#define CONFIG_CMD_NFS
118#define CONFIG_CMD_PING
Jon Loeligerd794cfe2007-07-04 22:31:15 -0500119#define CONFIG_CMD_REGINFO
120#define CONFIG_CMD_SNTP
121#define CONFIG_CMD_BSP
122#define CONFIG_CMD_USB
123
Jon Loeligeraf075ee2007-07-08 17:02:01 -0500124#ifdef CONFIG_VIDEO
125#define CONFIG_CMD_BMP
126#endif
127
128#ifdef CONFIG_POST
129#define CONFIG__CMD_DIAG
130#endif
131
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200132
133#define CONFIG_TIMESTAMP /* display image timestamps */
134
135#if (TEXT_BASE == 0xFC000000) /* Boot low */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136# define CONFIG_SYS_LOWBOOT 1
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200137#endif
138
139/*
140 * Autobooting
141 */
142#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
143
144#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +0100145 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200146 "echo"
147
148#undef CONFIG_BOOTARGS
149
Wolfgang Denk45a212c2006-07-19 17:52:30 +0200150#if defined(CONFIG_TQM5200_B)
151#define CONFIG_EXTRA_ENV_SETTINGS \
152 "netdev=eth0\0" \
153 "rootpath=/opt/eldk/ppc_6xx\0" \
154 "ramargs=setenv bootargs root=/dev/ram rw\0" \
155 "nfsargs=setenv bootargs root=/dev/nfs rw " \
156 "nfsroot=${serverip}:${rootpath}\0" \
157 "addip=setenv bootargs ${bootargs} " \
158 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
159 ":${hostname}:${netdev}:off panic=1\0" \
160 "flash_self=run ramargs addip;" \
161 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
162 "flash_nfs=run nfsargs addip;" \
163 "bootm ${kernel_addr}\0" \
164 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
165 "bootfile=/tftpboot/tqm5200/uImage\0" \
166 "load=tftp 200000 ${u-boot}\0" \
167 "u-boot=/tftpboot/tqm5200/u-boot.bin\0" \
168 "update=protect off FC000000 FC07FFFF;" \
169 "erase FC000000 FC07FFFF;" \
170 "cp.b 200000 FC000000 ${filesize};" \
171 "protect on FC000000 FC07FFFF\0" \
172 ""
173#else
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200174#define CONFIG_EXTRA_ENV_SETTINGS \
175 "netdev=eth0\0" \
176 "rootpath=/opt/eldk/ppc_6xx\0" \
177 "ramargs=setenv bootargs root=/dev/ram rw\0" \
178 "nfsargs=setenv bootargs root=/dev/nfs rw " \
179 "nfsroot=${serverip}:${rootpath}\0" \
180 "addip=setenv bootargs ${bootargs} " \
181 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
182 ":${hostname}:${netdev}:off panic=1\0" \
183 "flash_self=run ramargs addip;" \
184 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
185 "flash_nfs=run nfsargs addip;" \
186 "bootm ${kernel_addr}\0" \
187 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
188 "bootfile=/tftpboot/tqm5200/uImage\0" \
189 "load=tftp 200000 $(u-boot)\0" \
190 "u-boot=/tftpboot/tqm5200/u-boot.bin\0" \
191 "update=protect off FC000000 FC05FFFF;" \
192 "erase FC000000 FC05FFFF;" \
193 "cp.b 200000 FC000000 ${filesize};" \
194 "protect on FC000000 FC05FFFF\0" \
195 ""
Wolfgang Denk45a212c2006-07-19 17:52:30 +0200196#endif /* CONFIG_TQM5200_B */
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200197
198#define CONFIG_BOOTCOMMAND "run net_nfs"
199
200/*
201 * IPB Bus clocking configuration.
202 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200204
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200206/*
207 * PCI Bus clocking configuration
208 *
209 * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210 * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
Bartlomiej Siekac99512d2007-05-27 16:53:43 +0200211 * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200212 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200214#endif
215
216/*
217 * I2C configuration
218 */
219#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #2 */
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200221
222/*
223 * I2C clock frequency
224 *
225 * Please notice, that the resulting clock frequency could differ from the
226 * configured value. This is because the I2C clock is derived from system
227 * clock over a frequency divider with only a few divider values. U-boot
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200228 * calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200229 * approximation allways lies below the configured value, never above.
230 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200231#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
232#define CONFIG_SYS_I2C_SLAVE 0x7F
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200233
234/*
235 * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
236 * also). For other EEPROMs configuration should be verified. On Mini-FAP the
237 * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
238 * same configuration could be used.
239 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200240#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
241#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
242#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
243#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200244
245/* List of I2C addresses to be verified by POST */
246#undef I2C_ADDR_LIST
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200247#define I2C_ADDR_LIST { CONFIG_SYS_I2C_EEPROM_ADDR, \
248 CONFIG_SYS_I2C_RTC_ADDR, \
249 CONFIG_SYS_I2C_SLAVE }
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200250
251/*
252 * Flash configuration
253 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#define CONFIG_SYS_FLASH_BASE TEXT_BASE /* 0xFC000000 */
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200255
Wolfgang Denk45a212c2006-07-19 17:52:30 +0200256/* use CFI flash driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200257#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200258#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200259#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START }
260#define CONFIG_SYS_FLASH_EMPTY_INFO
261#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MByte */
262#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
263#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200264
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200265#if !defined(CONFIG_SYS_LOWBOOT)
266#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00760000 + 0x00800000)
267#else /* CONFIG_SYS_LOWBOOT */
Wolfgang Denk45a212c2006-07-19 17:52:30 +0200268#if defined(CONFIG_TQM5200_B)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200269#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00080000)
Wolfgang Denk45a212c2006-07-19 17:52:30 +0200270#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200271#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000)
Wolfgang Denk45a212c2006-07-19 17:52:30 +0200272#endif /* CONFIG_TQM5200_B */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200273#endif /* CONFIG_SYS_LOWBOOT */
274#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200275 (= chip selects) */
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200276
277/* Dynamic MTD partition support */
Stefan Roese68d7d652009-03-19 13:30:36 +0100278#define CONFIG_CMD_MTDPARTS
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200279#define MTDIDS_DEFAULT "nor0=TQM5200-0"
Wolfgang Denk45a212c2006-07-19 17:52:30 +0200280#if defined(CONFIG_TQM5200_B)
281#define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:768k(firmware)," \
282 "1280k(kernel)," \
283 "2m(initrd)," \
284 "4m(small-fs)," \
285 "16m(big-fs)," \
286 "8m(misc)"
287#else
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200288#define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \
289 "1408k(kernel)," \
290 "2m(initrd)," \
291 "4m(small-fs)," \
292 "16m(big-fs)," \
293 "8m(misc)"
Wolfgang Denk45a212c2006-07-19 17:52:30 +0200294#endif /* CONFIG_TQM5200_B */
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200295
296/*
297 * Environment settings
298 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200299#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200300#define CONFIG_ENV_SIZE 0x10000
Wolfgang Denk45a212c2006-07-19 17:52:30 +0200301#if defined(CONFIG_TQM5200_B)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200302#define CONFIG_ENV_SECT_SIZE 0x40000
Wolfgang Denk45a212c2006-07-19 17:52:30 +0200303#else
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200304#define CONFIG_ENV_SECT_SIZE 0x20000
305#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
306#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Wolfgang Denk45a212c2006-07-19 17:52:30 +0200307#endif /* CONFIG_TQM5200_B */
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200308
309/*
310 * Memory map
311 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200312#define CONFIG_SYS_MBAR 0xF0000000
313#define CONFIG_SYS_SDRAM_BASE 0x00000000
314#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200315
316/* Use ON-Chip SRAM until RAM will be available */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200317#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200318#ifdef CONFIG_POST
319/* preserve space for the post_word at end of on-chip SRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200320#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200321#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200322#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200323#endif
324
325
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200326#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
327#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
328#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200329
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200330#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
331#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
332# define CONFIG_SYS_RAMBOOT 1
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200333#endif
334
Wolfgang Denk45a212c2006-07-19 17:52:30 +0200335#if defined(CONFIG_TQM5200_B)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200336#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
Wolfgang Denk45a212c2006-07-19 17:52:30 +0200337#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200338#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
Wolfgang Denk45a212c2006-07-19 17:52:30 +0200339#endif /* CONFIG_TQM5200_B */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200340#define CONFIG_SYS_MALLOC_LEN (1024 << 10) /* Reserve 1024 kB for malloc() */
341#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200342
343/*
344 * Ethernet configuration
345 */
346#define CONFIG_MPC5xxx_FEC 1
Ben Warren86321fc2009-02-05 23:58:25 -0800347#define CONFIG_MPC5xxx_FEC_MII100
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200348/*
Ben Warren86321fc2009-02-05 23:58:25 -0800349 * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200350 */
Ben Warren86321fc2009-02-05 23:58:25 -0800351/* #define CONFIG_MPC5xxx_FEC_MII10 */
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200352#define CONFIG_PHY_ADDR 0x00
353
354/*
355 * GPIO configuration
356 *
357 * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
358 * Bit 0 (mask: 0x80000000): 1
359 * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
360 * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
361 * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
362 * Use for REV200 STK52XX boards. Do not use with REV100 modules
363 * (because, there I2C1 is used as I2C bus)
364 * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
365 * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030)
366 * 000 -> All PSC2 pins are GIOPs
367 * 001 -> CAN1/2 on PSC2 pins
368 * Use for REV100 STK52xx boards
369 * use PSC3: Bits 20:23 (mask: 0x00000300):
370 * 0001 -> USB2
371 * 0000 -> GPIO
372 * use PSC6:
373 * on STK52xx:
374 * use as UART. Pins PSC6_0 to PSC6_3 are used.
375 * Bits 9:11 (mask: 0x00700000):
376 * 101 -> PSC6 : Extended POST test is not available
377 * on MINI-FAP and TQM5200_IB:
378 * use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000):
379 * 000 -> PSC6 could not be used as UART, CODEC or IrDA
380 * GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
381 * tests.
382 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200383#define CONFIG_SYS_GPS_PORT_CONFIG 0x81500114
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200384
385/*
386 * RTC configuration
387 */
388#define CONFIG_RTC_M41T11 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200389#define CONFIG_SYS_I2C_RTC_ADDR 0x68
390#define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* because Linux uses the same base
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200391 year */
392
393/*
394 * Miscellaneous configurable options
395 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200396#define CONFIG_SYS_LONGHELP /* undef to save memory */
397#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Martin Krause33ed73b2007-11-12 10:56:17 +0100398#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Jon Loeligerd794cfe2007-07-04 22:31:15 -0500399#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200400#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200401#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200402#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200403#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200404#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
405#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
406#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200407
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200408#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
Jon Loeligerd794cfe2007-07-04 22:31:15 -0500409#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200410# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
Jon Loeligerd794cfe2007-07-04 22:31:15 -0500411#endif
412
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200413/* Enable an alternate, more extensive memory test */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200414#define CONFIG_SYS_ALT_MEMTEST
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200415
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200416#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
417#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200418
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200419#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200420
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200421#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200422
423/*
Jon Loeligera1aa0bb2007-07-10 09:22:23 -0500424 * Enable loopw command.
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200425 */
426#define CONFIG_LOOPW
427
428/*
429 * Various low-level settings
430 */
431#if defined(CONFIG_MPC5200)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200432#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
433#define CONFIG_SYS_HID0_FINAL HID0_ICE
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200434#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200435#define CONFIG_SYS_HID0_INIT 0
436#define CONFIG_SYS_HID0_FINAL 0
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200437#endif
438
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200439#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
440#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
441#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
442#define CONFIG_SYS_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200443#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200444#define CONFIG_SYS_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200445#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200446#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
447#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200448
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200449#define CONFIG_LAST_STAGE_INIT
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200450
451/*
452 * SRAM - Do not map below 2 GB in address space, because this area is used
453 * for SDRAM autosizing.
454 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200455#define CONFIG_SYS_CS2_START 0xE5000000
456#define CONFIG_SYS_CS2_SIZE 0x100000 /* 1 MByte */
457#define CONFIG_SYS_CS2_CFG 0x0004D930
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200458
459/*
460 * Grafic controller - Do not map below 2 GB in address space, because this
461 * area is used for SDRAM autosizing.
462 */
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200463#define SM501_FB_BASE 0xE0000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200464#define CONFIG_SYS_CS1_START (SM501_FB_BASE)
465#define CONFIG_SYS_CS1_SIZE 0x4000000 /* 64 MByte */
466#define CONFIG_SYS_CS1_CFG 0x8F48FF70
467#define SM501_MMIO_BASE CONFIG_SYS_CS1_START + 0x03E00000
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200468
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200469#define CONFIG_SYS_CS_BURST 0x00000000
470#define CONFIG_SYS_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200471
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200472#define CONFIG_SYS_RESET_ADDRESS 0xff000000
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200473
474/*-----------------------------------------------------------------------
475 * USB stuff
476 *-----------------------------------------------------------------------
477 */
478#define CONFIG_USB_CLOCK 0x0001BBBB
479#define CONFIG_USB_CONFIG 0x00001000
480
481/*-----------------------------------------------------------------------
482 * IDE/ATA stuff Supports IDE harddisk
483 *-----------------------------------------------------------------------
484 */
485
486#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
487
488#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
489#undef CONFIG_IDE_LED /* LED for ide not supported */
490
491#define CONFIG_IDE_RESET /* reset for ide supported */
492#define CONFIG_IDE_PREINIT
493
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200494#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
495#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200496
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200497#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200498
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200499#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200500
501/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200502#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200503
504/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200505#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200506
507/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200508#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200509
510/* Interval between registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200511#define CONFIG_SYS_ATA_STRIDE 4
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200512
513#endif /* __CONFIG_H */