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Julien May5c374c92008-06-23 13:57:52 +02001/*
2 * Copyright (C) 2008 Miromico AG
3 *
4 * Configuration settings for the Miromico Hammerhead AVR32 board
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24#ifndef __CONFIG_H
25#define __CONFIG_H
26
27#define CONFIG_AVR32 1
28#define CONFIG_AT32AP 1
29#define CONFIG_AT32AP7000 1
30#define CONFIG_HAMMERHEAD 1
31
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020032#define CONFIG_SYS_HZ 1000
Julien May5c374c92008-06-23 13:57:52 +020033
34/*
35 * Set up the PLL to run at 125 MHz, the CPU to run at the PLL
36 * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency
37 * and the PBA bus to run at 1/4 the PLL frequency.
38 */
39#define CONFIG_PLL 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020040#define CONFIG_SYS_POWER_MANAGER 1
41#define CONFIG_SYS_OSC0_HZ 25000000
42#define CONFIG_SYS_PLL0_DIV 1
43#define CONFIG_SYS_PLL0_MUL 5
44#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16
45#define CONFIG_SYS_CLKDIV_CPU 0
46#define CONFIG_SYS_CLKDIV_HSB 1
47#define CONFIG_SYS_CLKDIV_PBA 2
48#define CONFIG_SYS_CLKDIV_PBB 1
Julien May5c374c92008-06-23 13:57:52 +020049
50/*
51 * The PLLOPT register controls the PLL like this:
52 * icp = PLLOPT<2>
53 * ivco = PLLOPT<1:0>
54 *
55 * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
56 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020057#define CONFIG_SYS_PLL0_OPT 0x04
Julien May5c374c92008-06-23 13:57:52 +020058
59#define CONFIG_USART1 1
60
61#define CONFIG_HOSTNAME hammerhead
62
63/* User serviceable stuff */
64#define CONFIG_DOS_PARTITION 1
65
66#define CONFIG_CMDLINE_TAG 1
67#define CONFIG_SETUP_MEMORY_TAGS 1
68#define CONFIG_INITRD_TAG 1
69
70#define CONFIG_STACKSIZE (2048)
71
72#define CONFIG_BAUDRATE 115200
73#define CONFIG_BOOTARGS \
74 "console=ttyS0 root=mtd1 rootfstype=jffs2"
75#define CONFIG_BOOTCOMMAND \
76 "fsload; bootm"
77
78/*
79 * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
80 * data on the serial line may interrupt the boot sequence.
81 */
82#define CONFIG_BOOTDELAY 1
83#define CONFIG_AUTOBOOT 1
84#define CONFIG_AUTOBOOT_KEYED 1
85#define CONFIG_AUTOBOOT_PROMPT \
Haavard Skinnemoen33eac2b2008-08-20 09:28:36 +020086 "Press SPACE to abort autoboot in %d seconds\n", bootdelay
Julien May5c374c92008-06-23 13:57:52 +020087#define CONFIG_AUTOBOOT_DELAY_STR "d"
88#define CONFIG_AUTOBOOT_STOP_STR " "
89
90/*
91 * After booting the board for the first time, new ethernet address
92 * should be generated and assigned to the environment variables
93 * "ethaddr". This is normally done during production.
94 */
95#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
96#define CONFIG_NET_MULTI 1
97
98/*
99 * BOOTP/DHCP options
100 */
101#define CONFIG_BOOTP_SUBNETMASK
102#define CONFIG_BOOTP_GATEWAY
103
104/*
105 * Command line configuration.
106 */
107#include <config_cmd_default.h>
108
109#define CONFIG_CMD_ASKENV
110#define CONFIG_CMD_DHCP
111#define CONFIG_CMD_EXT2
112#define CONFIG_CMD_FAT
113#define CONFIG_CMD_JFFS2
114#define CONFIG_CMD_MMC
115#undef CONFIG_CMD_FPGA
116#undef CONFIG_CMD_SETGETDCR
117
118#define CONFIG_ATMEL_USART 1
119#define CONFIG_MACB 1
Haavard Skinnemoenab0df362008-08-29 21:09:49 +0200120#define CONFIG_PORTMUX_PIO 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121#define CONFIG_SYS_NR_PIOS 5
122#define CONFIG_SYS_HSDRAMC 1
Julien May5c374c92008-06-23 13:57:52 +0200123#define CONFIG_MMC 1
124#define CONFIG_ATMEL_MCI 1
125
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126#define CONFIG_SYS_DCACHE_LINESZ 32
127#define CONFIG_SYS_ICACHE_LINESZ 32
Julien May5c374c92008-06-23 13:57:52 +0200128
129#define CONFIG_NR_DRAM_BANKS 1
130
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#define CONFIG_SYS_FLASH_CFI 1
Haavard Skinnemoen49267142008-08-20 09:40:16 +0200132#define CONFIG_FLASH_CFI_DRIVER 1
Julien May5c374c92008-06-23 13:57:52 +0200133
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#define CONFIG_SYS_FLASH_BASE 0x00000000
135#define CONFIG_SYS_FLASH_SIZE 0x800000
136#define CONFIG_SYS_MAX_FLASH_BANKS 1
137#define CONFIG_SYS_MAX_FLASH_SECT 135
Julien May5c374c92008-06-23 13:57:52 +0200138
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
Julien May5c374c92008-06-23 13:57:52 +0200140
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#define CONFIG_SYS_INTRAM_BASE 0x24000000
142#define CONFIG_SYS_INTRAM_SIZE 0x8000
Julien May5c374c92008-06-23 13:57:52 +0200143
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_SDRAM_BASE 0x10000000
Julien May5c374c92008-06-23 13:57:52 +0200145
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200146#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200147#define CONFIG_ENV_SIZE 65536
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
Julien May5c374c92008-06-23 13:57:52 +0200149
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
Julien May5c374c92008-06-23 13:57:52 +0200151
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152#define CONFIG_SYS_MALLOC_LEN (256*1024)
Julien May5c374c92008-06-23 13:57:52 +0200153
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154#define CONFIG_SYS_DMA_ALLOC_LEN (16384)
Julien May5c374c92008-06-23 13:57:52 +0200155
156/* Allow 4MB for the kernel run-time image */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x00400000)
158#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
Julien May5c374c92008-06-23 13:57:52 +0200159
160/* Other configuration settings that shouldn't have to change all that often */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161#define CONFIG_SYS_PROMPT "Hammerhead> "
162#define CONFIG_SYS_CBSIZE 256
163#define CONFIG_SYS_MAXARGS 16
164#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
165#define CONFIG_SYS_LONGHELP 1
Julien May5c374c92008-06-23 13:57:52 +0200166
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
168#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x1f00000)
Julien May5c374c92008-06-23 13:57:52 +0200169
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
Julien May5c374c92008-06-23 13:57:52 +0200171
172#endif /* __CONFIG_H */