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Heiko Schocherd0449542009-03-12 07:37:28 +01001/*
2 * (C) Copyright 2009
3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * configuration options, keymile 8xx board specific
26 */
27
28#ifndef __CONFIG_KM8XX_H
29#define __CONFIG_KM8XX_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_KM8XX 1 /* on a km8xx board */
37
38/* include common defines/options for all Keymile boards */
39#include "keymile-common.h"
40
Heiko Schocher1b6275d2009-03-12 07:37:34 +010041#if defined(CONFIG_KMSUPX4)
42#undef CONFIG_I2C_MUX /* no I2C mux on this board */
43#endif
44
Heiko Schocherd0449542009-03-12 07:37:28 +010045#define CONFIG_8xx_GCLK_FREQ 66000000
46
47#define CONFIG_SYS_SMC_UCODE_PATCH 1 /* Relocate SMC1 */
48#define CONFIG_SYS_SMC_DPMEM_OFFSET 0x1fc0
49#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
50#define CONFIG_SYS_SMC_RXBUFLEN 128
51#define CONFIG_SYS_MAXIDLE 10
52
53#define CONFIG_SYS_CPM_BOOTCOUNT_ADDR 0x1eb0 /* In case of SMC relocation,
54 * the default value is not
55 * working
56 */
57
58#define BOOTFLASH_START F0000000
59#define CONFIG_PRAM 512 /* protected RAM [KBytes] */
60
61#define CONFIG_PREBOOT "echo;" \
62 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
63 "echo"
64
65#define BOOTFLASH_START F0000000
66#define CONFIG_PRAM 512 /* protected RAM [KBytes] */
67
Heiko Schocher1b6275d2009-03-12 07:37:34 +010068#if defined(CONFIG_MGSUVD)
Heiko Schocherd0449542009-03-12 07:37:28 +010069#define CONFIG_ENV_IVM "EEprom_ivm=pca9544a:70:4 \0"
Heiko Schocher1b6275d2009-03-12 07:37:34 +010070#else
71#define CONFIG_ENV_IVM ""
72#endif
73
74#define MTDIDS_DEFAULT "nor0=app"
75#define MTDPARTS_DEFAULT \
76 "mtdparts=app:384k(u-boot),128k(env),128k(envred),128k(free)," \
77 "1536k(esw0),8704k(rootfs0),1536k(esw1),2432k(rootfs1),640k(var)," \
78 "768k(cfg)"
Heiko Schocherd0449542009-03-12 07:37:28 +010079
80#define CONFIG_EXTRA_ENV_SETTINGS \
81 CONFIG_KM_DEF_ENV \
82 "rootpath=/opt/eldk/ppc_8xx\0" \
83 "addcon=setenv bootargs ${bootargs} " \
84 "console=ttyCPM0,${baudrate}\0" \
85 "mtdids=nor0=app \0" \
Heiko Schocher1b6275d2009-03-12 07:37:34 +010086 "mtdparts=" MK_STR(MTDPARTS_DEFAULT) "\0" \
Heiko Schocherd0449542009-03-12 07:37:28 +010087 "partition=nor0,9 \0" \
88 "new_env=prot off F0060000 F009FFFF; era F0060000 F009FFFF \0" \
89 CONFIG_ENV_IVM \
90 ""
91
92#undef CONFIG_RTC_MPC8xx /* MPC866 does not support RTC */
93
94#define CONFIG_TIMESTAMP /* but print image timestmps */
95
96/*
97 * Low Level Configuration Settings
98 * (address mappings, register initial values, etc.)
99 * You should know what you are doing if you make changes here.
100 */
101/*-----------------------------------------------------------------------
102 * Internal Memory Mapped Register
103 */
104#define CONFIG_SYS_IMMR 0xFFF00000
105
106/*-----------------------------------------------------------------------
107 * Definitions for initial stack pointer and data area (in DPRAM)
108 */
109#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
110#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
111#define CONFIG_SYS_GBL_DATA_SIZE 64
112#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
113#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
114
115/*-----------------------------------------------------------------------
116 * Start addresses for the final memory configuration
117 * (Set up by the startup code)
118 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
119 */
120#define CONFIG_SYS_SDRAM_BASE 0x00000000
121#define CONFIG_SYS_FLASH_BASE 0xf0000000
122#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* 384 kB for Monitor */
123#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
124#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* 256 kB for malloc() */
125
126/*
127 * For booting Linux, the board info and command line data
128 * have to be in the first 8 MB of memory, since this is
129 * the maximum mapped by the Linux kernel during initialization.
130 */
131#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
132
133/*-----------------------------------------------------------------------
134 * FLASH organization
135 */
136/* max number of memory banks */
137#define CONFIG_SYS_MAX_FLASH_BANKS 1
138#define CONFIG_SYS_FLASH_SIZE 32
139#define CONFIG_SYS_FLASH_CFI
140#define CONFIG_FLASH_CFI_DRIVER
141/* max num of sects on one chip */
142#define CONFIG_SYS_MAX_FLASH_SECT 256
143
144#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* (in ms) */
145#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* (in ms) */
146
147#define CONFIG_ENV_IS_IN_FLASH 1
148#define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN
149#define CONFIG_ENV_SIZE 0x04000 /* Total Size of Environment Sector */
150#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
151
152/* Address and size of Redundant Environment Sector */
153#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
154#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
155#define CONFIG_ENV_BUFFER_PRINT 1
156
157/*-----------------------------------------------------------------------
158 * Cache Configuration
159 */
160#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
161#if defined(CONFIG_CMD_KGDB)
162#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
163#endif
164
165/*-----------------------------------------------------------------------
166 * SYPCR - System Protection Control 11-9
167 * SYPCR can only be written once after reset!
168 *-----------------------------------------------------------------------
169 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
170 */
171#define CONFIG_SYS_SYPCR 0xffffff89
172
173/*-----------------------------------------------------------------------
174 * SIUMCR - SIU Module Configuration 11-6
175 *-----------------------------------------------------------------------
176 */
Heiko Schocher1b6275d2009-03-12 07:37:34 +0100177#if defined(CONFIG_MGSUVD)
Heiko Schocherd0449542009-03-12 07:37:28 +0100178#define CONFIG_SYS_SIUMCR 0x00610480
Heiko Schocher1b6275d2009-03-12 07:37:34 +0100179#else
180#define CONFIG_SYS_SIUMCR 0x00610400
181#endif
Heiko Schocherd0449542009-03-12 07:37:28 +0100182
183/*-----------------------------------------------------------------------
184 * TBSCR - Time Base Status and Control 11-26
185 *-----------------------------------------------------------------------
186 * Clear Reference Interrupt Status, Timebase freezing enabled
187 */
188#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
189
190/*-----------------------------------------------------------------------
191 * PISCR - Periodic Interrupt Status and Control 11-31
192 *-----------------------------------------------------------------------
193 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
194 */
195#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
196
197/*-----------------------------------------------------------------------
198 * SCCR - System Clock and reset Control Register 15-27
199 *-----------------------------------------------------------------------
200 * Set clock output, timebase and RTC source and divider,
201 * power management and some other internal clocks
202 */
Heiko Schocher1b6275d2009-03-12 07:37:34 +0100203#if defined(CONFIG_MGSUVD)
Heiko Schocherd0449542009-03-12 07:37:28 +0100204#define SCCR_MASK 0x01800000
Heiko Schocher1b6275d2009-03-12 07:37:34 +0100205#else
206#define SCCR_MASK 0x00000000
207#endif
Heiko Schocherd0449542009-03-12 07:37:28 +0100208#define CONFIG_SYS_SCCR 0x01800000
209
210#define CONFIG_SYS_DER 0
211
212/*
213 * Init Memory Controller:
214 *
215 * BR0/1 and OR0/1 (FLASH)
216 */
217
218#define FLASH_BASE0_PRELIM 0xf0000000 /* FLASH bank #0 */
219
220/* used to re-map FLASH both when starting from SRAM or FLASH:
221 * restrict access enough to keep SRAM working (if any)
222 * but not too much to meddle with FLASH accesses
223 */
224#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
225#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
226
227/*
228 * FLASH timing: Default value of OR0 after reset
229 */
230#define CONFIG_SYS_OR0_PRELIM 0xfe000954
231#define CONFIG_SYS_BR0_PRELIM 0xf0000401
232
233/*
234 * BR1 and OR1 (SDRAM)
235 *
236 */
237#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */
238#define SDRAM_MAX_SIZE (64 << 20) /* max 64 MB per bank */
239
240/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
241#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
242
243#define CONFIG_SYS_OR1_PRELIM 0xfc000800
244#define CONFIG_SYS_BR1_PRELIM (0x000000C0 | 0x01)
245
246#define CONFIG_SYS_MPTPR 0x0200
247/* PTB=16, AMB=001, FIXME 1 RAS precharge cycles, 1 READ loop cycle (not used),
248 1 Write loop Cycle (not used), 1 Timer Loop Cycle */
Heiko Schocher1b6275d2009-03-12 07:37:34 +0100249#if defined(CONFIG_MGSUVD)
Heiko Schocherd0449542009-03-12 07:37:28 +0100250#define CONFIG_SYS_MBMR 0x10964111
Heiko Schocher1b6275d2009-03-12 07:37:34 +0100251#else
252#define CONFIG_SYS_MBMR 0x20964111
253#endif
Heiko Schocherd0449542009-03-12 07:37:28 +0100254#define CONFIG_SYS_MAR 0x00000088
255
256/*
257 * 4096 Rows from SDRAM example configuration
258 * 1000 factor s -> ms
259 * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
260 * 4 Number of refresh cycles per period
261 * 64 Refresh cycle in ms per number of rows
262 */
263#define CONFIG_SYS_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
264
265/* GPIO/PIGGY on CS3 initialization values
266*/
267#define CONFIG_SYS_PIGGY_BASE (0x30000000)
Heiko Schocher1b6275d2009-03-12 07:37:34 +0100268#if defined(CONFIG_MGSUVD)
Heiko Schocherd0449542009-03-12 07:37:28 +0100269#define CONFIG_SYS_OR3_PRELIM (0xfe000d24)
270#define CONFIG_SYS_BR3_PRELIM (0x30000401)
Heiko Schocher1b6275d2009-03-12 07:37:34 +0100271#else
272#define CONFIG_SYS_OR3_PRELIM (0xf8000d26)
273#define CONFIG_SYS_BR3_PRELIM (0x30000401)
274#endif
Heiko Schocherd0449542009-03-12 07:37:28 +0100275
276/*
277 * Internal Definitions
278 *
279 * Boot Flags
280 */
281#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
282#define BOOTFLAG_WARM 0x02 /* Software reboot */
283
284#define CONFIG_SCC3_ENET
285#define CONFIG_ETHPRIME "SCC ETHERNET"
286#define CONFIG_HAS_ETH0
287
288/* pass open firmware flat tree */
289#define CONFIG_OF_LIBFDT 1
290#define CONFIG_OF_BOARD_SETUP 1
291
292#define OF_STDOUT_PATH "/soc/cpm/serial@a80"
293
294/* enable I2C and select the hardware/software driver */
295#undef CONFIG_HARD_I2C /* I2C with hardware support */
296#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
297/* I2C speed and slave address */
298#define CONFIG_SYS_I2C_SPEED 50000
299#define CONFIG_SYS_I2C_SLAVE 0x7F
300#define I2C_SOFT_DECLARATIONS
301
302/*
303 * Software (bit-bang) I2C driver configuration
304 */
305#define I2C_BASE_DIR ((u16 *)(CONFIG_SYS_PIGGY_BASE + 0x04))
306#define I2C_BASE_PORT ((u8 *)(CONFIG_SYS_PIGGY_BASE + 0x09))
307
308#define SDA_BIT 0x40
309#define SCL_BIT 0x80
310#define SDA_CONF 0x1000
311#define SCL_CONF 0x2000
312
313#define I2C_ACTIVE do {} while (0)
314#define I2C_TRISTATE do {} while (0)
315#define I2C_READ ((in_8(I2C_BASE_PORT) & SDA_BIT) == SDA_BIT)
316#define I2C_SDA(bit) if(bit) { \
317 clrbits(be16, I2C_BASE_DIR, SDA_CONF); \
318 } else { \
319 clrbits(8, I2C_BASE_PORT, SDA_BIT); \
320 setbits(be16, I2C_BASE_DIR, SDA_CONF); \
321 }
322#define I2C_SCL(bit) if(bit) { \
323 clrbits(be16, I2C_BASE_DIR, SCL_CONF); \
324 } else { \
325 clrbits(8, I2C_BASE_PORT, SCL_BIT); \
326 setbits(be16, I2C_BASE_DIR, SCL_CONF); \
327 }
328#define I2C_DELAY udelay(50) /* 1/4 I2C clock duration */
329
330#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
331
332/* I2C SYSMON (LM75, AD7414 is almost compatible) */
333#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
Heiko Schocher1b6275d2009-03-12 07:37:34 +0100334#if defined(CONFIG_MGSUVD)
Heiko Schocherd0449542009-03-12 07:37:28 +0100335#define CONFIG_DTT_SENSORS {0, 2, 4, 6} /* Sensor addresses */
Heiko Schocher1b6275d2009-03-12 07:37:34 +0100336#else
337#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
338#endif
Heiko Schocherd0449542009-03-12 07:37:28 +0100339#define CONFIG_SYS_DTT_MAX_TEMP 70
340#define CONFIG_SYS_DTT_LOW_TEMP -30
341#define CONFIG_SYS_DTT_HYSTERESIS 3
342#define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS)
Heiko Schocherd0449542009-03-12 07:37:28 +0100343#endif /* __CONFIG_KM8XX_H */