blob: 748ec0ab5224bd58b95e7d152cde2a7480fdc669 [file] [log] [blame]
Stefan Roese5fb692c2007-01-18 10:25:34 +01001/*
2 * (C) Copyright 2007
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <ppc_asm.tmpl>
25#include <config.h>
26
27/* General */
28#define TLB_VALID 0x00000200
29#define _256M 0x10000000
30
31/* Supported page sizes */
32
33#define SZ_1K 0x00000000
34#define SZ_4K 0x00000010
35#define SZ_16K 0x00000020
36#define SZ_64K 0x00000030
37#define SZ_256K 0x00000040
38#define SZ_1M 0x00000050
39#define SZ_8M 0x00000060
40#define SZ_16M 0x00000070
41#define SZ_256M 0x00000090
42
43/* Storage attributes */
44#define SA_W 0x00000800 /* Write-through */
45#define SA_I 0x00000400 /* Caching inhibited */
46#define SA_M 0x00000200 /* Memory coherence */
47#define SA_G 0x00000100 /* Guarded */
48#define SA_E 0x00000080 /* Endian */
49
50/* Access control */
51#define AC_X 0x00000024 /* Execute */
52#define AC_W 0x00000012 /* Write */
53#define AC_R 0x00000009 /* Read */
54
55/* Some handy macros */
56
57#define EPN(e) ((e) & 0xfffffc00)
58#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
59#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
60#define TLB2(a) ( (a)&0x00000fbf )
61
62#define tlbtab_start\
63 mflr r1 ;\
64 bl 0f ;
65
66#define tlbtab_end\
67 .long 0, 0, 0 ; \
680: mflr r0 ; \
69 mtlr r1 ; \
70 blr ;
71
72#define tlbentry(epn,sz,rpn,erpn,attr)\
73 .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
74
75/**************************************************************************
76 * TLB TABLE
77 *
78 * This table is used by the cpu boot code to setup the initial tlb
79 * entries. Rather than make broad assumptions in the cpu source tree,
80 * this table lets each board set things up however they like.
81 *
82 * Pointer to the table is returned in r1
83 *
84 *************************************************************************/
85
86 .section .bootpg,"ax"
87 .globl tlbtab
88
89tlbtab:
90 tlbtab_start
91 tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020092 tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
93 tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X )
94 tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
95 tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
96 tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
Stefan Roese5fb692c2007-01-18 10:25:34 +010097 tlbtab_end