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Ilya Yanok0b23fb32009-07-21 19:32:21 +04001/*
2 * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com>
3 * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org>
4 * (C) Copyright 2008 Armadeus Systems nc
5 * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
6 * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <malloc.h>
26#include <net.h>
27#include <miiphy.h>
28#include "fec_mxc.h"
29
30#include <asm/arch/clock.h>
31#include <asm/arch/imx-regs.h>
32#include <asm/io.h>
33#include <asm/errno.h>
34
35DECLARE_GLOBAL_DATA_PTR;
36
37#ifndef CONFIG_MII
38#error "CONFIG_MII has to be defined!"
39#endif
40
Marek Vasut392b8502011-09-11 18:05:33 +000041#ifndef CONFIG_FEC_XCV_TYPE
42#define CONFIG_FEC_XCV_TYPE MII100
43#endif
44
Ilya Yanok0b23fb32009-07-21 19:32:21 +040045#undef DEBUG
46
47struct nbuf {
48 uint8_t data[1500]; /**< actual data */
49 int length; /**< actual length */
50 int used; /**< buffer in use or not */
51 uint8_t head[16]; /**< MAC header(6 + 6 + 2) + 2(aligned) */
52};
53
Ilya Yanok0b23fb32009-07-21 19:32:21 +040054/*
55 * MII-interface related functions
56 */
Mike Frysinger5700bb62010-07-27 18:35:08 -040057static int fec_miiphy_read(const char *dev, uint8_t phyAddr, uint8_t regAddr,
Ilya Yanok0b23fb32009-07-21 19:32:21 +040058 uint16_t *retVal)
59{
60 struct eth_device *edev = eth_get_dev_by_name(dev);
61 struct fec_priv *fec = (struct fec_priv *)edev->priv;
Marek Vasutd133b882011-09-11 18:05:34 +000062 struct ethernet_regs *eth = fec->eth;
Ilya Yanok0b23fb32009-07-21 19:32:21 +040063
64 uint32_t reg; /* convenient holder for the PHY register */
65 uint32_t phy; /* convenient holder for the PHY */
66 uint32_t start;
67
68 /*
69 * reading from any PHY's register is done by properly
70 * programming the FEC's MII data register.
71 */
Marek Vasutd133b882011-09-11 18:05:34 +000072 writel(FEC_IEVENT_MII, &eth->ievent);
Ilya Yanok0b23fb32009-07-21 19:32:21 +040073 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
74 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
75
76 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA |
Marek Vasutd133b882011-09-11 18:05:34 +000077 phy | reg, &eth->mii_data);
Ilya Yanok0b23fb32009-07-21 19:32:21 +040078
79 /*
80 * wait for the related interrupt
81 */
Graeme Russa60d1e52011-07-15 23:31:37 +000082 start = get_timer(0);
Marek Vasutd133b882011-09-11 18:05:34 +000083 while (!(readl(&eth->ievent) & FEC_IEVENT_MII)) {
Ilya Yanok0b23fb32009-07-21 19:32:21 +040084 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
85 printf("Read MDIO failed...\n");
86 return -1;
87 }
88 }
89
90 /*
91 * clear mii interrupt bit
92 */
Marek Vasutd133b882011-09-11 18:05:34 +000093 writel(FEC_IEVENT_MII, &eth->ievent);
Ilya Yanok0b23fb32009-07-21 19:32:21 +040094
95 /*
96 * it's now safe to read the PHY's register
97 */
Marek Vasutd133b882011-09-11 18:05:34 +000098 *retVal = readl(&eth->mii_data);
Ilya Yanok0b23fb32009-07-21 19:32:21 +040099 debug("fec_miiphy_read: phy: %02x reg:%02x val:%#x\n", phyAddr,
100 regAddr, *retVal);
101 return 0;
102}
103
Stefano Babic4294b242010-02-01 14:51:30 +0100104static void fec_mii_setspeed(struct fec_priv *fec)
105{
106 /*
107 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
108 * and do not drop the Preamble.
109 */
110 writel((((imx_get_fecclk() / 1000000) + 2) / 5) << 1,
111 &fec->eth->mii_speed);
112 debug("fec_init: mii_speed %#lx\n",
Marek Vasut879cf262011-09-11 18:05:29 +0000113 readl(&fec->eth->mii_speed));
Stefano Babic4294b242010-02-01 14:51:30 +0100114}
Mike Frysinger5700bb62010-07-27 18:35:08 -0400115static int fec_miiphy_write(const char *dev, uint8_t phyAddr, uint8_t regAddr,
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400116 uint16_t data)
117{
118 struct eth_device *edev = eth_get_dev_by_name(dev);
119 struct fec_priv *fec = (struct fec_priv *)edev->priv;
Marek Vasutd133b882011-09-11 18:05:34 +0000120 struct ethernet_regs *eth = fec->eth;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400121
122 uint32_t reg; /* convenient holder for the PHY register */
123 uint32_t phy; /* convenient holder for the PHY */
124 uint32_t start;
125
126 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
127 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
128
129 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
Marek Vasutd133b882011-09-11 18:05:34 +0000130 FEC_MII_DATA_TA | phy | reg | data, &eth->mii_data);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400131
132 /*
133 * wait for the MII interrupt
134 */
Graeme Russa60d1e52011-07-15 23:31:37 +0000135 start = get_timer(0);
Marek Vasutd133b882011-09-11 18:05:34 +0000136 while (!(readl(&eth->ievent) & FEC_IEVENT_MII)) {
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400137 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
138 printf("Write MDIO failed...\n");
139 return -1;
140 }
141 }
142
143 /*
144 * clear MII interrupt bit
145 */
Marek Vasutd133b882011-09-11 18:05:34 +0000146 writel(FEC_IEVENT_MII, &eth->ievent);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400147 debug("fec_miiphy_write: phy: %02x reg:%02x val:%#x\n", phyAddr,
148 regAddr, data);
149
150 return 0;
151}
152
153static int miiphy_restart_aneg(struct eth_device *dev)
154{
Marek Vasut9e27e9d2011-09-16 01:13:47 +0200155 struct fec_priv *fec = (struct fec_priv *)dev->priv;
Marek Vasut2e5f4422011-09-11 18:05:36 +0000156 int ret = 0;
Marek Vasut9e27e9d2011-09-16 01:13:47 +0200157
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400158 /*
159 * Wake up from sleep if necessary
160 * Reset PHY, then delay 300ns
161 */
John Rigbycb17b922010-01-25 23:12:55 -0700162#ifdef CONFIG_MX27
Marek Vasut9e27e9d2011-09-16 01:13:47 +0200163 miiphy_write(dev->name, fec->phy_id, MII_DCOUNTER, 0x00FF);
John Rigbycb17b922010-01-25 23:12:55 -0700164#endif
Marek Vasut9e27e9d2011-09-16 01:13:47 +0200165 miiphy_write(dev->name, fec->phy_id, MII_BMCR,
Mike Frysinger8ef583a2010-12-23 15:40:12 -0500166 BMCR_RESET);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400167 udelay(1000);
168
169 /*
170 * Set the auto-negotiation advertisement register bits
171 */
Marek Vasut9e27e9d2011-09-16 01:13:47 +0200172 miiphy_write(dev->name, fec->phy_id, MII_ADVERTISE,
Mike Frysinger8ef583a2010-12-23 15:40:12 -0500173 LPA_100FULL | LPA_100HALF | LPA_10FULL |
174 LPA_10HALF | PHY_ANLPAR_PSB_802_3);
Marek Vasut9e27e9d2011-09-16 01:13:47 +0200175 miiphy_write(dev->name, fec->phy_id, MII_BMCR,
Mike Frysinger8ef583a2010-12-23 15:40:12 -0500176 BMCR_ANENABLE | BMCR_ANRESTART);
Marek Vasut2e5f4422011-09-11 18:05:36 +0000177
178 if (fec->mii_postcall)
179 ret = fec->mii_postcall(fec->phy_id);
180
181 return ret;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400182}
183
184static int miiphy_wait_aneg(struct eth_device *dev)
185{
186 uint32_t start;
187 uint16_t status;
Marek Vasut9e27e9d2011-09-16 01:13:47 +0200188 struct fec_priv *fec = (struct fec_priv *)dev->priv;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400189
190 /*
191 * Wait for AN completion
192 */
Graeme Russa60d1e52011-07-15 23:31:37 +0000193 start = get_timer(0);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400194 do {
195 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
196 printf("%s: Autonegotiation timeout\n", dev->name);
197 return -1;
198 }
199
Marek Vasut9e27e9d2011-09-16 01:13:47 +0200200 if (miiphy_read(dev->name, fec->phy_id,
Mike Frysinger8ef583a2010-12-23 15:40:12 -0500201 MII_BMSR, &status)) {
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400202 printf("%s: Autonegotiation failed. status: 0x%04x\n",
203 dev->name, status);
204 return -1;
205 }
Mike Frysinger8ef583a2010-12-23 15:40:12 -0500206 } while (!(status & BMSR_LSTATUS));
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400207
208 return 0;
209}
210static int fec_rx_task_enable(struct fec_priv *fec)
211{
212 writel(1 << 24, &fec->eth->r_des_active);
213 return 0;
214}
215
216static int fec_rx_task_disable(struct fec_priv *fec)
217{
218 return 0;
219}
220
221static int fec_tx_task_enable(struct fec_priv *fec)
222{
223 writel(1 << 24, &fec->eth->x_des_active);
224 return 0;
225}
226
227static int fec_tx_task_disable(struct fec_priv *fec)
228{
229 return 0;
230}
231
232/**
233 * Initialize receive task's buffer descriptors
234 * @param[in] fec all we know about the device yet
235 * @param[in] count receive buffer count to be allocated
236 * @param[in] size size of each receive buffer
237 * @return 0 on success
238 *
239 * For this task we need additional memory for the data buffers. And each
240 * data buffer requires some alignment. Thy must be aligned to a specific
241 * boundary each (DB_DATA_ALIGNMENT).
242 */
243static int fec_rbd_init(struct fec_priv *fec, int count, int size)
244{
245 int ix;
246 uint32_t p = 0;
247
248 /* reserve data memory and consider alignment */
javier Martin651ef902009-10-29 08:22:43 +0100249 if (fec->rdb_ptr == NULL)
250 fec->rdb_ptr = malloc(size * count + DB_DATA_ALIGNMENT);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400251 p = (uint32_t)fec->rdb_ptr;
252 if (!p) {
Stefano Babic4294b242010-02-01 14:51:30 +0100253 puts("fec_mxc: not enough malloc memory\n");
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400254 return -ENOMEM;
255 }
256 memset((void *)p, 0, size * count + DB_DATA_ALIGNMENT);
257 p += DB_DATA_ALIGNMENT-1;
258 p &= ~(DB_DATA_ALIGNMENT-1);
259
260 for (ix = 0; ix < count; ix++) {
261 writel(p, &fec->rbd_base[ix].data_pointer);
262 p += size;
263 writew(FEC_RBD_EMPTY, &fec->rbd_base[ix].status);
264 writew(0, &fec->rbd_base[ix].data_length);
265 }
266 /*
267 * mark the last RBD to close the ring
268 */
269 writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &fec->rbd_base[ix - 1].status);
270 fec->rbd_index = 0;
271
272 return 0;
273}
274
275/**
276 * Initialize transmit task's buffer descriptors
277 * @param[in] fec all we know about the device yet
278 *
279 * Transmit buffers are created externally. We only have to init the BDs here.\n
280 * Note: There is a race condition in the hardware. When only one BD is in
281 * use it must be marked with the WRAP bit to use it for every transmitt.
282 * This bit in combination with the READY bit results into double transmit
283 * of each data buffer. It seems the state machine checks READY earlier then
284 * resetting it after the first transfer.
285 * Using two BDs solves this issue.
286 */
287static void fec_tbd_init(struct fec_priv *fec)
288{
289 writew(0x0000, &fec->tbd_base[0].status);
290 writew(FEC_TBD_WRAP, &fec->tbd_base[1].status);
291 fec->tbd_index = 0;
292}
293
294/**
295 * Mark the given read buffer descriptor as free
296 * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0
297 * @param[in] pRbd buffer descriptor to mark free again
298 */
299static void fec_rbd_clean(int last, struct fec_bd *pRbd)
300{
301 /*
302 * Reset buffer descriptor as empty
303 */
304 if (last)
305 writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &pRbd->status);
306 else
307 writew(FEC_RBD_EMPTY, &pRbd->status);
308 /*
309 * no data in it
310 */
311 writew(0, &pRbd->data_length);
312}
313
314static int fec_get_hwaddr(struct eth_device *dev, unsigned char *mac)
315{
Liu Hui-R64343565e39c2010-11-18 23:45:55 +0000316 imx_get_mac_from_fuse(mac);
Eric Jarrige2e236bf2010-04-16 00:03:19 +0200317 return !is_valid_ether_addr(mac);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400318}
319
Stefano Babic4294b242010-02-01 14:51:30 +0100320static int fec_set_hwaddr(struct eth_device *dev)
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400321{
Stefano Babic4294b242010-02-01 14:51:30 +0100322 uchar *mac = dev->enetaddr;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400323 struct fec_priv *fec = (struct fec_priv *)dev->priv;
324
325 writel(0, &fec->eth->iaddr1);
326 writel(0, &fec->eth->iaddr2);
327 writel(0, &fec->eth->gaddr1);
328 writel(0, &fec->eth->gaddr2);
329
330 /*
331 * Set physical address
332 */
333 writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3],
334 &fec->eth->paddr1);
335 writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2);
336
337 return 0;
338}
339
340/**
341 * Start the FEC engine
342 * @param[in] dev Our device to handle
343 */
344static int fec_open(struct eth_device *edev)
345{
346 struct fec_priv *fec = (struct fec_priv *)edev->priv;
347
348 debug("fec_open: fec_open(dev)\n");
349 /* full-duplex, heartbeat disabled */
350 writel(1 << 2, &fec->eth->x_cntrl);
351 fec->rbd_index = 0;
352
353 /*
354 * Enable FEC-Lite controller
355 */
John Rigbycb17b922010-01-25 23:12:55 -0700356 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,
357 &fec->eth->ecntrl);
Liu Hui-R6434396912452011-01-03 22:27:36 +0000358#if defined(CONFIG_MX25) || defined(CONFIG_MX53)
John Rigby740d6ae2010-01-25 23:12:57 -0700359 udelay(100);
360 /*
361 * setup the MII gasket for RMII mode
362 */
363
364 /* disable the gasket */
365 writew(0, &fec->eth->miigsk_enr);
366
367 /* wait for the gasket to be disabled */
368 while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY)
369 udelay(2);
370
371 /* configure gasket for RMII, 50 MHz, no loopback, and no echo */
372 writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr);
373
374 /* re-enable the gasket */
375 writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr);
376
377 /* wait until MII gasket is ready */
378 int max_loops = 10;
379 while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) {
380 if (--max_loops <= 0) {
381 printf("WAIT for MII Gasket ready timed out\n");
382 break;
383 }
384 }
385#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400386
387 miiphy_wait_aneg(edev);
Marek Vasut9e27e9d2011-09-16 01:13:47 +0200388 miiphy_speed(edev->name, fec->phy_id);
389 miiphy_duplex(edev->name, fec->phy_id);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400390
391 /*
392 * Enable SmartDMA receive task
393 */
394 fec_rx_task_enable(fec);
395
396 udelay(100000);
397 return 0;
398}
399
400static int fec_init(struct eth_device *dev, bd_t* bd)
401{
402 uint32_t base;
403 struct fec_priv *fec = (struct fec_priv *)dev->priv;
Marek Vasut9e27e9d2011-09-16 01:13:47 +0200404 uint32_t mib_ptr = (uint32_t)&fec->eth->rmon_t_drop;
Marek Vasut9eb37702011-09-11 18:05:31 +0000405 uint32_t rcntrl;
Marek Vasut9e27e9d2011-09-16 01:13:47 +0200406 int i;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400407
John Rigbye9319f12010-10-13 14:31:08 -0600408 /* Initialize MAC address */
409 fec_set_hwaddr(dev);
410
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400411 /*
412 * reserve memory for both buffer descriptor chains at once
413 * Datasheet forces the startaddress of each chain is 16 byte
414 * aligned
415 */
javier Martin651ef902009-10-29 08:22:43 +0100416 if (fec->base_ptr == NULL)
417 fec->base_ptr = malloc((2 + FEC_RBD_NUM) *
418 sizeof(struct fec_bd) + DB_ALIGNMENT);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400419 base = (uint32_t)fec->base_ptr;
420 if (!base) {
Stefano Babic4294b242010-02-01 14:51:30 +0100421 puts("fec_mxc: not enough malloc memory\n");
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400422 return -ENOMEM;
423 }
424 memset((void *)base, 0, (2 + FEC_RBD_NUM) *
425 sizeof(struct fec_bd) + DB_ALIGNMENT);
426 base += (DB_ALIGNMENT-1);
427 base &= ~(DB_ALIGNMENT-1);
428
429 fec->rbd_base = (struct fec_bd *)base;
430
431 base += FEC_RBD_NUM * sizeof(struct fec_bd);
432
433 fec->tbd_base = (struct fec_bd *)base;
434
435 /*
436 * Set interrupt mask register
437 */
438 writel(0x00000000, &fec->eth->imask);
439
440 /*
441 * Clear FEC-Lite interrupt event register(IEVENT)
442 */
443 writel(0xffffffff, &fec->eth->ievent);
444
445
446 /*
447 * Set FEC-Lite receive control register(R_CNTRL):
448 */
Stefano Babic4294b242010-02-01 14:51:30 +0100449
Marek Vasut9eb37702011-09-11 18:05:31 +0000450 /* Start with frame length = 1518, common for all modes. */
451 rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT;
452 if (fec->xcv_type == SEVENWIRE)
453 rcntrl |= FEC_RCNTRL_FCE;
Marek Vasuta50a90c2011-09-11 18:05:32 +0000454 else if (fec->xcv_type == RMII)
455 rcntrl |= FEC_RCNTRL_RMII;
Marek Vasut9eb37702011-09-11 18:05:31 +0000456 else /* MII mode */
457 rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE;
458
459 writel(rcntrl, &fec->eth->r_cntrl);
460
461 if (fec->xcv_type == MII10 || fec->xcv_type == MII100)
Stefano Babic4294b242010-02-01 14:51:30 +0100462 fec_mii_setspeed(fec);
Marek Vasut9eb37702011-09-11 18:05:31 +0000463
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400464 /*
465 * Set Opcode/Pause Duration Register
466 */
467 writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */
468 writel(0x2, &fec->eth->x_wmrk);
469 /*
470 * Set multicast address filter
471 */
472 writel(0x00000000, &fec->eth->gaddr1);
473 writel(0x00000000, &fec->eth->gaddr2);
474
475
476 /* clear MIB RAM */
Marek Vasut9e27e9d2011-09-16 01:13:47 +0200477 for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
478 writel(0, i);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400479
480 /* FIFO receive start register */
481 writel(0x520, &fec->eth->r_fstart);
482
483 /* size and address of each buffer */
484 writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr);
485 writel((uint32_t)fec->tbd_base, &fec->eth->etdsr);
486 writel((uint32_t)fec->rbd_base, &fec->eth->erdsr);
487
488 /*
489 * Initialize RxBD/TxBD rings
490 */
491 if (fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE) < 0) {
492 free(fec->base_ptr);
John Ognessc179a282009-12-11 09:47:28 +0100493 fec->base_ptr = NULL;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400494 return -ENOMEM;
495 }
496 fec_tbd_init(fec);
497
498
499 if (fec->xcv_type != SEVENWIRE)
500 miiphy_restart_aneg(dev);
501
502 fec_open(dev);
503 return 0;
504}
505
506/**
507 * Halt the FEC engine
508 * @param[in] dev Our device to handle
509 */
510static void fec_halt(struct eth_device *dev)
511{
Marek Vasut9e27e9d2011-09-16 01:13:47 +0200512 struct fec_priv *fec = (struct fec_priv *)dev->priv;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400513 int counter = 0xffff;
514
515 /*
516 * issue graceful stop command to the FEC transmitter if necessary
517 */
John Rigbycb17b922010-01-25 23:12:55 -0700518 writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl),
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400519 &fec->eth->x_cntrl);
520
521 debug("eth_halt: wait for stop regs\n");
522 /*
523 * wait for graceful stop to register
524 */
525 while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA)))
John Rigbycb17b922010-01-25 23:12:55 -0700526 udelay(1);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400527
528 /*
529 * Disable SmartDMA tasks
530 */
531 fec_tx_task_disable(fec);
532 fec_rx_task_disable(fec);
533
534 /*
535 * Disable the Ethernet Controller
536 * Note: this will also reset the BD index counter!
537 */
John Rigby740d6ae2010-01-25 23:12:57 -0700538 writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN,
539 &fec->eth->ecntrl);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400540 fec->rbd_index = 0;
541 fec->tbd_index = 0;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400542 debug("eth_halt: done\n");
543}
544
545/**
546 * Transmit one frame
547 * @param[in] dev Our ethernet device to handle
548 * @param[in] packet Pointer to the data to be transmitted
549 * @param[in] length Data count in bytes
550 * @return 0 on success
551 */
552static int fec_send(struct eth_device *dev, volatile void* packet, int length)
553{
554 unsigned int status;
555
556 /*
557 * This routine transmits one frame. This routine only accepts
558 * 6-byte Ethernet addresses.
559 */
560 struct fec_priv *fec = (struct fec_priv *)dev->priv;
561
562 /*
563 * Check for valid length of data.
564 */
565 if ((length > 1500) || (length <= 0)) {
Stefano Babic4294b242010-02-01 14:51:30 +0100566 printf("Payload (%d) too large\n", length);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400567 return -1;
568 }
569
570 /*
571 * Setup the transmit buffer
572 * Note: We are always using the first buffer for transmission,
573 * the second will be empty and only used to stop the DMA engine
574 */
575 writew(length, &fec->tbd_base[fec->tbd_index].data_length);
576 writel((uint32_t)packet, &fec->tbd_base[fec->tbd_index].data_pointer);
577 /*
578 * update BD's status now
579 * This block:
580 * - is always the last in a chain (means no chain)
581 * - should transmitt the CRC
582 * - might be the last BD in the list, so the address counter should
583 * wrap (-> keep the WRAP flag)
584 */
585 status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP;
586 status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
587 writew(status, &fec->tbd_base[fec->tbd_index].status);
588
589 /*
590 * Enable SmartDMA transmit task
591 */
592 fec_tx_task_enable(fec);
593
594 /*
595 * wait until frame is sent .
596 */
597 while (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY) {
John Rigbycb17b922010-01-25 23:12:55 -0700598 udelay(1);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400599 }
600 debug("fec_send: status 0x%x index %d\n",
601 readw(&fec->tbd_base[fec->tbd_index].status),
602 fec->tbd_index);
603 /* for next transmission use the other buffer */
604 if (fec->tbd_index)
605 fec->tbd_index = 0;
606 else
607 fec->tbd_index = 1;
608
609 return 0;
610}
611
612/**
613 * Pull one frame from the card
614 * @param[in] dev Our ethernet device to handle
615 * @return Length of packet read
616 */
617static int fec_recv(struct eth_device *dev)
618{
619 struct fec_priv *fec = (struct fec_priv *)dev->priv;
620 struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index];
621 unsigned long ievent;
622 int frame_length, len = 0;
623 struct nbuf *frame;
624 uint16_t bd_status;
625 uchar buff[FEC_MAX_PKT_SIZE];
626
627 /*
628 * Check if any critical events have happened
629 */
630 ievent = readl(&fec->eth->ievent);
631 writel(ievent, &fec->eth->ievent);
632 debug("fec_recv: ievent 0x%x\n", ievent);
633 if (ievent & FEC_IEVENT_BABR) {
634 fec_halt(dev);
635 fec_init(dev, fec->bd);
636 printf("some error: 0x%08lx\n", ievent);
637 return 0;
638 }
639 if (ievent & FEC_IEVENT_HBERR) {
640 /* Heartbeat error */
641 writel(0x00000001 | readl(&fec->eth->x_cntrl),
642 &fec->eth->x_cntrl);
643 }
644 if (ievent & FEC_IEVENT_GRA) {
645 /* Graceful stop complete */
646 if (readl(&fec->eth->x_cntrl) & 0x00000001) {
647 fec_halt(dev);
648 writel(~0x00000001 & readl(&fec->eth->x_cntrl),
649 &fec->eth->x_cntrl);
650 fec_init(dev, fec->bd);
651 }
652 }
653
654 /*
655 * ensure reading the right buffer status
656 */
657 bd_status = readw(&rbd->status);
658 debug("fec_recv: status 0x%x\n", bd_status);
659
660 if (!(bd_status & FEC_RBD_EMPTY)) {
661 if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) &&
662 ((readw(&rbd->data_length) - 4) > 14)) {
663 /*
664 * Get buffer address and size
665 */
666 frame = (struct nbuf *)readl(&rbd->data_pointer);
667 frame_length = readw(&rbd->data_length) - 4;
668 /*
669 * Fill the buffer and pass it to upper layers
670 */
671 memcpy(buff, frame->data, frame_length);
672 NetReceive(buff, frame_length);
673 len = frame_length;
674 } else {
675 if (bd_status & FEC_RBD_ERR)
676 printf("error frame: 0x%08lx 0x%08x\n",
677 (ulong)rbd->data_pointer,
678 bd_status);
679 }
680 /*
681 * free the current buffer, restart the engine
682 * and move forward to the next buffer
683 */
684 fec_rbd_clean(fec->rbd_index == (FEC_RBD_NUM - 1) ? 1 : 0, rbd);
685 fec_rx_task_enable(fec);
686 fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM;
687 }
688 debug("fec_recv: stop\n");
689
690 return len;
691}
692
Marek Vasut9e27e9d2011-09-16 01:13:47 +0200693static int fec_probe(bd_t *bd, int dev_id, int phy_id, uint32_t base_addr)
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400694{
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400695 struct eth_device *edev;
Marek Vasut9e27e9d2011-09-16 01:13:47 +0200696 struct fec_priv *fec;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400697 unsigned char ethaddr[6];
Marek Vasute382fb42011-09-11 18:05:37 +0000698 uint32_t start;
699 int ret = 0;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400700
701 /* create and fill edev struct */
702 edev = (struct eth_device *)malloc(sizeof(struct eth_device));
703 if (!edev) {
Marek Vasut9e27e9d2011-09-16 01:13:47 +0200704 puts("fec_mxc: not enough malloc memory for eth_device\n");
Marek Vasute382fb42011-09-11 18:05:37 +0000705 ret = -ENOMEM;
706 goto err1;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400707 }
Marek Vasut9e27e9d2011-09-16 01:13:47 +0200708
709 fec = (struct fec_priv *)malloc(sizeof(struct fec_priv));
710 if (!fec) {
711 puts("fec_mxc: not enough malloc memory for fec_priv\n");
Marek Vasute382fb42011-09-11 18:05:37 +0000712 ret = -ENOMEM;
713 goto err2;
Marek Vasut9e27e9d2011-09-16 01:13:47 +0200714 }
715
Nobuhiro Iwamatsude0b9572010-10-19 14:03:42 +0900716 memset(edev, 0, sizeof(*edev));
Marek Vasut9e27e9d2011-09-16 01:13:47 +0200717 memset(fec, 0, sizeof(*fec));
718
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400719 edev->priv = fec;
720 edev->init = fec_init;
721 edev->send = fec_send;
722 edev->recv = fec_recv;
723 edev->halt = fec_halt;
Heiko Schocherfb57ec92010-04-27 07:43:52 +0200724 edev->write_hwaddr = fec_set_hwaddr;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400725
Marek Vasut9e27e9d2011-09-16 01:13:47 +0200726 fec->eth = (struct ethernet_regs *)base_addr;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400727 fec->bd = bd;
728
Marek Vasut392b8502011-09-11 18:05:33 +0000729 fec->xcv_type = CONFIG_FEC_XCV_TYPE;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400730
731 /* Reset chip. */
John Rigbycb17b922010-01-25 23:12:55 -0700732 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl);
Marek Vasute382fb42011-09-11 18:05:37 +0000733 start = get_timer(0);
734 while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) {
735 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
736 printf("FEC MXC: Timeout reseting chip\n");
737 goto err3;
738 }
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400739 udelay(10);
Marek Vasute382fb42011-09-11 18:05:37 +0000740 }
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400741
742 /*
743 * Set interrupt mask register
744 */
745 writel(0x00000000, &fec->eth->imask);
746
747 /*
748 * Clear FEC-Lite interrupt event register(IEVENT)
749 */
750 writel(0xffffffff, &fec->eth->ievent);
751
752 /*
753 * Set FEC-Lite receive control register(R_CNTRL):
754 */
755 /*
756 * Frame length=1518; MII mode;
757 */
Marek Vasut9eb37702011-09-11 18:05:31 +0000758 writel((PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT) | FEC_RCNTRL_FCE |
759 FEC_RCNTRL_MII_MODE, &fec->eth->r_cntrl);
Stefano Babic4294b242010-02-01 14:51:30 +0100760 fec_mii_setspeed(fec);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400761
Marek Vasut9e27e9d2011-09-16 01:13:47 +0200762 if (dev_id == -1) {
763 sprintf(edev->name, "FEC");
764 fec->dev_id = 0;
765 } else {
766 sprintf(edev->name, "FEC%i", dev_id);
767 fec->dev_id = dev_id;
768 }
769 fec->phy_id = phy_id;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400770
771 miiphy_register(edev->name, fec_miiphy_read, fec_miiphy_write);
772
773 eth_register(edev);
774
Stefano Babic4294b242010-02-01 14:51:30 +0100775 if (fec_get_hwaddr(edev, ethaddr) == 0) {
Marek Vasut17fb2682011-09-11 18:05:38 +0000776 debug("got MAC address from fuse: %pM\n", ethaddr);
Stefano Babic4294b242010-02-01 14:51:30 +0100777 memcpy(edev->enetaddr, ethaddr, 6);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400778 }
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400779
Marek Vasute382fb42011-09-11 18:05:37 +0000780 return ret;
781
782err3:
783 free(fec);
784err2:
785 free(edev);
786err1:
787 return ret;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400788}
789
Marek Vasut9e27e9d2011-09-16 01:13:47 +0200790#ifndef CONFIG_FEC_MXC_MULTI
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400791int fecmxc_initialize(bd_t *bd)
792{
793 int lout = 1;
794
795 debug("eth_init: fec_probe(bd)\n");
Marek Vasut9e27e9d2011-09-16 01:13:47 +0200796 lout = fec_probe(bd, -1, CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
797
798 return lout;
799}
800#endif
801
802int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr)
803{
804 int lout = 1;
805
806 debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr);
807 lout = fec_probe(bd, dev_id, phy_id, addr);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400808
809 return lout;
810}
Marek Vasut2e5f4422011-09-11 18:05:36 +0000811
812int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int))
813{
814 struct fec_priv *fec = (struct fec_priv *)dev->priv;
815 fec->mii_postcall = cb;
816 return 0;
817}