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Stefan Roese5568e612005-11-22 13:20:42 +01001/*
Stefan Roese62534be2006-03-17 10:28:24 +01002 * (C) Copyright 2005-2006
Stefan Roese5568e612005-11-22 13:20:42 +01003 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
6 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02007 * SPDX-License-Identifier: GPL-2.0+
Stefan Roese5568e612005-11-22 13:20:42 +01008 */
9
10/************************************************************************
11 * board/config_p3p440.h - configuration for Prodrive P3P440
12 ***********************************************************************/
13
14#ifndef __CONFIG_H
15#define __CONFIG_H
16
17/*-----------------------------------------------------------------------
18 * High Level Configuration Options
19 *----------------------------------------------------------------------*/
20#define CONFIG_P3P440 1 /* Board is P3P440 */
21#define CONFIG_440GP 1 /* Specifc GP support */
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +020022#define CONFIG_440 1 /* ... PPC440 family */
Stefan Roese5568e612005-11-22 13:20:42 +010023#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
24#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
Wolfgang Denk2ae18242010-10-06 09:05:45 +020025
26#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
27
Stefan Roese5568e612005-11-22 13:20:42 +010028#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
29
30/*-----------------------------------------------------------------------
31 * Base addresses -- Note these are effective addresses where the
32 * actual resources get mapped (not physical addresses)
33 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020034#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
35#define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH */
36#define CONFIG_SYS_MONITOR_BASE 0xfffc0000 /* start of monitor */
37#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020038#define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */
39#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
Stefan Roese5568e612005-11-22 13:20:42 +010040
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020041#define CONFIG_SYS_USB_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000000)
Stefan Roese5568e612005-11-22 13:20:42 +010042
43/*-----------------------------------------------------------------------
44 * Initial RAM & stack pointer (placed in internal SRAM)
45 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020046#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */
Wolfgang Denk553f0982010-10-26 13:32:32 +020047#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
Stefan Roese5568e612005-11-22 13:20:42 +010048
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +020049#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020050#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Stefan Roese5568e612005-11-22 13:20:42 +010051
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020052#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/
53#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/
Stefan Roese5568e612005-11-22 13:20:42 +010054
55/*-----------------------------------------------------------------------
56 * DDR SDRAM
57 *----------------------------------------------------------------------*/
58#define CONFIG_SDRAM_BANK0 1 /* init onboard DDR SDRAM bank 0*/
Stefan Roese62534be2006-03-17 10:28:24 +010059#define CONFIG_SDRAM_ECC /* enable ECC support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020060#define CONFIG_SYS_SDRAM_TABLE { \
Stefan Roese62534be2006-03-17 10:28:24 +010061 {(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4)*/ \
62 {(64 << 20), 12, 0x00082001}} /* 64MB mode 2, 12x9(4) */
Stefan Roese5568e612005-11-22 13:20:42 +010063
64/*-----------------------------------------------------------------------
65 * Serial Port
66 *----------------------------------------------------------------------*/
Stefan Roese550650d2010-09-20 16:05:31 +020067#define CONFIG_CONS_INDEX 1 /* Use UART0 */
68#define CONFIG_SYS_NS16550
69#define CONFIG_SYS_NS16550_SERIAL
70#define CONFIG_SYS_NS16550_REG_SIZE 1
71#define CONFIG_SYS_NS16550_CLK get_serial_clock()
72
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020073#undef CONFIG_SYS_EXT_SERIAL_CLOCK
Stefan Roese5568e612005-11-22 13:20:42 +010074#define CONFIG_BAUDRATE 115200
75
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020076#define CONFIG_SYS_BAUDRATE_TABLE \
Stefan Roese5568e612005-11-22 13:20:42 +010077 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
78 57600, 115200, 230400, 460800, 921600 }
79
80/*-----------------------------------------------------------------------
81 * I2C
82 *----------------------------------------------------------------------*/
Dirk Eibach880540d2013-04-25 02:40:01 +000083#define CONFIG_SYS_I2C
84#define CONFIG_SYS_I2C_PPC4XX
85#define CONFIG_SYS_I2C_PPC4XX_CH0
86#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
87#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
88#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* Don't probe these addrs */
Stefan Roese5568e612005-11-22 13:20:42 +010089
90/*-----------------------------------------------------------------------
91 * I2C RTC
92 *----------------------------------------------------------------------*/
93#define CONFIG_RTC_MAX6900 1 /* MAX6900 RTC */
94
95/*-----------------------------------------------------------------------
96 * I2C EEPROM (PCF8594C) for environment
97 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020098#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 /* EEPROM PCF8594C */
99#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
Stefan Roese5568e612005-11-22 13:20:42 +0100100/* mask of address bits that overflow into the "EEPROM chip address" */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
102#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 /* The Philips PCF8594C has */
Stefan Roese5568e612005-11-22 13:20:42 +0100103 /* 8 byte page write mode using */
104 /* last 3 bits of the address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200105#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 40 /* and takes up to 40 msec */
Stefan Roese5568e612005-11-22 13:20:42 +0100106
107/*-----------------------------------------------------------------------
108 * Default configuration (environment varibles...)
109 *----------------------------------------------------------------------*/
110#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +0100111 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
Stefan Roese5568e612005-11-22 13:20:42 +0100112 "echo"
113
114#undef CONFIG_BOOTARGS
115
116#define CONFIG_EXTRA_ENV_SETTINGS \
117 "netdev=eth0\0" \
118 "hostname=p3p440\0" \
119 "nfsargs=setenv bootargs root=/dev/nfs rw " \
120 "nfsroot=${serverip}:${rootpath}\0" \
121 "ramargs=setenv bootargs root=/dev/ram rw\0" \
122 "addip=setenv bootargs ${bootargs} " \
123 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
124 ":${hostname}:${netdev}:off panic=1\0" \
125 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
126 "flash_nfs=run nfsargs addip addtty;" \
127 "bootm ${kernel_addr}\0" \
128 "flash_self=run ramargs addip addtty;" \
129 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
130 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
Wolfgang Denk93e14592013-10-04 17:43:24 +0200131 "bootm\0" \
Stefan Roese5568e612005-11-22 13:20:42 +0100132 "rootpath=/opt/eldk/ppc_4xx\0" \
133 "bootfile=/tftpboot/p3p440/uImage\0" \
134 "kernel_addr=ff800000\0" \
135 "ramdisk_addr=ff810000\0" \
136 "load=tftp 100000 /tftpboot/p3p440/u-boot.bin\0" \
137 "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
138 "cp.b 100000 fffc0000 40000;" \
139 "setenv filesize;saveenv\0" \
Detlev Zundeld8ab58b2008-03-06 16:45:53 +0100140 "upd=run load update\0" \
Stefan Roese2662b402006-04-01 13:41:03 +0200141 "unlock=yes\0" \
Stefan Roese5568e612005-11-22 13:20:42 +0100142 ""
143#define CONFIG_BOOTCOMMAND "run net_nfs"
144
145#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
146
147#define CONFIG_BAUDRATE 115200
148
149#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Stefan Roese5568e612005-11-22 13:20:42 +0100151
Ben Warren96e21f82008-10-27 23:50:15 -0700152#define CONFIG_PPC4xx_EMAC
Stefan Roese5568e612005-11-22 13:20:42 +0100153#define CONFIG_MII 1 /* MII PHY management */
154#define CONFIG_PHY_ADDR 0x1c /* PHY address */
155#define CONFIG_HAS_ETH1
156#define CONFIG_PHY1_ADDR 0x1d /* EMAC1 PHY address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
Stefan Roese5568e612005-11-22 13:20:42 +0100158
159#define CONFIG_NETCONSOLE /* include NetConsole support */
160
Stefan Roese5568e612005-11-22 13:20:42 +0100161
Jon Loeliger26a34562007-07-04 22:33:17 -0500162/*
Jon Loeliger079a1362007-07-10 10:12:10 -0500163 * BOOTP options
164 */
165#define CONFIG_BOOTP_BOOTFILESIZE
166#define CONFIG_BOOTP_BOOTPATH
167#define CONFIG_BOOTP_GATEWAY
168#define CONFIG_BOOTP_HOSTNAME
169
170
171/*
Jon Loeliger26a34562007-07-04 22:33:17 -0500172 * Command line configuration.
173 */
Jon Loeliger26a34562007-07-04 22:33:17 -0500174#define CONFIG_CMD_ASKENV
175#define CONFIG_CMD_DATE
176#define CONFIG_CMD_DHCP
177#define CONFIG_CMD_DIAG
178#define CONFIG_CMD_ELF
179#define CONFIG_CMD_I2C
180#define CONFIG_CMD_IRQ
181#define CONFIG_CMD_MII
Jon Loeliger26a34562007-07-04 22:33:17 -0500182#define CONFIG_CMD_PCI
183#define CONFIG_CMD_PING
184#define CONFIG_CMD_REGINFO
185#define CONFIG_CMD_EEPROM
186#define CONFIG_CMD_SNTP
187
Stefan Roese5568e612005-11-22 13:20:42 +0100188
189#undef CONFIG_WATCHDOG /* watchdog disabled */
190
191/*-----------------------------------------------------------------------
192 * Miscellaneous configurable options
193 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_SYS_LONGHELP /* undef to save memory */
Jon Loeliger26a34562007-07-04 22:33:17 -0500195#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Stefan Roese5568e612005-11-22 13:20:42 +0100197#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Stefan Roese5568e612005-11-22 13:20:42 +0100199#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200200#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
201#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
202#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Stefan Roese5568e612005-11-22 13:20:42 +0100203
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
205#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
Stefan Roese5568e612005-11-22 13:20:42 +0100206
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
208#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
Stefan Roese5568e612005-11-22 13:20:42 +0100209
Stefan Roese5568e612005-11-22 13:20:42 +0100210#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
211#define CONFIG_LOOPW 1 /* enable loopw command */
212#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
213#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
214
215/*-----------------------------------------------------------------------
216 * PCI stuff
217 *----------------------------------------------------------------------*/
218/* General PCI */
219#define CONFIG_PCI /* include pci support */
Gabor Juhos842033e2013-05-30 07:06:12 +0000220#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
Stefan Roese5568e612005-11-22 13:20:42 +0100221#define CONFIG_PCI_PNP /* do pci plug-and-play */
222#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
Stefan Roese5568e612005-11-22 13:20:42 +0100224
225/* Board-specific PCI */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */
Stefan Roese5568e612005-11-22 13:20:42 +0100227
228#define CONFIG_DISABLE_PISE_TEST /* disable PISE test (PCIX only)*/
229
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200230#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
231#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
Stefan Roese5568e612005-11-22 13:20:42 +0100232
233/*-----------------------------------------------------------------------
234 * External Bus Controller (EBC) Setup
235 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200236#define CONFIG_SYS_FLASH0 0xFF800000
237#define CONFIG_SYS_FLASH1 0xFF000000
238#define CONFIG_SYS_FLASH2 0xFE800000
239#define CONFIG_SYS_FLASH3 0xFE000000
240#define CONFIG_SYS_USB 0xF0000000
Stefan Roese5568e612005-11-22 13:20:42 +0100241
242/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243#define CONFIG_SYS_EBC_PB0AP 0x03050200
244#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH0 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */
Stefan Roese5568e612005-11-22 13:20:42 +0100245
246/* Memory Bank 1 (Flash Bank 1, NOR-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200247#define CONFIG_SYS_EBC_PB1AP 0x03050200
248#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_FLASH1 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */
Stefan Roese5568e612005-11-22 13:20:42 +0100249
250/* Memory Bank 2 (Flash Bank 2, NOR-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251#define CONFIG_SYS_EBC_PB2AP 0x03050200
252#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FLASH2 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */
Stefan Roese5568e612005-11-22 13:20:42 +0100253
254/* Memory Bank 3 (Flash Bank 3, NOR-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200255#define CONFIG_SYS_EBC_PB3AP 0x03050200
256#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_FLASH3 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */
Stefan Roese5568e612005-11-22 13:20:42 +0100257
258/* Memory Bank 7 (USB controller) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200259#define CONFIG_SYS_EBC_PB7AP 0x02015000
260#define CONFIG_SYS_EBC_PB7CR (CONFIG_SYS_USB | 0xFE000) /* BAS=0xF00,BS=128MB,BU=R/W,BW=16bit*/
Stefan Roese5568e612005-11-22 13:20:42 +0100261
262/*-----------------------------------------------------------------------
263 * FLASH related
264 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200265#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200266#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
Stefan Roese5568e612005-11-22 13:20:42 +0100267
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200268#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH3, CONFIG_SYS_FLASH2, CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
Stefan Roese5568e612005-11-22 13:20:42 +0100269
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200270#define CONFIG_SYS_MAX_FLASH_BANKS 4 /* max number of memory banks */
271#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
Stefan Roese5568e612005-11-22 13:20:42 +0100272
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200273#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
274#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
Stefan Roese5568e612005-11-22 13:20:42 +0100275
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200276#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
277#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */
Stefan Roese62534be2006-03-17 10:28:24 +0100278
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
280#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
Stefan Roese5568e612005-11-22 13:20:42 +0100281
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200282#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
Stefan Roese5568e612005-11-22 13:20:42 +0100283
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200284#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200285#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200286#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
Stefan Roese5568e612005-11-22 13:20:42 +0100287
288/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200289#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
290#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Stefan Roese5568e612005-11-22 13:20:42 +0100291
292/*
293 * For booting Linux, the board info and command line data
294 * have to be in the first 8 MB of memory, since this is
295 * the maximum mapped by the Linux kernel during initialization.
296 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200297#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Stefan Roese5568e612005-11-22 13:20:42 +0100298
Jon Loeliger26a34562007-07-04 22:33:17 -0500299#if defined(CONFIG_CMD_KGDB)
Stefan Roese5568e612005-11-22 13:20:42 +0100300#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Stefan Roese5568e612005-11-22 13:20:42 +0100301#endif
302#endif /* __CONFIG_H */