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Xiangfu Liu3c945542011-10-12 12:24:06 +08001/*
2 * Authors: Xiangfu Liu <xiangfu.z@gmail.com>
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 3 of the License, or (at your option) any later version.
8 */
9
10#ifndef __CONFIG_QI_LB60_H
11#define __CONFIG_QI_LB60_H
12
13#define CONFIG_MIPS32 /* MIPS32 CPU core */
Daniel Schwierzeck2c0e3de2012-08-21 23:27:37 +020014#define CONFIG_SYS_LITTLE_ENDIAN
Xiangfu Liu3c945542011-10-12 12:24:06 +080015#define CONFIG_JZSOC /* Jz SoC */
16#define CONFIG_JZ4740 /* Jz4740 SoC */
17#define CONFIG_NAND_JZ4740
18
19#define CONFIG_SYS_CPU_SPEED 336000000 /* CPU clock: 336 MHz */
20#define CONFIG_SYS_EXTAL 12000000 /* EXTAL freq: 12 MHz */
21#define CONFIG_SYS_HZ (CONFIG_SYS_EXTAL / 256) /* incrementer freq */
22#define CONFIG_SYS_MIPS_TIMER_FREQ CONFIG_SYS_CPU_SPEED
23
24#define CONFIG_SYS_UART_BASE JZ4740_UART0_BASE /* Base of the UART channel */
25#define CONFIG_BAUDRATE 57600
Xiangfu Liu3c945542011-10-12 12:24:06 +080026
27#define CONFIG_SKIP_LOWLEVEL_INIT
28#define CONFIG_BOARD_EARLY_INIT_F
29#define CONFIG_SYS_NO_FLASH
30#define CONFIG_SYS_FLASH_BASE 0 /* init flash_base as 0 */
31#define CONFIG_ENV_OVERWRITE
32
33#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAUL)
34#define CONFIG_BOOTDELAY 0
35#define CONFIG_BOOTARGS "mem=32M console=tty0 console=ttyS0,57600n8 ubi.mtd=2 rootfstype=ubifs root=ubi0:rootfs rw rootwait"
36#define CONFIG_BOOTCOMMAND "nand read 0x80600000 0x400000 0x200000;bootm"
37
38/*
39 * Command line configuration.
40 */
41#define CONFIG_CMD_BOOTD /* bootd */
42#define CONFIG_CMD_CONSOLE /* coninfo */
43#define CONFIG_CMD_ECHO /* echo arguments */
44
45#define CONFIG_CMD_LOADB /* loadb */
46#define CONFIG_CMD_LOADS /* loads */
47#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */
48#define CONFIG_CMD_MISC /* Misc functions like sleep etc*/
49#define CONFIG_CMD_RUN /* run command in env variable */
50#define CONFIG_CMD_SAVEENV /* saveenv */
51#define CONFIG_CMD_SETGETDCR /* DCR support on 4xx */
52#define CONFIG_CMD_SOURCE /* "source" command support */
53#define CONFIG_CMD_NAND
54
55/*
56 * Serial download configuration
57 */
58#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
59
60/*
61 * Miscellaneous configurable options
62 */
63#define CONFIG_SYS_MAXARGS 16
64#define CONFIG_SYS_LONGHELP
65#define CONFIG_SYS_PROMPT "NanoNote# "
66#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
67#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
68
69#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
70#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024)
71
72#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
73#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
74#define CONFIG_SYS_LOAD_ADDR 0x80600000
75#define CONFIG_SYS_MEMTEST_START 0x80100000
76#define CONFIG_SYS_MEMTEST_END 0x80800000
77
78/*
79 * Environment
80 */
81#define CONFIG_ENV_IS_IN_NAND /* use NAND for environment vars */
82
83#define CONFIG_SYS_NAND_5_ADDR_CYCLE
84/*
85 * if board nand flash is 1GB, set to 1
86 * if board nand flash is 2GB, set to 2
87 * for change the PAGE_SIZE and BLOCK_SIZE
88 * will delete when there is no 1GB flash
89 */
90#define NANONOTE_NAND_SIZE 2
91
92#define CONFIG_SYS_NAND_PAGE_SIZE (2048 * NANONOTE_NAND_SIZE)
93#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * NANONOTE_NAND_SIZE << 10)
94/* nand bad block was marked at this page in a block, start from 0 */
95#define CONFIG_SYS_NAND_BADBLOCK_PAGE 127
96#define CONFIG_SYS_NAND_PAGE_COUNT 128
97#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
98/* ECC offset position in oob area, default value is 6 if it isn't defined */
99#define CONFIG_SYS_NAND_ECC_POS (6 * NANONOTE_NAND_SIZE)
100#define CONFIG_SYS_NAND_ECCSIZE 512
101#define CONFIG_SYS_NAND_ECCBYTES 9
Xiangfu Liu3c945542011-10-12 12:24:06 +0800102#define CONFIG_SYS_NAND_ECCPOS \
103 {12, 13, 14, 15, 16, 17, 18, 19,\
104 20, 21, 22, 23, 24, 25, 26, 27, \
105 28, 29, 30, 31, 32, 33, 34, 35, \
106 36, 37, 38, 39, 40, 41, 42, 43, \
107 44, 45, 46, 47, 48, 49, 50, 51, \
108 52, 53, 54, 55, 56, 57, 58, 59, \
109 60, 61, 62, 63, 64, 65, 66, 67, \
110 68, 69, 70, 71, 72, 73, 74, 75, \
111 76, 77, 78, 79, 80, 81, 82, 83}
112
113#define CONFIG_SYS_NAND_OOBSIZE 128
114#define CONFIG_SYS_NAND_BASE 0xB8000000
115#define CONFIG_SYS_ONENAND_BASE CONFIG_SYS_NAND_BASE
Xiangfu Liu3c945542011-10-12 12:24:06 +0800116#define CONFIG_SYS_MAX_NAND_DEVICE 1
117#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl.*/
118#define CONFIG_NAND_SPL_TEXT_BASE 0x80000000
119
120/*
121 * IPL (Initial Program Loader, integrated inside CPU)
122 * Will load first 8k from NAND (SPL) into cache and execute it from there.
123 *
124 * SPL (Secondary Program Loader)
125 * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
126 * has to fit into 8kByte. It sets up the CPU and configures the SDRAM
127 * controller and the NAND controller so that the special U-Boot image can be
128 * loaded from NAND to SDRAM.
129 *
130 * NUB (NAND U-Boot)
131 * This NAND U-Boot (NUB) is a special U-Boot version which can be started
132 * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
133 *
134 */
135#define CONFIG_SYS_NAND_U_BOOT_DST 0x80100000 /* Load NUB to this addr */
136#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
137/* Start NUB from this addr*/
138
139/*
140 * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
141 */
142#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) /* Offset to RAM U-Boot image */
143#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) /* Size of RAM U-Boot image */
144
145#define CONFIG_ENV_SIZE (4 << 10)
146#define CONFIG_ENV_OFFSET \
147 (CONFIG_SYS_NAND_BLOCK_SIZE + CONFIG_SYS_NAND_U_BOOT_SIZE)
148#define CONFIG_ENV_OFFSET_REDUND \
149 (CONFIG_ENV_OFFSET + CONFIG_SYS_NAND_BLOCK_SIZE)
150
151#define CONFIG_SYS_TEXT_BASE 0x80100000
152#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
153
154/*
155 * SDRAM Info.
156 */
157#define CONFIG_NR_DRAM_BANKS 1
158
159/*
160 * Cache Configuration
161 */
162#define CONFIG_SYS_DCACHE_SIZE 16384
163#define CONFIG_SYS_ICACHE_SIZE 16384
164#define CONFIG_SYS_CACHELINE_SIZE 32
165
166/*
167 * GPIO definition
168 */
169#define GPIO_LCD_CS (2 * 32 + 21)
170#define GPIO_AMP_EN (3 * 32 + 4)
171
172#define GPIO_SDPW_EN (3 * 32 + 2)
173#define GPIO_SD_DETECT (3 * 32 + 0)
174
175#define GPIO_BUZZ_PWM (3 * 32 + 27)
176#define GPIO_USB_DETECT (3 * 32 + 28)
177
178#define GPIO_AUDIO_POP (1 * 32 + 29)
179#define GPIO_COB_TEST (1 * 32 + 30)
180
181#define GPIO_KEYOUT_BASE (2 * 32 + 10)
182#define GPIO_KEYIN_BASE (3 * 32 + 18)
183#define GPIO_KEYIN_8 (3 * 32 + 26)
184
185#define GPIO_SD_CD_N GPIO_SD_DETECT /* SD Card insert detect */
186#define GPIO_SD_VCC_EN_N GPIO_SDPW_EN /* SD Card Power Enable */
187
188#define SPEN GPIO_LCD_CS /* LCDCS :Serial command enable */
189#define SPDA (2 * 32 + 22) /* LCDSCL:Serial command clock input */
190#define SPCK (2 * 32 + 23) /* LCDSDA:Serial command data input */
191
192/* SDRAM paramters */
193#define SDRAM_BW16 1 /* Data bus width: 0-32bit, 1-16bit */
194#define SDRAM_BANK4 1 /* Banks each chip: 0-2bank, 1-4bank */
195#define SDRAM_ROW 13 /* Row address: 11 to 13 */
196#define SDRAM_COL 9 /* Column address: 8 to 12 */
197#define SDRAM_CASL 2 /* CAS latency: 2 or 3 */
198
199/* SDRAM Timings, unit: ns */
200#define SDRAM_TRAS 45 /* RAS# Active Time */
201#define SDRAM_RCD 20 /* RAS# to CAS# Delay */
202#define SDRAM_TPC 20 /* RAS# Precharge Time */
203#define SDRAM_TRWL 7 /* Write Latency Time */
204#define SDRAM_TREF 15625 /* Refresh period: 8192 cycles/64ms */
205
206#endif