Piotr Wilczek | 4d6c967 | 2013-09-20 15:01:27 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2013 Samsung Electronics Co., Ltd. All rights reserved. |
| 3 | * Sanghee Kim <sh0130.kim@samsung.com> |
| 4 | * Piotr Wilczek <p.wilczek@samsung.com> |
| 5 | * |
| 6 | * SPDX-License-Identifier: GPL-2.0+ |
| 7 | */ |
| 8 | |
| 9 | #include <common.h> |
| 10 | #include <lcd.h> |
| 11 | #include <asm/io.h> |
| 12 | #include <asm/arch/gpio.h> |
| 13 | #include <asm/arch/mmc.h> |
| 14 | #include <asm/arch/power.h> |
| 15 | #include <asm/arch/clk.h> |
| 16 | #include <asm/arch/clock.h> |
| 17 | #include <asm/arch/mipi_dsim.h> |
| 18 | #include <asm/arch/pinmux.h> |
| 19 | #include <asm/arch/power.h> |
| 20 | #include <power/pmic.h> |
| 21 | #include <power/max77686_pmic.h> |
| 22 | #include <power/battery.h> |
| 23 | #include <power/max77693_pmic.h> |
| 24 | #include <power/max77693_muic.h> |
| 25 | #include <power/max77693_fg.h> |
| 26 | #include <libtizen.h> |
| 27 | #include <errno.h> |
Piotr Wilczek | ab8efbb | 2013-11-21 15:46:45 +0100 | [diff] [blame] | 28 | #include <usb.h> |
| 29 | #include <usb/s3c_udc.h> |
| 30 | #include <usb_mass_storage.h> |
Piotr Wilczek | 4d6c967 | 2013-09-20 15:01:27 +0200 | [diff] [blame] | 31 | |
| 32 | DECLARE_GLOBAL_DATA_PTR; |
| 33 | |
| 34 | static struct exynos4x12_gpio_part1 *gpio1; |
| 35 | static struct exynos4x12_gpio_part2 *gpio2; |
| 36 | |
| 37 | static unsigned int board_rev = -1; |
| 38 | |
| 39 | static inline u32 get_model_rev(void); |
| 40 | |
| 41 | static void check_hw_revision(void) |
| 42 | { |
| 43 | int modelrev = 0; |
| 44 | int i; |
| 45 | |
| 46 | gpio2 = (struct exynos4x12_gpio_part2 *)EXYNOS4X12_GPIO_PART2_BASE; |
| 47 | |
| 48 | /* |
| 49 | * GPM1[1:0]: MODEL_REV[1:0] |
| 50 | * Don't set as pull-none for these N/C pin. |
| 51 | * TRM say that it may cause unexcepted state and leakage current. |
| 52 | * and pull-none is only for output function. |
| 53 | */ |
| 54 | for (i = 0; i < 2; i++) |
| 55 | s5p_gpio_cfg_pin(&gpio2->m1, i, GPIO_INPUT); |
| 56 | |
| 57 | /* GPM1[5:2]: HW_REV[3:0] */ |
| 58 | for (i = 2; i < 6; i++) { |
| 59 | s5p_gpio_cfg_pin(&gpio2->m1, i, GPIO_INPUT); |
| 60 | s5p_gpio_set_pull(&gpio2->m1, i, GPIO_PULL_NONE); |
| 61 | } |
| 62 | |
| 63 | /* GPM1[1:0]: MODEL_REV[1:0] */ |
| 64 | for (i = 0; i < 2; i++) |
| 65 | modelrev |= (s5p_gpio_get_value(&gpio2->m1, i) << i); |
| 66 | |
| 67 | /* board_rev[15:8] = model */ |
| 68 | board_rev = modelrev << 8; |
| 69 | } |
| 70 | |
| 71 | #ifdef CONFIG_DISPLAY_BOARDINFO |
| 72 | int checkboard(void) |
| 73 | { |
| 74 | puts("Board:\tTRATS2\n"); |
| 75 | return 0; |
| 76 | } |
| 77 | #endif |
| 78 | |
| 79 | static void show_hw_revision(void) |
| 80 | { |
| 81 | printf("HW Revision:\t0x%04x\n", board_rev); |
| 82 | } |
| 83 | |
| 84 | u32 get_board_rev(void) |
| 85 | { |
| 86 | return board_rev; |
| 87 | } |
| 88 | |
| 89 | static inline u32 get_model_rev(void) |
| 90 | { |
| 91 | return (board_rev >> 8) & 0xff; |
| 92 | } |
| 93 | |
| 94 | static void board_external_gpio_init(void) |
| 95 | { |
| 96 | gpio2 = (struct exynos4x12_gpio_part2 *)EXYNOS4X12_GPIO_PART2_BASE; |
| 97 | |
| 98 | /* |
| 99 | * some pins which in alive block are connected with external pull-up |
| 100 | * but it's default setting is pull-down. |
| 101 | * if that pin set as input then that floated |
| 102 | */ |
| 103 | |
| 104 | s5p_gpio_set_pull(&gpio2->x0, 2, GPIO_PULL_NONE); /* PS_ALS_INT */ |
| 105 | s5p_gpio_set_pull(&gpio2->x0, 4, GPIO_PULL_NONE); /* TSP_nINT */ |
| 106 | s5p_gpio_set_pull(&gpio2->x0, 7, GPIO_PULL_NONE); /* AP_PMIC_IRQ*/ |
| 107 | s5p_gpio_set_pull(&gpio2->x1, 5, GPIO_PULL_NONE); /* IF_PMIC_IRQ*/ |
| 108 | s5p_gpio_set_pull(&gpio2->x2, 0, GPIO_PULL_NONE); /* VOL_UP */ |
| 109 | s5p_gpio_set_pull(&gpio2->x2, 1, GPIO_PULL_NONE); /* VOL_DOWN */ |
| 110 | s5p_gpio_set_pull(&gpio2->x2, 3, GPIO_PULL_NONE); /* FUEL_ALERT */ |
| 111 | s5p_gpio_set_pull(&gpio2->x2, 4, GPIO_PULL_NONE); /* ADC_INT */ |
| 112 | s5p_gpio_set_pull(&gpio2->x2, 7, GPIO_PULL_NONE); /* nPOWER */ |
| 113 | s5p_gpio_set_pull(&gpio2->x3, 0, GPIO_PULL_NONE); /* WPC_INT */ |
| 114 | s5p_gpio_set_pull(&gpio2->x3, 5, GPIO_PULL_NONE); /* OK_KEY */ |
| 115 | s5p_gpio_set_pull(&gpio2->x3, 7, GPIO_PULL_NONE); /* HDMI_HPD */ |
| 116 | } |
| 117 | |
| 118 | #ifdef CONFIG_SYS_I2C_INIT_BOARD |
| 119 | static void board_init_i2c(void) |
| 120 | { |
| 121 | gpio1 = (struct exynos4x12_gpio_part1 *)EXYNOS4X12_GPIO_PART1_BASE; |
| 122 | gpio2 = (struct exynos4x12_gpio_part2 *)EXYNOS4X12_GPIO_PART2_BASE; |
| 123 | |
| 124 | /* I2C_7 */ |
| 125 | s5p_gpio_direction_output(&gpio1->d0, 2, 1); |
| 126 | s5p_gpio_direction_output(&gpio1->d0, 3, 1); |
| 127 | |
| 128 | /* I2C_8 */ |
| 129 | s5p_gpio_direction_output(&gpio1->f1, 4, 1); |
| 130 | s5p_gpio_direction_output(&gpio1->f1, 5, 1); |
| 131 | |
| 132 | /* I2C_9 */ |
| 133 | s5p_gpio_direction_output(&gpio2->m2, 1, 1); |
| 134 | s5p_gpio_direction_output(&gpio2->m2, 0, 1); |
| 135 | } |
| 136 | #endif |
| 137 | |
| 138 | int board_early_init_f(void) |
| 139 | { |
| 140 | check_hw_revision(); |
| 141 | board_external_gpio_init(); |
| 142 | |
| 143 | gd->flags |= GD_FLG_DISABLE_CONSOLE; |
| 144 | |
| 145 | return 0; |
| 146 | } |
| 147 | |
| 148 | static int pmic_init_max77686(void); |
| 149 | |
| 150 | int board_init(void) |
| 151 | { |
| 152 | struct exynos4_power *pwr = |
| 153 | (struct exynos4_power *)EXYNOS4X12_POWER_BASE; |
| 154 | |
| 155 | gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; |
| 156 | |
| 157 | /* workaround: clear INFORM4..5 */ |
| 158 | writel(0, (unsigned int)&pwr->inform4); |
| 159 | writel(0, (unsigned int)&pwr->inform5); |
| 160 | |
| 161 | return 0; |
| 162 | } |
| 163 | |
| 164 | int power_init_board(void) |
| 165 | { |
| 166 | int chrg; |
| 167 | struct power_battery *pb; |
| 168 | struct pmic *p_chrg, *p_muic, *p_fg, *p_bat; |
| 169 | |
| 170 | #ifdef CONFIG_SYS_I2C_INIT_BOARD |
| 171 | board_init_i2c(); |
| 172 | #endif |
| 173 | pmic_init(I2C_0); /* I2C adapter 0 - bus name I2C_5 */ |
| 174 | pmic_init_max77686(); |
| 175 | pmic_init_max77693(I2C_2); /* I2C adapter 2 - bus name I2C_10 */ |
| 176 | power_muic_init(I2C_2); /* I2C adapter 2 - bus name I2C_10 */ |
| 177 | power_fg_init(I2C_1); /* I2C adapter 1 - bus name I2C_9 */ |
| 178 | power_bat_init(0); |
| 179 | |
| 180 | p_chrg = pmic_get("MAX77693_PMIC"); |
| 181 | if (!p_chrg) { |
| 182 | puts("MAX77693_PMIC: Not found\n"); |
| 183 | return -ENODEV; |
| 184 | } |
| 185 | |
| 186 | p_muic = pmic_get("MAX77693_MUIC"); |
| 187 | if (!p_muic) { |
| 188 | puts("MAX77693_MUIC: Not found\n"); |
| 189 | return -ENODEV; |
| 190 | } |
| 191 | |
| 192 | p_fg = pmic_get("MAX77693_FG"); |
| 193 | if (!p_fg) { |
| 194 | puts("MAX17042_FG: Not found\n"); |
| 195 | return -ENODEV; |
| 196 | } |
| 197 | |
| 198 | if (p_chrg->chrg->chrg_bat_present(p_chrg) == 0) |
| 199 | puts("No battery detected\n"); |
| 200 | |
| 201 | p_bat = pmic_get("BAT_TRATS2"); |
| 202 | if (!p_bat) { |
| 203 | puts("BAT_TRATS2: Not found\n"); |
| 204 | return -ENODEV; |
| 205 | } |
| 206 | |
| 207 | p_fg->parent = p_bat; |
| 208 | p_chrg->parent = p_bat; |
| 209 | p_muic->parent = p_bat; |
| 210 | |
| 211 | p_bat->pbat->battery_init(p_bat, p_fg, p_chrg, p_muic); |
| 212 | |
| 213 | pb = p_bat->pbat; |
| 214 | chrg = p_muic->chrg->chrg_type(p_muic); |
| 215 | debug("CHARGER TYPE: %d\n", chrg); |
| 216 | |
| 217 | if (!p_chrg->chrg->chrg_bat_present(p_chrg)) { |
| 218 | puts("No battery detected\n"); |
| 219 | return -1; |
| 220 | } |
| 221 | |
| 222 | p_fg->fg->fg_battery_check(p_fg, p_bat); |
| 223 | |
| 224 | if (pb->bat->state == CHARGE && chrg == CHARGER_USB) |
| 225 | puts("CHARGE Battery !\n"); |
| 226 | |
| 227 | return 0; |
| 228 | } |
| 229 | |
| 230 | int dram_init(void) |
| 231 | { |
| 232 | u32 size_mb; |
| 233 | |
| 234 | size_mb = (get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) + |
| 235 | get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE) + |
| 236 | get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE) + |
| 237 | get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE)) >> 20; |
| 238 | |
| 239 | gd->ram_size = size_mb << 20; |
| 240 | |
| 241 | return 0; |
| 242 | } |
| 243 | |
| 244 | void dram_init_banksize(void) |
| 245 | { |
| 246 | gd->bd->bi_dram[0].start = PHYS_SDRAM_1; |
| 247 | gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; |
| 248 | gd->bd->bi_dram[1].start = PHYS_SDRAM_2; |
| 249 | gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; |
| 250 | gd->bd->bi_dram[2].start = PHYS_SDRAM_3; |
| 251 | gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; |
| 252 | gd->bd->bi_dram[3].start = PHYS_SDRAM_4; |
| 253 | gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; |
| 254 | } |
| 255 | |
| 256 | int board_mmc_init(bd_t *bis) |
| 257 | { |
| 258 | int err0, err2 = 0; |
| 259 | |
| 260 | gpio2 = (struct exynos4x12_gpio_part2 *)EXYNOS4X12_GPIO_PART2_BASE; |
| 261 | |
| 262 | /* eMMC_EN: SD_0_CDn: GPK0[2] Output High */ |
| 263 | s5p_gpio_direction_output(&gpio2->k0, 2, 1); |
| 264 | s5p_gpio_set_pull(&gpio2->k0, 2, GPIO_PULL_NONE); |
| 265 | |
| 266 | /* |
| 267 | * eMMC GPIO: |
| 268 | * SDR 8-bit@48MHz at MMC0 |
| 269 | * GPK0[0] SD_0_CLK(2) |
| 270 | * GPK0[1] SD_0_CMD(2) |
| 271 | * GPK0[2] SD_0_CDn -> Not used |
| 272 | * GPK0[3:6] SD_0_DATA[0:3](2) |
| 273 | * GPK1[3:6] SD_0_DATA[0:3](3) |
| 274 | * |
| 275 | * DDR 4-bit@26MHz at MMC4 |
| 276 | * GPK0[0] SD_4_CLK(3) |
| 277 | * GPK0[1] SD_4_CMD(3) |
| 278 | * GPK0[2] SD_4_CDn -> Not used |
| 279 | * GPK0[3:6] SD_4_DATA[0:3](3) |
| 280 | * GPK1[3:6] SD_4_DATA[4:7](4) |
| 281 | */ |
| 282 | |
| 283 | err0 = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE); |
| 284 | |
| 285 | /* |
| 286 | * MMC device init |
| 287 | * mmc0 : eMMC (8-bit buswidth) |
| 288 | * mmc2 : SD card (4-bit buswidth) |
| 289 | */ |
| 290 | if (err0) |
| 291 | debug("SDMMC0 not configured\n"); |
| 292 | else |
| 293 | err0 = s5p_mmc_init(0, 8); |
| 294 | |
| 295 | /* T-flash detect */ |
| 296 | s5p_gpio_cfg_pin(&gpio2->x3, 4, 0xf); |
| 297 | s5p_gpio_set_pull(&gpio2->x3, 4, GPIO_PULL_UP); |
| 298 | |
| 299 | /* |
| 300 | * Check the T-flash detect pin |
| 301 | * GPX3[4] T-flash detect pin |
| 302 | */ |
| 303 | if (!s5p_gpio_get_value(&gpio2->x3, 4)) { |
| 304 | err2 = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE); |
| 305 | if (err2) |
| 306 | debug("SDMMC2 not configured\n"); |
| 307 | else |
| 308 | err2 = s5p_mmc_init(2, 4); |
| 309 | } |
| 310 | |
| 311 | return err0 & err2; |
| 312 | } |
| 313 | |
Piotr Wilczek | ab8efbb | 2013-11-21 15:46:45 +0100 | [diff] [blame] | 314 | #ifdef CONFIG_USB_GADGET |
| 315 | static int s5pc210_phy_control(int on) |
| 316 | { |
| 317 | int ret = 0; |
| 318 | unsigned int val; |
| 319 | struct pmic *p, *p_pmic, *p_muic; |
| 320 | |
| 321 | p_pmic = pmic_get("MAX77686_PMIC"); |
| 322 | if (!p_pmic) |
| 323 | return -ENODEV; |
| 324 | |
| 325 | if (pmic_probe(p_pmic)) |
| 326 | return -1; |
| 327 | |
| 328 | p_muic = pmic_get("MAX77693_MUIC"); |
| 329 | if (!p_muic) |
| 330 | return -ENODEV; |
| 331 | |
| 332 | if (pmic_probe(p_muic)) |
| 333 | return -1; |
| 334 | |
| 335 | if (on) { |
| 336 | ret = max77686_set_ldo_mode(p_pmic, 12, OPMODE_ON); |
| 337 | if (ret) |
| 338 | return -1; |
| 339 | |
| 340 | p = pmic_get("MAX77693_PMIC"); |
| 341 | if (!p) |
| 342 | return -ENODEV; |
| 343 | |
| 344 | if (pmic_probe(p)) |
| 345 | return -1; |
| 346 | |
| 347 | /* SAFEOUT */ |
| 348 | ret = pmic_reg_read(p, MAX77693_SAFEOUT, &val); |
| 349 | if (ret) |
| 350 | return -1; |
| 351 | |
| 352 | val |= MAX77693_ENSAFEOUT1; |
| 353 | ret = pmic_reg_write(p, MAX77693_SAFEOUT, val); |
| 354 | if (ret) |
| 355 | return -1; |
| 356 | |
| 357 | /* PATH: USB */ |
| 358 | ret = pmic_reg_write(p_muic, MAX77693_MUIC_CONTROL1, |
| 359 | MAX77693_MUIC_CTRL1_DN1DP2); |
| 360 | |
| 361 | } else { |
| 362 | ret = max77686_set_ldo_mode(p_pmic, 12, OPMODE_LPM); |
| 363 | if (ret) |
| 364 | return -1; |
| 365 | |
| 366 | /* PATH: UART */ |
| 367 | ret = pmic_reg_write(p_muic, MAX77693_MUIC_CONTROL1, |
| 368 | MAX77693_MUIC_CTRL1_UT1UR2); |
| 369 | } |
| 370 | |
| 371 | if (ret) |
| 372 | return -1; |
| 373 | |
| 374 | return 0; |
| 375 | } |
| 376 | |
| 377 | struct s3c_plat_otg_data s5pc210_otg_data = { |
| 378 | .phy_control = s5pc210_phy_control, |
| 379 | .regs_phy = EXYNOS4X12_USBPHY_BASE, |
| 380 | .regs_otg = EXYNOS4X12_USBOTG_BASE, |
| 381 | .usb_phy_ctrl = EXYNOS4X12_USBPHY_CONTROL, |
| 382 | .usb_flags = PHY0_SLEEP, |
| 383 | }; |
| 384 | |
| 385 | int board_usb_init(int index, enum usb_init_type init) |
| 386 | { |
| 387 | debug("USB_udc_probe\n"); |
| 388 | return s3c_udc_probe(&s5pc210_otg_data); |
| 389 | } |
| 390 | |
| 391 | #ifdef CONFIG_USB_CABLE_CHECK |
| 392 | int usb_cable_connected(void) |
| 393 | { |
| 394 | struct pmic *muic = pmic_get("MAX77693_MUIC"); |
| 395 | if (!muic) |
| 396 | return 0; |
| 397 | |
| 398 | return !!muic->chrg->chrg_type(muic); |
| 399 | } |
| 400 | #endif |
| 401 | #endif |
| 402 | |
Piotr Wilczek | 4d6c967 | 2013-09-20 15:01:27 +0200 | [diff] [blame] | 403 | static int pmic_init_max77686(void) |
| 404 | { |
| 405 | struct pmic *p = pmic_get("MAX77686_PMIC"); |
| 406 | |
| 407 | if (pmic_probe(p)) |
| 408 | return -1; |
| 409 | |
| 410 | /* BUCK/LDO Output Voltage */ |
| 411 | max77686_set_ldo_voltage(p, 21, 2800000); /* LDO21 VTF_2.8V */ |
| 412 | max77686_set_ldo_voltage(p, 23, 3300000); /* LDO23 TSP_AVDD_3.3V*/ |
| 413 | max77686_set_ldo_voltage(p, 24, 1800000); /* LDO24 TSP_VDD_1.8V */ |
| 414 | |
| 415 | /* BUCK/LDO Output Mode */ |
| 416 | max77686_set_buck_mode(p, 1, OPMODE_STANDBY); /* BUCK1 VMIF_1.1V_AP */ |
| 417 | max77686_set_buck_mode(p, 2, OPMODE_ON); /* BUCK2 VARM_1.0V_AP */ |
| 418 | max77686_set_buck_mode(p, 3, OPMODE_ON); /* BUCK3 VINT_1.0V_AP */ |
| 419 | max77686_set_buck_mode(p, 4, OPMODE_ON); /* BUCK4 VG3D_1.0V_AP */ |
| 420 | max77686_set_buck_mode(p, 5, OPMODE_ON); /* BUCK5 VMEM_1.2V_AP */ |
| 421 | max77686_set_buck_mode(p, 6, OPMODE_ON); /* BUCK6 VCC_SUB_1.35V*/ |
| 422 | max77686_set_buck_mode(p, 7, OPMODE_ON); /* BUCK7 VCC_SUB_2.0V */ |
| 423 | max77686_set_buck_mode(p, 8, OPMODE_OFF); /* VMEM_VDDF_2.85V */ |
| 424 | max77686_set_buck_mode(p, 9, OPMODE_OFF); /* CAM_ISP_CORE_1.2V*/ |
| 425 | |
| 426 | max77686_set_ldo_mode(p, 1, OPMODE_LPM); /* LDO1 VALIVE_1.0V_AP*/ |
| 427 | max77686_set_ldo_mode(p, 2, OPMODE_STANDBY); /* LDO2 VM1M2_1.2V_AP */ |
| 428 | max77686_set_ldo_mode(p, 3, OPMODE_LPM); /* LDO3 VCC_1.8V_AP */ |
| 429 | max77686_set_ldo_mode(p, 4, OPMODE_LPM); /* LDO4 VCC_2.8V_AP */ |
| 430 | max77686_set_ldo_mode(p, 5, OPMODE_OFF); /* LDO5_VCC_1.8V_IO */ |
| 431 | max77686_set_ldo_mode(p, 6, OPMODE_STANDBY); /* LDO6 VMPLL_1.0V_AP */ |
| 432 | max77686_set_ldo_mode(p, 7, OPMODE_STANDBY); /* LDO7 VPLL_1.0V_AP */ |
| 433 | max77686_set_ldo_mode(p, 8, OPMODE_LPM); /* LDO8 VMIPI_1.0V_AP */ |
| 434 | max77686_set_ldo_mode(p, 9, OPMODE_OFF); /* CAM_ISP_MIPI_1.2*/ |
| 435 | max77686_set_ldo_mode(p, 10, OPMODE_LPM); /* LDO10 VMIPI_1.8V_AP*/ |
| 436 | max77686_set_ldo_mode(p, 11, OPMODE_STANDBY); /* LDO11 VABB1_1.8V_AP*/ |
| 437 | max77686_set_ldo_mode(p, 12, OPMODE_LPM); /* LDO12 VUOTG_3.0V_AP*/ |
| 438 | max77686_set_ldo_mode(p, 13, OPMODE_OFF); /* LDO13 VC2C_1.8V_AP */ |
| 439 | max77686_set_ldo_mode(p, 14, OPMODE_STANDBY); /* VABB02_1.8V_AP */ |
| 440 | max77686_set_ldo_mode(p, 15, OPMODE_STANDBY); /* LDO15 VHSIC_1.0V_AP*/ |
| 441 | max77686_set_ldo_mode(p, 16, OPMODE_STANDBY); /* LDO16 VHSIC_1.8V_AP*/ |
| 442 | max77686_set_ldo_mode(p, 17, OPMODE_OFF); /* CAM_SENSOR_CORE_1.2*/ |
| 443 | max77686_set_ldo_mode(p, 18, OPMODE_OFF); /* CAM_ISP_SEN_IO_1.8V*/ |
| 444 | max77686_set_ldo_mode(p, 19, OPMODE_OFF); /* LDO19 VT_CAM_1.8V */ |
| 445 | max77686_set_ldo_mode(p, 20, OPMODE_ON); /* LDO20 VDDQ_PRE_1.8V*/ |
| 446 | max77686_set_ldo_mode(p, 21, OPMODE_OFF); /* LDO21 VTF_2.8V */ |
| 447 | max77686_set_ldo_mode(p, 22, OPMODE_OFF); /* LDO22 VMEM_VDD_2.8V*/ |
| 448 | max77686_set_ldo_mode(p, 23, OPMODE_OFF); /* LDO23 TSP_AVDD_3.3V*/ |
| 449 | max77686_set_ldo_mode(p, 24, OPMODE_OFF); /* LDO24 TSP_VDD_1.8V */ |
| 450 | max77686_set_ldo_mode(p, 25, OPMODE_OFF); /* LDO25 VCC_3.3V_LCD */ |
| 451 | max77686_set_ldo_mode(p, 26, OPMODE_OFF); /*LDO26 VCC_3.0V_MOTOR*/ |
| 452 | |
| 453 | return 0; |
| 454 | } |
| 455 | |
| 456 | /* |
| 457 | * LCD |
| 458 | */ |
| 459 | |
| 460 | #ifdef CONFIG_LCD |
| 461 | static struct mipi_dsim_config dsim_config = { |
| 462 | .e_interface = DSIM_VIDEO, |
| 463 | .e_virtual_ch = DSIM_VIRTUAL_CH_0, |
| 464 | .e_pixel_format = DSIM_24BPP_888, |
| 465 | .e_burst_mode = DSIM_BURST_SYNC_EVENT, |
| 466 | .e_no_data_lane = DSIM_DATA_LANE_4, |
| 467 | .e_byte_clk = DSIM_PLL_OUT_DIV8, |
| 468 | .hfp = 1, |
| 469 | |
| 470 | .p = 3, |
| 471 | .m = 120, |
| 472 | .s = 1, |
| 473 | |
| 474 | /* D-PHY PLL stable time spec :min = 200usec ~ max 400usec */ |
| 475 | .pll_stable_time = 500, |
| 476 | |
| 477 | /* escape clk : 10MHz */ |
| 478 | .esc_clk = 20 * 1000000, |
| 479 | |
| 480 | /* stop state holding counter after bta change count 0 ~ 0xfff */ |
| 481 | .stop_holding_cnt = 0x7ff, |
| 482 | /* bta timeout 0 ~ 0xff */ |
| 483 | .bta_timeout = 0xff, |
| 484 | /* lp rx timeout 0 ~ 0xffff */ |
| 485 | .rx_timeout = 0xffff, |
| 486 | }; |
| 487 | |
| 488 | static struct exynos_platform_mipi_dsim dsim_platform_data = { |
| 489 | .lcd_panel_info = NULL, |
| 490 | .dsim_config = &dsim_config, |
| 491 | }; |
| 492 | |
| 493 | static struct mipi_dsim_lcd_device mipi_lcd_device = { |
| 494 | .name = "s6e8ax0", |
| 495 | .id = -1, |
| 496 | .bus_id = 0, |
| 497 | .platform_data = (void *)&dsim_platform_data, |
| 498 | }; |
| 499 | |
| 500 | static int mipi_power(void) |
| 501 | { |
| 502 | struct pmic *p = pmic_get("MAX77686_PMIC"); |
| 503 | |
| 504 | /* LDO8 VMIPI_1.0V_AP */ |
| 505 | max77686_set_ldo_mode(p, 8, OPMODE_ON); |
| 506 | /* LDO10 VMIPI_1.8V_AP */ |
| 507 | max77686_set_ldo_mode(p, 10, OPMODE_ON); |
| 508 | |
| 509 | return 0; |
| 510 | } |
| 511 | |
| 512 | void exynos_lcd_power_on(void) |
| 513 | { |
| 514 | struct pmic *p = pmic_get("MAX77686_PMIC"); |
| 515 | |
| 516 | gpio1 = (struct exynos4x12_gpio_part1 *)EXYNOS4X12_GPIO_PART1_BASE; |
| 517 | |
| 518 | /* LCD_2.2V_EN: GPC0[1] */ |
| 519 | s5p_gpio_set_pull(&gpio1->c0, 1, GPIO_PULL_UP); |
| 520 | s5p_gpio_direction_output(&gpio1->c0, 1, 1); |
| 521 | |
| 522 | /* LDO25 VCC_3.1V_LCD */ |
| 523 | pmic_probe(p); |
| 524 | max77686_set_ldo_voltage(p, 25, 3100000); |
| 525 | max77686_set_ldo_mode(p, 25, OPMODE_LPM); |
| 526 | } |
| 527 | |
| 528 | void exynos_reset_lcd(void) |
| 529 | { |
| 530 | gpio1 = (struct exynos4x12_gpio_part1 *)EXYNOS4X12_GPIO_PART1_BASE; |
| 531 | |
| 532 | /* reset lcd */ |
| 533 | s5p_gpio_direction_output(&gpio1->f2, 1, 0); |
| 534 | udelay(10); |
| 535 | s5p_gpio_set_value(&gpio1->f2, 1, 1); |
| 536 | } |
| 537 | |
| 538 | vidinfo_t panel_info = { |
| 539 | .vl_freq = 60, |
| 540 | .vl_col = 720, |
| 541 | .vl_row = 1280, |
| 542 | .vl_width = 720, |
| 543 | .vl_height = 1280, |
| 544 | .vl_clkp = CONFIG_SYS_HIGH, |
| 545 | .vl_hsp = CONFIG_SYS_LOW, |
| 546 | .vl_vsp = CONFIG_SYS_LOW, |
| 547 | .vl_dp = CONFIG_SYS_LOW, |
| 548 | .vl_bpix = 5, /* Bits per pixel, 2^5 = 32 */ |
| 549 | |
| 550 | /* s6e8ax0 Panel infomation */ |
| 551 | .vl_hspw = 5, |
| 552 | .vl_hbpd = 10, |
| 553 | .vl_hfpd = 10, |
| 554 | |
| 555 | .vl_vspw = 2, |
| 556 | .vl_vbpd = 1, |
| 557 | .vl_vfpd = 13, |
| 558 | .vl_cmd_allow_len = 0xf, |
| 559 | .mipi_enabled = 1, |
| 560 | |
| 561 | .dual_lcd_enabled = 0, |
| 562 | |
| 563 | .init_delay = 0, |
| 564 | .power_on_delay = 25, |
| 565 | .reset_delay = 0, |
| 566 | .interface_mode = FIMD_RGB_INTERFACE, |
| 567 | }; |
| 568 | |
| 569 | void init_panel_info(vidinfo_t *vid) |
| 570 | { |
| 571 | vid->logo_on = 1; |
| 572 | vid->resolution = HD_RESOLUTION; |
| 573 | vid->rgb_mode = MODE_RGB_P; |
| 574 | |
| 575 | vid->power_on_delay = 30; |
| 576 | |
| 577 | mipi_lcd_device.reverse_panel = 1; |
| 578 | |
| 579 | #ifdef CONFIG_TIZEN |
| 580 | get_tizen_logo_info(vid); |
| 581 | #endif |
| 582 | |
| 583 | strcpy(dsim_platform_data.lcd_panel_name, mipi_lcd_device.name); |
| 584 | dsim_platform_data.mipi_power = mipi_power; |
| 585 | dsim_platform_data.phy_enable = set_mipi_phy_ctrl; |
| 586 | dsim_platform_data.lcd_panel_info = (void *)vid; |
| 587 | exynos_mipi_dsi_register_lcd_device(&mipi_lcd_device); |
| 588 | |
| 589 | s6e8ax0_init(); |
| 590 | |
| 591 | exynos_set_dsim_platform_data(&dsim_platform_data); |
| 592 | } |
| 593 | #endif /* LCD */ |
| 594 | |
| 595 | #ifdef CONFIG_MISC_INIT_R |
| 596 | int misc_init_r(void) |
| 597 | { |
| 598 | setenv("model", "GT-I8800"); |
| 599 | setenv("board", "TRATS2"); |
| 600 | |
| 601 | show_hw_revision(); |
| 602 | |
| 603 | return 0; |
| 604 | } |
| 605 | #endif |