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wdenk074cff02004-02-24 00:16:43 +00001/*
2 * Startup Code for S3C44B0 CPU-core
3 *
4 * (C) Copyright 2004
5 * DAVE Srl
6 *
7 * http://www.dave-tech.it
8 * http://www.wawnet.biz
9 * mailto:info@wawnet.biz
10 *
11 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 */
29
30
31#include <config.h>
32#include <version.h>
33
34
35/*
36 * Jump vector table
37 */
38
39
40.globl _start
41_start: b reset
42 add pc, pc, #0x0c000000
43 add pc, pc, #0x0c000000
44 add pc, pc, #0x0c000000
45 add pc, pc, #0x0c000000
46 add pc, pc, #0x0c000000
47 add pc, pc, #0x0c000000
48 add pc, pc, #0x0c000000
49
50 .balignl 16,0xdeadbeef
51
52
53/*
54 *************************************************************************
55 *
56 * Startup Code (reset vector)
57 *
58 * do important init only if we don't start from memory!
59 * relocate u-boot to ram
60 * setup stack
61 * jump to second stage
62 *
63 *************************************************************************
64 */
65
66_TEXT_BASE:
67 .word TEXT_BASE
68
69.globl _armboot_start
70_armboot_start:
71 .word _start
72
73/*
wdenk42dfe7a2004-03-14 22:25:36 +000074 * These are defined in the board-specific linker script.
wdenk074cff02004-02-24 00:16:43 +000075 */
wdenk42dfe7a2004-03-14 22:25:36 +000076.globl _bss_start
77_bss_start:
78 .word __bss_start
79
80.globl _bss_end
81_bss_end:
82 .word _end
wdenk074cff02004-02-24 00:16:43 +000083
84#ifdef CONFIG_USE_IRQ
85/* IRQ stack memory (calculated at run-time) */
86.globl IRQ_STACK_START
87IRQ_STACK_START:
88 .word 0x0badc0de
89
90/* IRQ stack memory (calculated at run-time) */
91.globl FIQ_STACK_START
92FIQ_STACK_START:
93 .word 0x0badc0de
94#endif
95
96
97/*
98 * the actual reset code
99 */
100
101reset:
102 /*
103 * set the cpu to SVC32 mode
104 */
105 mrs r0,cpsr
106 bic r0,r0,#0x1f
107 orr r0,r0,#0x13
108 msr cpsr,r0
109
110 /*
111 * we do sys-critical inits only at reboot,
112 * not when booting from ram!
113 */
114
wdenk8aa1a2d2005-04-04 12:44:11 +0000115#ifndef CONFIG_SKIP_LOWLEVEL_INIT
wdenk074cff02004-02-24 00:16:43 +0000116 bl cpu_init_crit
117 /*
118 * before relocating, we have to setup RAM timing
119 * because memory timing is board-dependend, you will
wdenk400558b2005-04-02 23:52:25 +0000120 * find a lowlevel_init.S in your board directory.
wdenk074cff02004-02-24 00:16:43 +0000121 */
wdenk400558b2005-04-02 23:52:25 +0000122 bl lowlevel_init
wdenk074cff02004-02-24 00:16:43 +0000123#endif
124
wdenk8aa1a2d2005-04-04 12:44:11 +0000125#ifndef CONFIG_SKIP_RELOCATE_UBOOT
wdenk074cff02004-02-24 00:16:43 +0000126relocate: /* relocate U-Boot to RAM */
127 adr r0, _start /* r0 <- current position of code */
128 ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
129 cmp r0, r1 /* don't reloc during debug */
130 beq stack_setup
131
132 ldr r2, _armboot_start
wdenk42dfe7a2004-03-14 22:25:36 +0000133 ldr r3, _bss_start
wdenk074cff02004-02-24 00:16:43 +0000134 sub r2, r3, r2 /* r2 <- size of armboot */
135 add r2, r0, r2 /* r2 <- source end address */
136
137copy_loop:
138 ldmia r0!, {r3-r10} /* copy from source address [r0] */
139 stmia r1!, {r3-r10} /* copy to target address [r1] */
140 cmp r0, r2 /* until source end addreee [r2] */
141 ble copy_loop
142
143/*
144 now copy to sram the interrupt vector
145*/
146 adr r0, real_vectors
147 add r2, r0, #1024
148 ldr r1, =0x0c000000
149 add r1, r1, #0x08
150vector_copy_loop:
151 ldmia r0!, {r3-r10}
152 stmia r1!, {r3-r10}
153 cmp r0, r2
154 ble vector_copy_loop
wdenk8aa1a2d2005-04-04 12:44:11 +0000155#endif /* CONFIG_SKIP_RELOCATE_UBOOT */
wdenk074cff02004-02-24 00:16:43 +0000156
157 /* Set up the stack */
158stack_setup:
159 ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200160 sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
161 sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
wdenk074cff02004-02-24 00:16:43 +0000162#ifdef CONFIG_USE_IRQ
163 sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
164#endif
165 sub sp, r0, #12 /* leave 3 words for abort-stack */
166
167 ldr pc, _start_armboot
168
169_start_armboot: .word start_armboot
170
171
172/*
173 *************************************************************************
174 *
175 * CPU_init_critical registers
176 *
177 * setup important registers
178 * setup memory timing
179 *
180 *************************************************************************
181 */
182
183#define INTCON (0x01c00000+0x200000)
184#define INTMSK (0x01c00000+0x20000c)
185#define LOCKTIME (0x01c00000+0x18000c)
186#define PLLCON (0x01c00000+0x180000)
187#define CLKCON (0x01c00000+0x180004)
188#define WTCON (0x01c00000+0x130000)
189cpu_init_crit:
190 /* disable watch dog */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200191 ldr r0, =WTCON
wdenk074cff02004-02-24 00:16:43 +0000192 ldr r1, =0x0
193 str r1, [r0]
194
195 /*
196 * mask all IRQs by clearing all bits in the INTMRs
197 */
198 ldr r1,=INTMSK
199 ldr r0, =0x03fffeff
200 str r0, [r1]
201
202 ldr r1, =INTCON
203 ldr r0, =0x05
204 str r0, [r1]
205
206 /* Set Clock Control Register */
207 ldr r1, =LOCKTIME
208 ldrb r0, =800
209 strb r0, [r1]
210
211 ldr r1, =PLLCON
212
213#if CONFIG_S3C44B0_CLOCK_SPEED==66
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200214 ldr r0, =0x34031 /* 66MHz (Quartz=11MHz) */
wdenk074cff02004-02-24 00:16:43 +0000215#elif CONFIG_S3C44B0_CLOCK_SPEED==75
216 ldr r0, =0x610c1 /*B2: Xtal=20mhz Fclk=75MHz */
217#else
218# error CONFIG_S3C44B0_CLOCK_SPEED undefined
219#endif
220
221 str r0, [r1]
222
223 ldr r1,=CLKCON
224 ldr r0, =0x7ff8
225 str r0, [r1]
226
227 mov pc, lr
228
229
230/*************************************************/
231/* interrupt vectors */
232/*************************************************/
233real_vectors:
234 b reset
235 b undefined_instruction
236 b software_interrupt
237 b prefetch_abort
238 b data_abort
239 b not_used
240 b irq
241 b fiq
242
243/*************************************************/
244
245undefined_instruction:
246 mov r6, #3
247 b reset
248
249software_interrupt:
250 mov r6, #4
251 b reset
252
253prefetch_abort:
254 mov r6, #5
255 b reset
256
257data_abort:
258 mov r6, #6
259 b reset
260
261not_used:
262 /* we *should* never reach this */
263 mov r6, #7
264 b reset
265
266irq:
267 mov r6, #8
268 b reset
269
270fiq:
271 mov r6, #9
272 b reset