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wdenkdb2f721f2003-03-06 00:58:30 +00001/*
2 * (C) Copyright 2003
3 * EMK Elektronik GmbH <www.emk-elektronik.de>
4 * Reinhard Meyer <r.meyer@emk-elektronik.de>
5 *
6 * Configuation settings for the TOP860 board.
7 *
8 * -----------------------------------------------------------------
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27/*
wdenk945af8d2003-07-16 21:53:01 +000028 * TOP860 is a simple module:
29 * 16-bit wide FLASH on CS0 (2MB or more)
30 * 32-bit wide DRAM on CS2 (either 4MB or 16MB)
31 * FEC with Am79C874 100-Base-T and Fiber Optic
32 * Ports available, but we choose SMC1 for Console
wdenkdb2f721f2003-03-06 00:58:30 +000033 * 8k I2C EEPROM at address 0xae, 6k user available, 2k factory set
wdenk945af8d2003-07-16 21:53:01 +000034 * 32768Hz crystal PLL set for 49.152MHz Core and 24.576MHz Bus Clock
35 *
36 * This config has been copied from MBX.h / MBX860T.h
wdenkdb2f721f2003-03-06 00:58:30 +000037 */
38/*
39 * board/config.h - configuration options, board specific
40 */
41
42#ifndef __CONFIG_H
43#define __CONFIG_H
44
45/*
46 * High Level Configuration Options
47 * (easy to change)
48 */
49
50/*-----------------------------------------------------------------------
51 * CPU and BOARD type
52 */
53#define CONFIG_MPC860 1 /* This is a MPC860 CPU */
54#define CONFIG_MPC860T 1 /* even better... an FEC! */
55#define CONFIG_TOP860 1 /* ...on a TOP860 module */
56#undef CONFIG_WATCHDOG /* watchdog disabled */
wdenk945af8d2003-07-16 21:53:01 +000057#define CONFIG_IDENT_STRING " EMK TOP860"
wdenkdb2f721f2003-03-06 00:58:30 +000058
59/*-----------------------------------------------------------------------
60 * CLOCK settings
61 */
wdenk945af8d2003-07-16 21:53:01 +000062#define CONFIG_SYSCLK 49152000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020063#define CONFIG_SYS_XTAL 32768
wdenk945af8d2003-07-16 21:53:01 +000064#define CONFIG_EBDF 1
65#define CONFIG_COM 3
66#define CONFIG_RTC_MPC8xx
67
wdenkdb2f721f2003-03-06 00:58:30 +000068/*-----------------------------------------------------------------------
69 * Physical memory map as defined by EMK
70 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020071#define CONFIG_SYS_IMMR 0xFFF00000 /* Internal Memory Mapped Register */
72#define CONFIG_SYS_FLASH_BASE 0x80000000 /* FLASH in final mapping */
73#define CONFIG_SYS_DRAM_BASE 0x00000000 /* DRAM in final mapping */
74#define CONFIG_SYS_FLASH_MAX 0x00400000 /* max FLASH to expect */
75#define CONFIG_SYS_DRAM_MAX 0x01000000 /* max DRAM to expect */
wdenk945af8d2003-07-16 21:53:01 +000076
wdenkdb2f721f2003-03-06 00:58:30 +000077/*-----------------------------------------------------------------------
78 * derived values
79 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020080#define CONFIG_SYS_MF (CONFIG_SYSCLK/CONFIG_SYS_XTAL)
81#define CONFIG_SYS_CPUCLOCK CONFIG_SYSCLK
82#define CONFIG_SYS_BRGCLOCK CONFIG_SYSCLK
83#define CONFIG_SYS_BUSCLOCK (CONFIG_SYSCLK >> CONFIG_EBDF)
84#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenk945af8d2003-07-16 21:53:01 +000085#define CONFIG_8xx_GCLK_FREQ CONFIG_SYSCLK
86
wdenkdb2f721f2003-03-06 00:58:30 +000087/*-----------------------------------------------------------------------
88 * FLASH organization
89 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020090#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
91#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
wdenkdb2f721f2003-03-06 00:58:30 +000092
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020093#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
94#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenk945af8d2003-07-16 21:53:01 +000095
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020096#define CONFIG_SYS_FLASH_CFI
wdenkdb2f721f2003-03-06 00:58:30 +000097
98/*-----------------------------------------------------------------------
99 * Command interpreter
100 */
101#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
102#undef CONFIG_8xx_CONS_SMC2
103#define CONFIG_BAUDRATE 9600
wdenk945af8d2003-07-16 21:53:01 +0000104
wdenkdb2f721f2003-03-06 00:58:30 +0000105/*
106 * Allow partial commands to be matched to uniqueness.
107 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200108#define CONFIG_SYS_MATCH_PARTIAL_CMD
wdenkdb2f721f2003-03-06 00:58:30 +0000109
Jon Loeligera5562902007-07-08 15:31:57 -0500110
wdenkdb2f721f2003-03-06 00:58:30 +0000111/*
Jon Loeligera5562902007-07-08 15:31:57 -0500112 * Command line configuration.
wdenkdb2f721f2003-03-06 00:58:30 +0000113 */
Jon Loeligera5562902007-07-08 15:31:57 -0500114#include <config_cmd_default.h>
115
116#define CONFIG_CMD_ASKENV
117#define CONFIG_CMD_DHCP
118#define CONFIG_CMD_I2C
119#define CONFIG_CMD_EEPROM
120#define CONFIG_CMD_REGINFO
121#define CONFIG_CMD_IMMAP
122#define CONFIG_CMD_ELF
123#define CONFIG_CMD_DATE
124#define CONFIG_CMD_MII
125#define CONFIG_CMD_BEDBUG
126
wdenkdb2f721f2003-03-06 00:58:30 +0000127
wdenk945af8d2003-07-16 21:53:01 +0000128#define CONFIG_AUTOSCRIPT 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200129#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
wdenkdb2f721f2003-03-06 00:58:30 +0000130#undef CONFIG_LOADS_ECHO /* NO echo on for serial download */
131
wdenkdb2f721f2003-03-06 00:58:30 +0000132
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133#define CONFIG_SYS_LONGHELP /* undef to save memory */
134#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
wdenk945af8d2003-07-16 21:53:01 +0000135
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136#undef CONFIG_SYS_HUSH_PARSER /* Hush parse for U-Boot */
wdenk945af8d2003-07-16 21:53:01 +0000137
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138#ifdef CONFIG_SYS_HUSH_PARSER
139 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
wdenkdb2f721f2003-03-06 00:58:30 +0000140#endif
wdenk945af8d2003-07-16 21:53:01 +0000141
Jon Loeligera5562902007-07-08 15:31:57 -0500142#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkdb2f721f2003-03-06 00:58:30 +0000144#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200145 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkdb2f721f2003-03-06 00:58:30 +0000146#endif
wdenk945af8d2003-07-16 21:53:01 +0000147
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
149#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
150#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkdb2f721f2003-03-06 00:58:30 +0000151
152/*-----------------------------------------------------------------------
153 * Memory Test Command
154 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
156#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenk945af8d2003-07-16 21:53:01 +0000157
wdenkdb2f721f2003-03-06 00:58:30 +0000158/*-----------------------------------------------------------------------
159 * Environment handler
160 * only the first 6k in EEPROM are available for user. Of that we use 256b
161 */
wdenk945af8d2003-07-16 21:53:01 +0000162#define CONFIG_SOFT_I2C
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200163#define CONFIG_ENV_IS_IN_EEPROM 1 /* turn on EEPROM env feature */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200164#define CONFIG_ENV_OFFSET 0x1000
165#define CONFIG_ENV_SIZE 0x0700
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
167#define CONFIG_SYS_FACT_OFFSET 0x1800
168#define CONFIG_SYS_FACT_SIZE 0x0800
169#define CONFIG_SYS_I2C_FACT_ADDR 0x57
170#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
171#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
172#define CONFIG_SYS_EEPROM_SIZE 0x2000
173#define CONFIG_SYS_I2C_SPEED 100000
174#define CONFIG_SYS_I2C_SLAVE 0xFE
175#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12
wdenk945af8d2003-07-16 21:53:01 +0000176#define CONFIG_ENV_OVERWRITE
177#define CONFIG_MISC_INIT_R
178
179#if defined (CONFIG_SOFT_I2C)
180#define SDA 0x00010
181#define SCL 0x00020
Wolfgang Denkf57f70a2005-10-13 01:45:54 +0200182#define __I2C_DIR immr->im_cpm.cp_pbdir
183#define __I2C_DAT immr->im_cpm.cp_pbdat
184#define __I2C_PAR immr->im_cpm.cp_pbpar
185#define __I2C_ODR immr->im_cpm.cp_pbodr
186#define I2C_INIT { __I2C_PAR &= ~(SDA|SCL); \
187 __I2C_ODR &= ~(SDA|SCL); \
188 __I2C_DAT |= (SDA|SCL); \
189 __I2C_DIR|=(SDA|SCL); }
190#define I2C_READ ((__I2C_DAT & SDA) ? 1 : 0)
191#define I2C_SDA(x) { if (x) __I2C_DAT |= SDA; else __I2C_DAT &= ~SDA; }
192#define I2C_SCL(x) { if (x) __I2C_DAT |= SCL; else __I2C_DAT &= ~SCL; }
193#define I2C_DELAY { udelay(5); }
194#define I2C_ACTIVE { __I2C_DIR |= SDA; }
195#define I2C_TRISTATE { __I2C_DIR &= ~SDA; }
wdenkdb2f721f2003-03-06 00:58:30 +0000196#endif
197
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
wdenkdb2f721f2003-03-06 00:58:30 +0000199
200/*-----------------------------------------------------------------------
201 * defines we need to get FEC running
wdenk945af8d2003-07-16 21:53:01 +0000202 */
wdenkdb2f721f2003-03-06 00:58:30 +0000203#define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200204#define CONFIG_FEC_ENET 1 /* Ethernet only via FEC */
205#define FEC_ENET 1 /* eth.c needs it that way... */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206#define CONFIG_SYS_DISCOVER_PHY 1
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200207#define CONFIG_MII 1
TsiChung Liew0f3ba7e2008-03-30 01:22:13 -0500208#define CONFIG_MII_INIT 1
wdenkdb2f721f2003-03-06 00:58:30 +0000209#define CONFIG_PHY_ADDR 31
wdenk945af8d2003-07-16 21:53:01 +0000210
wdenkdb2f721f2003-03-06 00:58:30 +0000211/*-----------------------------------------------------------------------
212 * adresses
wdenk945af8d2003-07-16 21:53:01 +0000213 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
215#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
216#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenk945af8d2003-07-16 21:53:01 +0000217
wdenkdb2f721f2003-03-06 00:58:30 +0000218/*-----------------------------------------------------------------------
219 * Start addresses for the final memory configuration
220 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkdb2f721f2003-03-06 00:58:30 +0000222 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223#define CONFIG_SYS_SDRAM_BASE 0x00000000
224#define CONFIG_SYS_FLASH_BASE 0x80000000
wdenk945af8d2003-07-16 21:53:01 +0000225
wdenkdb2f721f2003-03-06 00:58:30 +0000226/*-----------------------------------------------------------------------
227 * Definitions for initial stack pointer and data area (in DPRAM)
228 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
230#define CONFIG_SYS_INIT_RAM_END 0x2f00 /* End of used area in DPRAM */
231#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
232#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
233#define CONFIG_SYS_INIT_VPD_SIZE 256 /* size in bytes reserved for vpd buffer */
234#define CONFIG_SYS_INIT_VPD_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_VPD_SIZE)
235#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_VPD_OFFSET-8)
wdenkdb2f721f2003-03-06 00:58:30 +0000236
237/*-----------------------------------------------------------------------
238 * Cache Configuration
239 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200240#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeligera5562902007-07-08 15:31:57 -0500241#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200242#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenkdb2f721f2003-03-06 00:58:30 +0000243#endif
244
245/* Interrupt level assignments.
246*/
247#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */
248
249/*
250 * Internal Definitions
251 *
252 * Boot Flags
253 */
254#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
255#define BOOTFLAG_WARM 0x02 /* Software reboot */
256
257/*-----------------------------------------------------------------------
258 * Debug Enable Register
259 *-----------------------------------------------------------------------
260 *
261 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200262#define CONFIG_SYS_DER 0 /* used in start.S */
wdenkdb2f721f2003-03-06 00:58:30 +0000263
264/*-----------------------------------------------------------------------
265 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
266 *-----------------------------------------------------------------------
wdenk945af8d2003-07-16 21:53:01 +0000267 * set up PLPRCR (PLL, Low-Power, and Reset Control Register)
268 * 12 MF calculated Multiplication factor
269 * 4 0 0000
270 * 1 SPLSS 0 System PLL lock status sticky
271 * 1 TEXPS 1 Timer expired status
272 * 1 0 0
273 * 1 TMIST 0 Timers interrupt status
274 * 1 0 0
275 * 1 CSRC 0 Clock source (0=DFNH, 1=DFNL)
276 * 2 LPM 00 Low-power modes
277 * 1 CSR 0 Checkstop reset enable
278 * 1 LOLRE 0 Loss-of-lock reset enable
279 * 1 FIOPD 0 Force I/O pull down
wdenk42d1f032003-10-15 23:53:47 +0000280 * 5 0 00000
wdenkdb2f721f2003-03-06 00:58:30 +0000281 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200282#define CONFIG_SYS_PLPRCR (PLPRCR_TEXPS | ((CONFIG_SYS_MF-1)<<20))
wdenk945af8d2003-07-16 21:53:01 +0000283
wdenkdb2f721f2003-03-06 00:58:30 +0000284/*-----------------------------------------------------------------------
285 * SYPCR - System Protection Control 11-9
286 * SYPCR can only be written once after reset!
287 *-----------------------------------------------------------------------
wdenk945af8d2003-07-16 21:53:01 +0000288 * set up SYPCR:
289 * 16 SWTC 0xffff Software watchdog timer count
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200290 * 8 BMT 0xff Bus monitor timing
wdenk945af8d2003-07-16 21:53:01 +0000291 * 1 BME 1 Bus monitor enable
292 * 3 0 000
293 * 1 SWF 1 Software watchdog freeze
294 * 1 SWE 0/1 Software watchdog enable
295 * 1 SWRI 0/1 Software watchdog reset/interrupt select (1=HRESET)
296 * 1 SWP 0/1 Software watchdog prescale (1=/2048)
wdenkdb2f721f2003-03-06 00:58:30 +0000297 */
298#if defined (CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200299 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200300 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
wdenkdb2f721f2003-03-06 00:58:30 +0000301#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200302 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF)
wdenkdb2f721f2003-03-06 00:58:30 +0000303#endif
304
305/*-----------------------------------------------------------------------
306 * SIUMCR - SIU Module Configuration 11-6
307 *-----------------------------------------------------------------------
wdenk945af8d2003-07-16 21:53:01 +0000308 * set up SIUMCR
309 * 1 EARB 0 External arbitration
310 * 3 EARP 000 External arbitration request priority
311 * 4 0 0000
312 * 1 DSHW 0 Data show cycles
313 * 2 DBGC 00 Debug pin configuration
314 * 2 DBPC 00 Debug port pins configuration
315 * 1 0 0
316 * 1 FRC 0 FRZ pin configuration
317 * 1 DLK 0 Debug register lock
318 * 1 OPAR 0 Odd parity
319 * 1 PNCS 0 Parity enable for non memory controller regions
320 * 1 DPC 0 Data parity pins configuration
321 * 1 MPRE 0 Multiprocessor reservation enable
322 * 2 MLRC 11 Multi level reservation control (00=IRQ4, 01=3State, 10=KR/RETRY, 11=SPKROUT)
323 * 1 AEME 0 Async external master enable
324 * 1 SEME 0 Sync external master enable
325 * 1 BSC 0 Byte strobe configuration
326 * 1 GB5E 0 GPL_B5 enable
wdenk42d1f032003-10-15 23:53:47 +0000327 * 1 B2DD 0 Bank 2 double drive
328 * 1 B3DD 0 Bank 3 double drive
wdenk945af8d2003-07-16 21:53:01 +0000329 * 4 0 0000
wdenkdb2f721f2003-03-06 00:58:30 +0000330 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200331#define CONFIG_SYS_SIUMCR (SIUMCR_MLRC11)
wdenk945af8d2003-07-16 21:53:01 +0000332
wdenkdb2f721f2003-03-06 00:58:30 +0000333/*-----------------------------------------------------------------------
334 * TBSCR - Time Base Status and Control 11-26
335 *-----------------------------------------------------------------------
336 * Clear Reference Interrupt Status, Timebase freezing enabled
337 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200338#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
wdenkdb2f721f2003-03-06 00:58:30 +0000339
340/*-----------------------------------------------------------------------
341 * PISCR - Periodic Interrupt Status and Control 11-31
342 *-----------------------------------------------------------------------
343 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
344 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200345#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE)
wdenkdb2f721f2003-03-06 00:58:30 +0000346
347/*-----------------------------------------------------------------------
348 * SCCR - System Clock and reset Control Register 15-27
349 *-----------------------------------------------------------------------
wdenk945af8d2003-07-16 21:53:01 +0000350 * set up SCCR (System Clock and Reset Control Register)
351 * 1 0 0
352 * 2 COM 11 Clock output module (00=full, 01=half, 11=off)
353 * 3 0 000
354 * 1 TBS 1 Timebase source (0=OSCCLK, 1=GCLK2)
355 * 1 RTDIV 0 Real-time clock divide (0=/4, 1=/512)
356 * 1 RTSEL 0 Real-time clock select (0=OSCM, 1=EXTCLK)
357 * 1 CRQEN 0 CPM request enable
358 * 1 PRQEN 0 Power management request enable
359 * 2 0 00
360 * 2 EBDF xx External bus division factor
361 * 2 0 00
362 * 2 DFSYNC 00 Division factor for SYNCLK
363 * 2 DFBRG 00 Division factor for BRGCLK
364 * 3 DFNL 000 Division factor low frequency
365 * 3 DFNH 000 Division factor high frequency
366 * 5 0 00000
wdenkdb2f721f2003-03-06 00:58:30 +0000367 */
368#define SCCR_MASK 0
wdenk42dfe7a2004-03-14 22:25:36 +0000369#ifdef CONFIG_EBDF
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200370 #define CONFIG_SYS_SCCR (SCCR_COM11 | SCCR_TBS | SCCR_EBDF01)
wdenk945af8d2003-07-16 21:53:01 +0000371#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200372 #define CONFIG_SYS_SCCR (SCCR_COM11 | SCCR_TBS)
wdenk945af8d2003-07-16 21:53:01 +0000373#endif
wdenkdb2f721f2003-03-06 00:58:30 +0000374
375/*-----------------------------------------------------------------------
376 * Chip Select 0 - FLASH
377 *-----------------------------------------------------------------------
378 * Preliminary Values
379 */
380/* FLASH timing: CSNT=1 ACS=10 BIH=1 SCY=4 SETA=0 TLRX=1 EHTR=1 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200381#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_4_CLK | OR_TRLX | OR_EHTR)
382#define CONFIG_SYS_OR0_PRELIM (-CONFIG_SYS_FLASH_MAX | CONFIG_SYS_OR_TIMING_FLASH)
383#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_V )
wdenk945af8d2003-07-16 21:53:01 +0000384
wdenkdb2f721f2003-03-06 00:58:30 +0000385/*-----------------------------------------------------------------------
386 * misc
387 *-----------------------------------------------------------------------
388 *
389 */
390/*
391 * Set the autoboot delay in seconds. A delay of -1 disables autoboot
392 */
393#define CONFIG_BOOTDELAY 5
394
395/*
396 * Pass the clock frequency to the Linux kernel in units of MHz
397 */
398#define CONFIG_CLOCKS_IN_MHZ
399
400#define CONFIG_PREBOOT \
401 "echo;echo"
402
403#undef CONFIG_BOOTARGS
404#define CONFIG_BOOTCOMMAND \
405 "bootp;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100406 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
407 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
wdenkdb2f721f2003-03-06 00:58:30 +0000408 "bootm"
409
410/*
411 * BOOTP options
412 */
Jon Loeliger37d4bb72007-07-09 21:38:02 -0500413#define CONFIG_BOOTP_SUBNETMASK
414#define CONFIG_BOOTP_GATEWAY
415#define CONFIG_BOOTP_HOSTNAME
416#define CONFIG_BOOTP_BOOTPATH
417#define CONFIG_BOOTP_BOOTFILESIZE
wdenk42d1f032003-10-15 23:53:47 +0000418
wdenkdb2f721f2003-03-06 00:58:30 +0000419
420/*
421 * Set default IP stuff just to get bootstrap entries into the
422 * environment so that we can autoscript the full default environment.
423 */
424#define CONFIG_ETHADDR 9a:52:63:15:85:25
425#define CONFIG_SERVERIP 10.0.4.200
426#define CONFIG_IPADDR 10.0.4.111
wdenk945af8d2003-07-16 21:53:01 +0000427
wdenkdb2f721f2003-03-06 00:58:30 +0000428/*-----------------------------------------------------------------------
429 * Defaults for Autoscript
430 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200431#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
432#define CONFIG_SYS_TFTP_LOADADDR 0x00100000
wdenk945af8d2003-07-16 21:53:01 +0000433
wdenkdb2f721f2003-03-06 00:58:30 +0000434/*
435 * For booting Linux, the board info and command line data
436 * have to be in the first 8 MB of memory, since this is
437 * the maximum mapped by the Linux kernel during initialization.
438 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200439#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkdb2f721f2003-03-06 00:58:30 +0000440
wdenk945af8d2003-07-16 21:53:01 +0000441
wdenkdb2f721f2003-03-06 00:58:30 +0000442#endif /* __CONFIG_H */