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Heiko Schocherde044362008-11-20 09:57:47 +01001/*
2 * Copyright (C) 2006 Freescale Semiconductor, Inc.
3 * Dave Liu <daveliu@freescale.com>
4 *
5 * Copyright (C) 2007 Logic Product Development, Inc.
6 * Peter Barada <peterb@logicpd.com>
7 *
8 * Copyright (C) 2007 MontaVista Software, Inc.
9 * Anton Vorontsov <avorontsov@ru.mvista.com>
10 *
Holger Brunckf41ee962011-03-14 15:49:05 +010011 * (C) Copyright 2008-2011
Heiko Schocherde044362008-11-20 09:57:47 +010012 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 */
19
20#ifndef __CONFIG_H
21#define __CONFIG_H
22
23/*
24 * High Level Configuration Options
25 */
Heiko Schocherb11f53f2011-03-15 16:52:29 +010026#define CONFIG_QE /* Has QE */
27#define CONFIG_MPC8360 /* MPC8360 CPU specific */
28#define CONFIG_KMETER1 /* KMETER1 board specific */
Heiko Schocher605f78e2009-02-24 11:30:44 +010029#define CONFIG_HOSTNAME kmeter1
Heiko Schocher62ddcf02010-02-18 08:08:25 +010030#define CONFIG_KM_BOARD_NAME "kmeter1"
Heiko Schocherde044362008-11-20 09:57:47 +010031
Wolfgang Denk2ae18242010-10-06 09:05:45 +020032#define CONFIG_SYS_TEXT_BASE 0xF0000000
Holger Brunckde3ad132011-03-14 16:01:04 +010033#define CONFIG_KM_DEF_NETDEV \
34 "netdev=eth2\0" \
Wolfgang Denk2ae18242010-10-06 09:05:45 +020035
Heiko Schocher62ddcf02010-02-18 08:08:25 +010036/* include common defines/options for all 83xx Keymile boards */
Valentin Longchamp264eaa02011-05-04 01:47:33 +000037#include "km/km83xx-common.h"
Heiko Schocher4897ee32010-01-07 08:55:50 +010038
Heiko Schocherb11f53f2011-03-15 16:52:29 +010039#define CONFIG_MISC_INIT_R
Heiko Schocherde044362008-11-20 09:57:47 +010040/*
Heiko Schocher62ddcf02010-02-18 08:08:25 +010041 * System IO Setup
Heiko Schocherde044362008-11-20 09:57:47 +010042 */
Heiko Schocher62ddcf02010-02-18 08:08:25 +010043#define CONFIG_SYS_SICRH (SICRH_UC1EOBI | SICRH_UC2E1OBI)
Heiko Schocherde044362008-11-20 09:57:47 +010044
45/*
46 * Hardware Reset Configuration Word
47 */
48#define CONFIG_SYS_HRCW_LOW (\
49 HRCWL_CSB_TO_CLKIN_4X1 | \
50 HRCWL_CORE_TO_CSB_2X1 | \
51 HRCWL_CE_PLL_VCO_DIV_2 | \
Joe Hershbergerb43b12e2011-10-11 23:57:23 -050052 HRCWL_CE_TO_PLL_1X6)
Heiko Schocherde044362008-11-20 09:57:47 +010053
54#define CONFIG_SYS_HRCW_HIGH (\
55 HRCWH_CORE_ENABLE | \
56 HRCWH_FROM_0X00000100 | \
Heiko Schocher605f78e2009-02-24 11:30:44 +010057 HRCWH_BOOTSEQ_DISABLE | \
Heiko Schocherde044362008-11-20 09:57:47 +010058 HRCWH_SW_WATCHDOG_DISABLE | \
59 HRCWH_ROM_LOC_LOCAL_16BIT | \
60 HRCWH_BIG_ENDIAN | \
Heiko Schocher605f78e2009-02-24 11:30:44 +010061 HRCWH_LALE_EARLY | \
Joe Hershbergerb43b12e2011-10-11 23:57:23 -050062 HRCWH_LDP_CLEAR)
Heiko Schocherde044362008-11-20 09:57:47 +010063
Heiko Schocher118cbe32009-02-24 11:30:40 +010064#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
Heiko Schocherde044362008-11-20 09:57:47 +010065#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
66 SDRAM_CFG_SREN)
67#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
68#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
Heiko Schocher605f78e2009-02-24 11:30:44 +010069#define CONFIG_SYS_DDR_INTERVAL ((0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
70 (0x3cf << SDRAM_INTERVAL_REFINT_SHIFT))
Heiko Schocherde044362008-11-20 09:57:47 +010071
Heiko Schocher62ddcf02010-02-18 08:08:25 +010072#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
73 CSCONFIG_ROW_BIT_13 | \
74 CSCONFIG_COL_BIT_10 | \
Joe Hershberger2fef4022011-10-11 23:57:29 -050075 CSCONFIG_ODT_WR_ONLY_CURRENT)
Heiko Schocher62ddcf02010-02-18 08:08:25 +010076
Joe Hershberger2fef4022011-10-11 23:57:29 -050077#define CONFIG_SYS_DDRCDR (DDRCDR_EN | DDRCDR_Q_DRN)
78 /* 0x40000001 */
Heiko Schocher605f78e2009-02-24 11:30:44 +010079#define CONFIG_SYS_DDR_MODE 0x47860452
80#define CONFIG_SYS_DDR_MODE2 0x8080c000
Heiko Schocherde044362008-11-20 09:57:47 +010081
82#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
83 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
84 (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
85 (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
86 (0 << TIMING_CFG0_WWT_SHIFT) | \
87 (0 << TIMING_CFG0_RRT_SHIFT) | \
88 (0 << TIMING_CFG0_WRT_SHIFT) | \
89 (0 << TIMING_CFG0_RWT_SHIFT))
90
Heiko Schocherb11f53f2011-03-15 16:52:29 +010091#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \
92 (2 << TIMING_CFG1_WRTORD_SHIFT) | \
93 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
94 (3 << TIMING_CFG1_WRREC_SHIFT) | \
95 (7 << TIMING_CFG1_REFREC_SHIFT) | \
96 (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
97 (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
98 (3 << TIMING_CFG1_PRETOACT_SHIFT))
Heiko Schocherde044362008-11-20 09:57:47 +010099
Heiko Schocher605f78e2009-02-24 11:30:44 +0100100#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
Heiko Schocherde044362008-11-20 09:57:47 +0100101 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
102 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
Heiko Schocher605f78e2009-02-24 11:30:44 +0100103 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
104 (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
Heiko Schocherde044362008-11-20 09:57:47 +0100105 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
Heiko Schocher605f78e2009-02-24 11:30:44 +0100106 (5 << TIMING_CFG2_CPO_SHIFT))
Heiko Schocherde044362008-11-20 09:57:47 +0100107
108#define CONFIG_SYS_DDR_TIMING_3 0x00000000
109
Heiko Schocher8ed74342011-03-08 10:47:39 +0100110/* PRIO FPGA */
111#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000
112#define CONFIG_SYS_KMBEC_FPGA_SIZE 128
113/* PAXE FPGA */
114#define CONFIG_SYS_PAXE_BASE 0xA0000000
Heiko Schocher605f78e2009-02-24 11:30:44 +0100115#define CONFIG_SYS_PAXE_SIZE 512
Heiko Schocherde044362008-11-20 09:57:47 +0100116
Heiko Schocher62ddcf02010-02-18 08:08:25 +0100117/* EEprom support */
118#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
Heiko Schocherde044362008-11-20 09:57:47 +0100119
120/*
121 * Local Bus Configuration & Clock Setup
122 */
Kim Phillipsc7190f02009-09-25 18:19:44 -0500123#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
124#define CONFIG_SYS_LCRR_EADC LCRR_EADC_2
125#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
Heiko Schocherde044362008-11-20 09:57:47 +0100126
127/*
128 * Init Local Bus Memory Controller:
129 *
130 * Bank Bus Machine PortSz Size Device
131 * ---- --- ------- ------ ----- ------
Heiko Schocher605f78e2009-02-24 11:30:44 +0100132 * 3 Local GPCM 8 bit 512MB PAXE
Heiko Schocherde044362008-11-20 09:57:47 +0100133 *
134 */
Heiko Schocherde044362008-11-20 09:57:47 +0100135
136/*
137 * PAXE on the local bus CS3
138 */
Heiko Schocherb11f53f2011-03-15 16:52:29 +0100139#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PAXE_BASE
Heiko Schocher605f78e2009-02-24 11:30:44 +0100140#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000001C /* 512MB window size */
Heiko Schocherde044362008-11-20 09:57:47 +0100141
142#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_PAXE_BASE | \
143 (1 << BR_PS_SHIFT) | /* 8 bit port size */ \
144 BR_V)
145#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_PAXE_SIZE) | \
146 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
147 OR_GPCM_SCY_2 | \
148 OR_GPCM_TRLX | OR_GPCM_EAD)
149
150/*
Heiko Schocherde044362008-11-20 09:57:47 +0100151 * MMU Setup
152 */
153
Heiko Schocherde044362008-11-20 09:57:47 +0100154/* PAXE: icache cacheable, but dcache-inhibit and guarded */
Joe Hershberger72cd4082011-10-11 23:57:28 -0500155#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_RW | \
Heiko Schocher62ddcf02010-02-18 08:08:25 +0100156 BATL_MEMCOHERENCE)
Heiko Schocherb11f53f2011-03-15 16:52:29 +0100157#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PAXE_BASE | BATU_BL_256M | \
Heiko Schocher62ddcf02010-02-18 08:08:25 +0100158 BATU_VS | BATU_VP)
Joe Hershberger72cd4082011-10-11 23:57:28 -0500159#define CONFIG_SYS_DBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_RW | \
Heiko Schocherde044362008-11-20 09:57:47 +0100160 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
161#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
162
163#ifdef CONFIG_PCI
164/* PCI MEM space: cacheable */
Joe Hershberger72cd4082011-10-11 23:57:28 -0500165#define CFG_IBAT6L (CFG_PCI1_MEM_PHYS | BATL_PP_RW | BATL_MEMCOHERENCE)
Heiko Schocherde044362008-11-20 09:57:47 +0100166#define CFG_IBAT6U (CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
167#define CFG_DBAT6L CFG_IBAT6L
168#define CFG_DBAT6U CFG_IBAT6U
169/* PCI MMIO space: cache-inhibit and guarded */
Joe Hershberger72cd4082011-10-11 23:57:28 -0500170#define CFG_IBAT7L (CFG_PCI1_MMIO_PHYS | BATL_PP_RW | \
Heiko Schocherde044362008-11-20 09:57:47 +0100171 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
172#define CFG_IBAT7U (CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
173#define CFG_DBAT7L CFG_IBAT7L
174#define CFG_DBAT7U CFG_IBAT7U
175#else /* CONFIG_PCI */
176#define CONFIG_SYS_IBAT6L (0)
177#define CONFIG_SYS_IBAT6U (0)
178#define CONFIG_SYS_IBAT7L (0)
179#define CONFIG_SYS_IBAT7U (0)
180#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
181#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
182#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
183#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
184#endif /* CONFIG_PCI */
185
Heiko Schocherde044362008-11-20 09:57:47 +0100186#endif /* __CONFIG_H */