blob: 030720c89f32f20e42132c65994c7712f33f57c3 [file] [log] [blame]
TsiChungLiewa90e79d2007-07-05 23:22:31 -05001/*
2 * timer.h -- ColdFire internal TIMER support defines.
3 *
4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26/****************************************************************************/
27#ifndef timer_h
28#define timer_h
29/****************************************************************************/
30
31/****************************************************************************/
32/* Timer structure */
33/****************************************************************************/
34/* DMA Timer module registers */
35typedef struct dtimer_ctrl {
TsiChungLiewab77bc52007-08-15 15:39:17 -050036#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
TsiChungLiewa90e79d2007-07-05 23:22:31 -050037 u16 tmr; /* 0x00 Mode register */
TsiChungLiewab77bc52007-08-15 15:39:17 -050038 u16 res1; /* 0x02 */
39 u16 trr; /* 0x04 Reference register */
40 u16 res2; /* 0x06 */
41 u16 tcr; /* 0x08 Capture register */
42 u16 res3; /* 0x0A */
43 u16 tcn; /* 0x0C Counter register */
44 u16 res4; /* 0x0E */
45 u8 res6; /* 0x10 */
46 u8 ter; /* 0x11 Event register */
47 u16 res7; /* 0x12 */
48#else
TsiChungLiew56115662007-08-15 19:38:15 -050049 u16 tmr; /* 0x00 Mode register */
TsiChungLiewa90e79d2007-07-05 23:22:31 -050050 u8 txmr; /* 0x02 Extended Mode register */
51 u8 ter; /* 0x03 Event register */
52 u32 trr; /* 0x04 Reference register */
53 u32 tcr; /* 0x08 Capture register */
54 u32 tcn; /* 0x0C Counter register */
TsiChungLiewab77bc52007-08-15 15:39:17 -050055#endif
TsiChungLiewa90e79d2007-07-05 23:22:31 -050056} dtmr_t;
57
58/*Programmable Interrupt Timer */
59typedef struct pit_ctrl {
60 u16 pcsr; /* 0x00 Control and Status Register */
61 u16 pmr; /* 0x02 Modulus Register */
62 u16 pcntr; /* 0x04 Count Register */
63} pit_t;
64
65/*********************************************************************
66* DMA Timers (DTIM)
67*********************************************************************/
68/* Bit definitions and macros for DTMR */
69#define DTIM_DTMR_RST (0x0001) /* Reset */
70#define DTIM_DTMR_CLK(x) (((x)&0x0003)<<1) /* Input clock source */
71#define DTIM_DTMR_FRR (0x0008) /* Free run/restart */
72#define DTIM_DTMR_ORRI (0x0010) /* Output reference request/interrupt enable */
73#define DTIM_DTMR_OM (0x0020) /* Output Mode */
74#define DTIM_DTMR_CE(x) (((x)&0x0003)<<6) /* Capture Edge */
75#define DTIM_DTMR_PS(x) (((x)&0x00FF)<<8) /* Prescaler value */
76#define DTIM_DTMR_RST_EN (0x0001)
77#define DTIM_DTMR_RST_RST (0x0000)
78#define DTIM_DTMR_CE_ANY (0x00C0)
79#define DTIM_DTMR_CE_FALL (0x0080)
80#define DTIM_DTMR_CE_RISE (0x0040)
81#define DTIM_DTMR_CE_NONE (0x0000)
82#define DTIM_DTMR_CLK_DTIN (0x0006)
83#define DTIM_DTMR_CLK_DIV16 (0x0004)
84#define DTIM_DTMR_CLK_DIV1 (0x0002)
85#define DTIM_DTMR_CLK_STOP (0x0000)
86
87/* Bit definitions and macros for DTXMR */
88#define DTIM_DTXMR_MODE16 (0x01) /* Increment Mode */
89#define DTIM_DTXMR_DMAEN (0x80) /* DMA request */
90
91/* Bit definitions and macros for DTER */
92#define DTIM_DTER_CAP (0x01) /* Capture event */
93#define DTIM_DTER_REF (0x02) /* Output reference event */
94
95/*********************************************************************
96*
97* Programmable Interrupt Timer Modules (PIT)
98*
99*********************************************************************/
100
101/* Bit definitions and macros for PCSR */
102#define PIT_PCSR_EN (0x0001)
103#define PIT_PCSR_RLD (0x0002)
104#define PIT_PCSR_PIF (0x0004)
105#define PIT_PCSR_PIE (0x0008)
106#define PIT_PCSR_OVW (0x0010)
107#define PIT_PCSR_HALTED (0x0020)
108#define PIT_PCSR_DOZE (0x0040)
109#define PIT_PCSR_PRE(x) (((x)&0x000F)<<8)
110
111/* Bit definitions and macros for PMR */
112#define PIT_PMR_PM(x) (x)
113
114/* Bit definitions and macros for PCNTR */
115#define PIT_PCNTR_PC(x) (x)
116
117/****************************************************************************/
118#endif /* timer_h */