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wdenke2211742002-11-02 23:30:20 +00001/*
2 * (C) Copyright 2000
3 * Murray Jensen <Murray.Jensen@cmst.csiro.au>
4 *
5 * (C) Copyright 2000
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
8 *
9 * Configuation settings for the R&S Protocol Board board.
10 *
11 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 */
29
30#ifndef __CONFIG_H
31#define __CONFIG_H
32
33/*
34 * High Level Configuration Options
35 * (easy to change)
36 */
37
38#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
39#define CONFIG_RSD_PROTO 1 /* on a R&S Protocol Board */
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050040#define CONFIG_CPM2 1 /* Has a CPM2 */
wdenke2211742002-11-02 23:30:20 +000041
Wolfgang Denk2ae18242010-10-06 09:05:45 +020042#define CONFIG_SYS_TEXT_BASE 0xff000000
43
wdenkc837dcb2004-01-20 23:12:12 +000044#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
45
wdenke2211742002-11-02 23:30:20 +000046/*
47 * select serial console configuration
48 *
49 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
50 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
51 * for SCC).
52 *
53 * if CONFIG_CONS_NONE is defined, then the serial console routines must
54 * defined elsewhere.
55 */
56#undef CONFIG_CONS_ON_SMC /* define if console on SMC */
57#define CONFIG_CONS_ON_SCC /* define if console on SCC */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020058#undef CONFIG_CONS_NONE /* define if console on neither */
wdenke2211742002-11-02 23:30:20 +000059#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */
60
61/*
62 * select ethernet configuration
63 *
64 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
65 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
66 * for FCC)
67 *
68 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
Jon Loeliger639221c2007-07-09 17:15:49 -050069 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
wdenke2211742002-11-02 23:30:20 +000070 */
71#undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */
72#define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */
73#undef CONFIG_ETHER_NONE /* define if ethernet on neither */
74#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
75
76#if (CONFIG_ETHER_INDEX == 2)
77
78/*
79 * - Rx-CLK is CLK13
80 * - Tx-CLK is CLK14
81 * - Select bus for bd/buffers (see 28-13)
82 * - Enable Full Duplex in FSMR
83 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020084# define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
85# define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
86# define CONFIG_SYS_CPMFCR_RAMTYPE (0)
87# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
wdenke2211742002-11-02 23:30:20 +000088
89#endif /* CONFIG_ETHER_INDEX */
90
91
92/* allow to overwrite serial and ethaddr */
93#define CONFIG_ENV_OVERWRITE
94
95/* enable I2C */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020096#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020097#define CONFIG_SYS_I2C_SPEED 50000 /* I2C speed and slave address */
98#define CONFIG_SYS_I2C_SLAVE 0x30
wdenke2211742002-11-02 23:30:20 +000099
100
101/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
102#define CONFIG_8260_CLKIN 50000000 /* in Hz */
103
104#define CONFIG_BAUDRATE 115200
105
Jon Loeliger90cc3eb2007-07-04 22:33:23 -0500106
107/*
Jon Loeliger079a1362007-07-10 10:12:10 -0500108 * BOOTP options
109 */
110#define CONFIG_BOOTP_BOOTFILESIZE
111#define CONFIG_BOOTP_BOOTPATH
112#define CONFIG_BOOTP_GATEWAY
113#define CONFIG_BOOTP_HOSTNAME
114
115
116/*
Jon Loeliger90cc3eb2007-07-04 22:33:23 -0500117 * Command line configuration.
118 */
119#include <config_cmd_default.h>
120
121#undef CONFIG_CMD_KGDB
122
wdenke2211742002-11-02 23:30:20 +0000123
124/* Define this if you want to boot from 0x00000100. If you don't define
125 * this, you will need to program the bootloader to 0xfff00000, and
126 * get the hardware reset config words at 0xfe000000. The simplest
127 * way to do that is to program the bootloader at both addresses.
128 * It is suggested that you just let U-Boot live at 0x00000000.
129 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130#define CONFIG_SYS_RSD_BOOT_LOW 1
wdenke2211742002-11-02 23:30:20 +0000131
wdenke2211742002-11-02 23:30:20 +0000132#define CONFIG_BOOTDELAY 5
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200133#define CONFIG_BOOTARGS "devfs=mount root=ramfs"
wdenke2211742002-11-02 23:30:20 +0000134#define CONFIG_ETHADDR 08:00:3e:26:0a:5a
135#define CONFIG_NETMASK 255.255.0.0
136
Jon Loeliger90cc3eb2007-07-04 22:33:23 -0500137#if defined(CONFIG_CMD_KGDB)
wdenke2211742002-11-02 23:30:20 +0000138#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
139#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
140#endif
141
142/*
143 * Miscellaneous configurable options
144 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200145#define CONFIG_SYS_LONGHELP /* undef to save memory */
146#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger90cc3eb2007-07-04 22:33:23 -0500147#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenke2211742002-11-02 23:30:20 +0000149#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenke2211742002-11-02 23:30:20 +0000151#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
153#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
154#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenke2211742002-11-02 23:30:20 +0000155
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
157#define CONFIG_SYS_MEMTEST_END 0x01c00000 /* 4 ... 28 MB in DRAM */
wdenke2211742002-11-02 23:30:20 +0000158
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenke2211742002-11-02 23:30:20 +0000160
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenke2211742002-11-02 23:30:20 +0000162
163 /* valid baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenke2211742002-11-02 23:30:20 +0000165
166/*
167 * Low Level Configuration Settings
168 * (address mappings, register initial values, etc.)
169 * You should know what you are doing if you make changes here.
170 */
171
172/*-----------------------------------------------------------------------
173 * Physical Memory Map
174 */
175#define PHYS_SDRAM_60X 0x00000000 /* SDRAM (60x Bus) */
176#define PHYS_SDRAM_60X_SIZE 0x08000000 /* 128 MB */
177
178#define PHYS_SDRAM_LOCAL 0x40000000 /* SDRAM (Local Bus) */
179#define PHYS_SDRAM_LOCAL_SIZE 0x04000000 /* 64 MB */
180
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200181#define PHYS_DPRAM_PCI 0xE8000000 /* DPRAM PPC/PCI */
182#define PHYS_DPRAM_PCI_SIZE 0x00020000 /* 128 KB */
wdenke2211742002-11-02 23:30:20 +0000183
184/*#define PHYS_DPRAM_PCI_SEM 0x04020000 / * DPRAM PPC/PCI Semaphore */
185/*#define PHYS_DPRAM_PCI_SEM_SIZE 0x00000001 / * 1 Byte */
186
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200187#define PHYS_DPRAM_SHARC 0xE8100000 /* DPRAM PPC/Sharc */
188#define PHYS_DPRAM_SHARC_SIZE 0x00040000 /* 256 KB */
wdenke2211742002-11-02 23:30:20 +0000189
190/*#define PHYS_DPRAM_SHARC_SEM 0x04140000 / * DPRAM PPC/Sharc Semaphore */
191/*#define PHYS_DPRAM_SHARC_SEM_SIZE 0x00000001 / * 1 Byte */
192
193#define PHYS_VIRTEX_REGISTER 0xE8300000 /* FPGA implemented register */
194#define PHYS_VIRTEX_REGISTER_SIZE 0x00000100
195
196#define PHYS_USB 0x04200000 /* USB Controller (60x Bus) */
197#define PHYS_USB_SIZE 0x00000002 /* 2 Bytes */
198
199#define PHYS_IMMR 0xF0000000 /* Internal Memory Mapped Reg. */
200
201#define PHYS_FLASH 0xFF000000 /* Flash (60x Bus) */
202#define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */
203
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204#define CONFIG_SYS_IMMR PHYS_IMMR
wdenke2211742002-11-02 23:30:20 +0000205
206/*-----------------------------------------------------------------------
207 * Reset Address
208 *
209 * In order to reset the CPU, U-Boot jumps to a special address which
210 * causes a machine check exception. The default address for this is
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200211 * CONFIG_SYS_MONITOR_BASE - sizeof (ulong), which might not always work, eg. when
wdenke2211742002-11-02 23:30:20 +0000212 * testing the monitor in RAM using a JTAG debugger.
213 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214 * Just set CONFIG_SYS_RESET_ADDRESS to an address that you know is sure to
wdenke2211742002-11-02 23:30:20 +0000215 * cause a bus error on your hardware.
216 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200217#define CONFIG_SYS_RESET_ADDRESS 0x20000000
wdenke2211742002-11-02 23:30:20 +0000218
219/*-----------------------------------------------------------------------
220 * Hard Reset Configuration Words
221 */
222
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223#if defined(CONFIG_SYS_RSD_BOOT_LOW)
224# define CONFIG_SYS_RSD_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS)
wdenke2211742002-11-02 23:30:20 +0000225#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226# define CONFIG_SYS_RSD_HRCW_BOOT_FLAGS (0)
227#endif /* defined(CONFIG_SYS_RSD_BOOT_LOW) */
wdenke2211742002-11-02 23:30:20 +0000228
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229/* get the HRCW ISB field from CONFIG_SYS_IMMR */
230#define CONFIG_SYS_RSD_HRCW_IMMR ( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) |\
231 ((CONFIG_SYS_IMMR & 0x01000000) >> 7) |\
232 ((CONFIG_SYS_IMMR & 0x00100000) >> 4) )
wdenke2211742002-11-02 23:30:20 +0000233
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200234#define CONFIG_SYS_HRCW_MASTER (HRCW_L2CPC10 | \
wdenke2211742002-11-02 23:30:20 +0000235 HRCW_DPPC11 | \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200236 CONFIG_SYS_RSD_HRCW_IMMR |\
wdenk8bde7f72003-06-27 21:31:46 +0000237 HRCW_MMR00 | \
238 HRCW_APPC10 | \
239 HRCW_CS10PC00 | \
240 HRCW_MODCK_H0000 |\
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241 CONFIG_SYS_RSD_HRCW_BOOT_FLAGS)
wdenke2211742002-11-02 23:30:20 +0000242
243/* no slaves */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244#define CONFIG_SYS_HRCW_SLAVE1 0
245#define CONFIG_SYS_HRCW_SLAVE2 0
246#define CONFIG_SYS_HRCW_SLAVE3 0
247#define CONFIG_SYS_HRCW_SLAVE4 0
248#define CONFIG_SYS_HRCW_SLAVE5 0
249#define CONFIG_SYS_HRCW_SLAVE6 0
250#define CONFIG_SYS_HRCW_SLAVE7 0
wdenke2211742002-11-02 23:30:20 +0000251
252/*-----------------------------------------------------------------------
253 * Definitions for initial stack pointer and data area (in DPRAM)
254 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200255#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200256#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200257#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200258#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenke2211742002-11-02 23:30:20 +0000259
260/*-----------------------------------------------------------------------
261 * Start addresses for the final memory configuration
262 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200263 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
264 * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependend.
wdenke2211742002-11-02 23:30:20 +0000265 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200266#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_60X
267#define CONFIG_SYS_FLASH_BASE PHYS_FLASH
268/*#define CONFIG_SYS_MONITOR_BASE 0x200000 */
269#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
270#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE
271#define CONFIG_SYS_RAMBOOT
wdenke2211742002-11-02 23:30:20 +0000272#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200273#define CONFIG_SYS_MONITOR_LEN (160 << 10) /* Reserve 160 kB for Monitor */
274#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenke2211742002-11-02 23:30:20 +0000275
276/*
277 * For booting Linux, the board info and command line data
278 * have to be in the first 8 MB of memory, since this is
279 * the maximum mapped by the Linux kernel during initialization.
280 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200281#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenke2211742002-11-02 23:30:20 +0000282
283/*-----------------------------------------------------------------------
284 * FLASH and environment organization
285 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200286#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
287#define CONFIG_SYS_MAX_FLASH_SECT 63 /* max number of sectors on one chip */
wdenke2211742002-11-02 23:30:20 +0000288
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200289#define CONFIG_SYS_FLASH_ERASE_TOUT 12000 /* Timeout for Flash Erase (in ms) */
290#define CONFIG_SYS_FLASH_WRITE_TOUT 3000 /* Timeout for Flash Write (in ms) */
wdenke2211742002-11-02 23:30:20 +0000291
292/* turn off NVRAM env feature */
293#undef CONFIG_NVRAM_ENV
294
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200295#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200296#define CONFIG_ENV_ADDR (PHYS_FLASH + 0x28000) /* Addr of Environment Sector */
297#define CONFIG_ENV_SECT_SIZE 0x8000 /* Total Size of Environment Sector */
wdenke2211742002-11-02 23:30:20 +0000298
299/*-----------------------------------------------------------------------
300 * Cache Configuration
301 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200302#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
Jon Loeliger90cc3eb2007-07-04 22:33:23 -0500303#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200304#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
wdenke2211742002-11-02 23:30:20 +0000305#endif
306
307/*-----------------------------------------------------------------------
308 * HIDx - Hardware Implementation-dependent Registers 2-11
309 *-----------------------------------------------------------------------
310 * HID0 also contains cache control - initially enable both caches and
311 * invalidate contents, then the final state leaves only the instruction
312 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
313 * but Soft reset does not.
314 *
315 * HID1 has only read-only information - nothing to set.
316 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200317#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|HID0_IFEM|HID0_ABE)
318#define CONFIG_SYS_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE|HID0_EMCP)
319#define CONFIG_SYS_HID2 0
wdenke2211742002-11-02 23:30:20 +0000320
321/*-----------------------------------------------------------------------
322 * RMR - Reset Mode Register
323 *-----------------------------------------------------------------------
324 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200325#define CONFIG_SYS_RMR 0
wdenke2211742002-11-02 23:30:20 +0000326
327/*-----------------------------------------------------------------------
328 * BCR - Bus Configuration 4-25
329 *-----------------------------------------------------------------------
330 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200331#define CONFIG_SYS_BCR 0x100c0000
wdenke2211742002-11-02 23:30:20 +0000332
333/*-----------------------------------------------------------------------
334 * SIUMCR - SIU Module Configuration 4-31
335 *-----------------------------------------------------------------------
336 */
337
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200338#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC11 | SIUMCR_L2CPC10 | SIUMCR_APPC10 | \
wdenke2211742002-11-02 23:30:20 +0000339 SIUMCR_CS10PC01 | SIUMCR_BCTLC01)
340
341/*-----------------------------------------------------------------------
342 * SYPCR - System Protection Control 11-9
343 * SYPCR can only be written once after reset!
344 *-----------------------------------------------------------------------
345 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
346 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200347#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_PBME | SYPCR_LBME | \
wdenke2211742002-11-02 23:30:20 +0000348 SYPCR_SWRI | SYPCR_SWP)
349
350/*-----------------------------------------------------------------------
351 * TMCNTSC - Time Counter Status and Control 4-40
352 *-----------------------------------------------------------------------
353 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
354 * and enable Time Counter
355 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200356#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC | TMCNTSC_ALR | TMCNTSC_TCF | TMCNTSC_TCE)
wdenke2211742002-11-02 23:30:20 +0000357
358/*-----------------------------------------------------------------------
359 * PISCR - Periodic Interrupt Status and Control 4-42
360 *-----------------------------------------------------------------------
361 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
362 * Periodic timer
363 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200364#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
wdenke2211742002-11-02 23:30:20 +0000365
366/*-----------------------------------------------------------------------
367 * SCCR - System Clock Control 9-8
368 *-----------------------------------------------------------------------
369 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200370#define CONFIG_SYS_SCCR 0x00000000
wdenke2211742002-11-02 23:30:20 +0000371
372/*-----------------------------------------------------------------------
373 * RCCR - RISC Controller Configuration 13-7
374 *-----------------------------------------------------------------------
375 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200376#define CONFIG_SYS_RCCR 0
wdenke2211742002-11-02 23:30:20 +0000377
378/*
379 * Init Memory Controller:
380 */
381
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200382#define CONFIG_SYS_PSDMR 0x494D2452
383#define CONFIG_SYS_LSDMR 0x49492552
wdenke2211742002-11-02 23:30:20 +0000384
385/* Flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200386#define CONFIG_SYS_BR0_PRELIM (PHYS_FLASH | BRx_V)
387#define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(PHYS_FLASH_SIZE) | \
wdenke2211742002-11-02 23:30:20 +0000388 ORxG_BCTLD | \
389 ORxG_SCY_5_CLK)
390
391/* DPRAM to the PCI BUS on the protocol board */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200392#define CONFIG_SYS_BR1_PRELIM (PHYS_DPRAM_PCI | BRx_V)
393#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(PHYS_DPRAM_PCI_SIZE) | \
wdenke2211742002-11-02 23:30:20 +0000394 ORxG_ACS_DIV4)
395
396/* 60x Bus SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200397#define CONFIG_SYS_BR2_PRELIM (PHYS_SDRAM_60X | BRx_MS_SDRAM_P | BRx_V)
398#define CONFIG_SYS_OR2_PRELIM (ORxS_SIZE_TO_AM(PHYS_SDRAM_60X_SIZE) | \
wdenke2211742002-11-02 23:30:20 +0000399 ORxS_BPD_4 | \
400 ORxS_ROWST_PBI1_A2 | \
401 ORxS_NUMR_13 | \
402 ORxS_IBID)
403
404/* Virtex-FPGA - Register */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200405#define CONFIG_SYS_BR3_PRELIM (PHYS_VIRTEX_REGISTER | BRx_V)
406#define CONFIG_SYS_OR3_PRELIM (ORxS_SIZE_TO_AM(PHYS_VIRTEX_REGISTER_SIZE) | \
wdenk8bde7f72003-06-27 21:31:46 +0000407 ORxG_SCY_1_CLK | \
408 ORxG_ACS_DIV2 | \
409 ORxG_CSNT )
wdenke2211742002-11-02 23:30:20 +0000410
411/* local bus SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200412#define CONFIG_SYS_BR4_PRELIM (PHYS_SDRAM_LOCAL | BRx_PS_32 | BRx_MS_SDRAM_L | BRx_V)
413#define CONFIG_SYS_OR4_PRELIM (ORxS_SIZE_TO_AM(PHYS_SDRAM_LOCAL_SIZE) | \
wdenke2211742002-11-02 23:30:20 +0000414 ORxS_BPD_4 | \
415 ORxS_ROWST_PBI1_A4 | \
416 ORxS_NUMR_13)
417
418/* DPRAM to the Sharc-Bus on the protocol board */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200419#define CONFIG_SYS_BR5_PRELIM (PHYS_DPRAM_SHARC | BRx_V)
420#define CONFIG_SYS_OR5_PRELIM (P2SZ_TO_AM(PHYS_DPRAM_SHARC_SIZE) | \
wdenke2211742002-11-02 23:30:20 +0000421 ORxG_ACS_DIV4)
422
wdenke2211742002-11-02 23:30:20 +0000423#endif /* __CONFIG_H */