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Haiying Wang765547d2009-03-27 17:02:45 -04001/*
Kumar Galae5fe96b2011-01-04 18:04:01 -06002 * Copyright 2009-2011 Freescale Semiconductor, Inc.
Haiying Wang765547d2009-03-27 17:02:45 -04003 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02004 * SPDX-License-Identifier: GPL-2.0+
Haiying Wang765547d2009-03-27 17:02:45 -04005 */
6
7/*
8 * mpc8569mds board configuration file
9 */
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13/* High Level Configuration Options */
14#define CONFIG_BOOKE 1 /* BOOKE */
15#define CONFIG_E500 1 /* BOOKE e500 family */
Haiying Wang765547d2009-03-27 17:02:45 -040016#define CONFIG_MPC8569 1 /* MPC8569 specific */
17#define CONFIG_MPC8569MDS 1 /* MPC8569MDS board specific */
18
19#define CONFIG_FSL_ELBC 1 /* Has Enhance localbus controller */
20
Kumar Galae5fe96b2011-01-04 18:04:01 -060021#define CONFIG_SYS_SRIO
22#define CONFIG_SRIO1 /* SRIO port 1 */
23
Haiying Wang765547d2009-03-27 17:02:45 -040024#define CONFIG_PCI 1 /* Disable PCI/PCIE */
25#define CONFIG_PCIE1 1 /* PCIE controller */
26#define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */
Gabor Juhos842033e2013-05-30 07:06:12 +000027#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
Haiying Wang765547d2009-03-27 17:02:45 -040028#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
29#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
30#define CONFIG_QE /* Enable QE */
31#define CONFIG_ENV_OVERWRITE
32#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
33
Haiying Wang765547d2009-03-27 17:02:45 -040034#ifndef __ASSEMBLY__
35extern unsigned long get_clock_freq(void);
36#endif
37/* Replace a call to get_clock_freq (after it is implemented)*/
Dave Liu67351042009-05-18 17:49:23 +080038#define CONFIG_SYS_CLK_FREQ 66666666
39#define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ
Haiying Wang765547d2009-03-27 17:02:45 -040040
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020041#ifdef CONFIG_ATM
Liu Yuc95d5412009-11-27 15:31:52 +080042#define CONFIG_PQ_MDS_PIB
43#define CONFIG_PQ_MDS_PIB_ATM
44#endif
45
Haiying Wang765547d2009-03-27 17:02:45 -040046/*
47 * These can be toggled for performance analysis, otherwise use default.
48 */
49#define CONFIG_L2_CACHE /* toggle L2 cache */
50#define CONFIG_BTB /* toggle branch predition */
51
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020052#ifdef CONFIG_NAND
Liu Yu674ef7b2010-01-18 19:03:28 +080053#define CONFIG_NAND_U_BOOT 1
54#define CONFIG_RAMBOOT_NAND 1
Haiying Wang96196a12010-11-10 15:37:13 -050055#ifdef CONFIG_NAND_SPL
56#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
57#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
58#else
Kumar Gala00203c62011-01-31 15:57:01 -060059#define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds
Wolfgang Denk2ae18242010-10-06 09:05:45 +020060#define CONFIG_SYS_TEXT_BASE 0xf8f82000
61#endif
Haiying Wang96196a12010-11-10 15:37:13 -050062#endif
Wolfgang Denk2ae18242010-10-06 09:05:45 +020063
64#ifndef CONFIG_SYS_TEXT_BASE
65#define CONFIG_SYS_TEXT_BASE 0xfff80000
Liu Yu674ef7b2010-01-18 19:03:28 +080066#endif
67
Haiying Wang96196a12010-11-10 15:37:13 -050068#ifndef CONFIG_SYS_MONITOR_BASE
69#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
70#endif
71
Haiying Wang765547d2009-03-27 17:02:45 -040072/*
73 * Only possible on E500 Version 2 or newer cores.
74 */
75#define CONFIG_ENABLE_36BIT_PHYS 1
76
77#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
Haiying Wang3aed5502010-09-29 13:31:35 -040078#define CONFIG_BOARD_EARLY_INIT_R 1
Anton Vorontsov7f52ed52009-10-15 17:47:06 +040079#define CONFIG_HWCONFIG
Haiying Wang765547d2009-03-27 17:02:45 -040080
81#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
82#define CONFIG_SYS_MEMTEST_END 0x00400000
83
84/*
Liu Yu674ef7b2010-01-18 19:03:28 +080085 * Config the L2 Cache as L2 SRAM
86 */
87#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
88#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
89#define CONFIG_SYS_L2_SIZE (512 << 10)
90#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
91
Timur Tabie46fedf2011-08-04 18:03:41 -050092#define CONFIG_SYS_CCSRBAR 0xe0000000
93#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
Haiying Wang765547d2009-03-27 17:02:45 -040094
Kumar Gala8d22ddc2011-11-09 09:10:49 -060095#if defined(CONFIG_NAND_SPL)
Timur Tabie46fedf2011-08-04 18:03:41 -050096#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
Liu Yu674ef7b2010-01-18 19:03:28 +080097#endif
98
Haiying Wang765547d2009-03-27 17:02:45 -040099/* DDR Setup */
York Sun5614e712013-09-30 09:22:09 -0700100#define CONFIG_SYS_FSL_DDR3
Haiying Wang765547d2009-03-27 17:02:45 -0400101#undef CONFIG_FSL_DDR_INTERACTIVE
102#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
103#define CONFIG_DDR_SPD
Haiying Wang765547d2009-03-27 17:02:45 -0400104#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
105
106#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
107
108#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
109 /* DDR is system memory*/
110#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
111
112#define CONFIG_NUM_DDR_CONTROLLERS 1
113#define CONFIG_DIMM_SLOTS_PER_CTLR 1
114#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
115
116/* I2C addresses of SPD EEPROMs */
Kumar Galac39f44d2011-01-31 22:18:47 -0600117#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
Haiying Wang765547d2009-03-27 17:02:45 -0400118
119/* These are used when DDR doesn't use SPD. */
120#define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1024MB */
121#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
122#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
123#define CONFIG_SYS_DDR_TIMING_3 0x00020000
124#define CONFIG_SYS_DDR_TIMING_0 0x00330004
125#define CONFIG_SYS_DDR_TIMING_1 0x6F6B4644
126#define CONFIG_SYS_DDR_TIMING_2 0x002888D0
127#define CONFIG_SYS_DDR_SDRAM_CFG 0x47000000
128#define CONFIG_SYS_DDR_SDRAM_CFG_2 0x04401040
129#define CONFIG_SYS_DDR_SDRAM_MODE 0x40401521
130#define CONFIG_SYS_DDR_SDRAM_MODE_2 0x8000C000
131#define CONFIG_SYS_DDR_SDRAM_INTERVAL 0x03E00000
132#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
133#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x01000000
134#define CONFIG_SYS_DDR_TIMING_4 0x00220001
135#define CONFIG_SYS_DDR_TIMING_5 0x03402400
136#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600
137#define CONFIG_SYS_DDR_WRLVL_CNTL 0x0655A604
138#define CONFIG_SYS_DDR_CDR_1 0x80040000
139#define CONFIG_SYS_DDR_CDR_2 0x00000000
140#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
141#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
142#define CONFIG_SYS_DDR_CONTROL 0xc7000000 /* Type = DDR3 */
143#define CONFIG_SYS_DDR_CONTROL2 0x24400000
144
145#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
146#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
147#define CONFIG_SYS_DDR_SBE 0x00010000
148
149#undef CONFIG_CLOCKS_IN_MHZ
150
151/*
152 * Local Bus Definitions
153 */
154
155#define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */
156#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
157
158#define CONFIG_SYS_BCSR_BASE 0xf8000000
159#define CONFIG_SYS_BCSR_BASE_PHYS CONFIG_SYS_BCSR_BASE
160
161/*Chip select 0 - Flash*/
Liu Yu674ef7b2010-01-18 19:03:28 +0800162#define CONFIG_FLASH_BR_PRELIM 0xfe000801
163#define CONFIG_FLASH_OR_PRELIM 0xfe000ff7
Haiying Wang765547d2009-03-27 17:02:45 -0400164
Haiying Wang399b53c2009-05-20 12:30:32 -0400165/*Chip select 1 - BCSR*/
Haiying Wang765547d2009-03-27 17:02:45 -0400166#define CONFIG_SYS_BR1_PRELIM 0xf8000801
167#define CONFIG_SYS_OR1_PRELIM 0xffffe9f7
168
Haiying Wang399b53c2009-05-20 12:30:32 -0400169/*Chip select 4 - PIB*/
170#define CONFIG_SYS_BR4_PRELIM 0xf8008801
171#define CONFIG_SYS_OR4_PRELIM 0xffffe9f7
172
173/*Chip select 5 - PIB*/
174#define CONFIG_SYS_BR5_PRELIM 0xf8010801
175#define CONFIG_SYS_OR5_PRELIM 0xffffe9f7
176
Haiying Wang765547d2009-03-27 17:02:45 -0400177#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
178#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
179#undef CONFIG_SYS_FLASH_CHECKSUM
180#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
181#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
182
Kumar Galaa55bb832010-11-29 14:32:11 -0600183#if defined(CONFIG_RAMBOOT_NAND)
Liu Yu674ef7b2010-01-18 19:03:28 +0800184#define CONFIG_SYS_RAMBOOT
Kumar Galaa55bb832010-11-29 14:32:11 -0600185#define CONFIG_SYS_EXTRA_ENV_RELOC
Liu Yu674ef7b2010-01-18 19:03:28 +0800186#else
187#undef CONFIG_SYS_RAMBOOT
188#endif
189
Haiying Wang765547d2009-03-27 17:02:45 -0400190#define CONFIG_FLASH_CFI_DRIVER
191#define CONFIG_SYS_FLASH_CFI
192#define CONFIG_SYS_FLASH_EMPTY_INFO
193
Anton Vorontsova29155e2009-10-15 17:47:08 +0400194/* Chip select 3 - NAND */
Liu Yu674ef7b2010-01-18 19:03:28 +0800195#ifndef CONFIG_NAND_SPL
Anton Vorontsova29155e2009-10-15 17:47:08 +0400196#define CONFIG_SYS_NAND_BASE 0xFC000000
Liu Yu674ef7b2010-01-18 19:03:28 +0800197#else
198#define CONFIG_SYS_NAND_BASE 0xFFF00000
199#endif
200
201/* NAND boot: 4K NAND loader config */
202#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
203#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
204#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
205#define CONFIG_SYS_NAND_U_BOOT_START \
206 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
207#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
208#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
209#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
210
Anton Vorontsova29155e2009-10-15 17:47:08 +0400211#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
212#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, }
213#define CONFIG_SYS_MAX_NAND_DEVICE 1
214#define CONFIG_MTD_NAND_VERIFY_WRITE 1
215#define CONFIG_CMD_NAND 1
216#define CONFIG_NAND_FSL_ELBC 1
217#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
Matthew McClintocka3055c52011-04-05 14:39:33 -0500218#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \
Anton Vorontsova29155e2009-10-15 17:47:08 +0400219 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
220 | BR_PS_8 /* Port Size = 8 bit */ \
221 | BR_MS_FCM /* MSEL = FCM */ \
222 | BR_V) /* valid */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500223#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
Anton Vorontsova29155e2009-10-15 17:47:08 +0400224 | OR_FCM_CSCT \
225 | OR_FCM_CST \
226 | OR_FCM_CHT \
227 | OR_FCM_SCY_1 \
228 | OR_FCM_TRLX \
229 | OR_FCM_EHTR)
Liu Yu674ef7b2010-01-18 19:03:28 +0800230
231#ifdef CONFIG_RAMBOOT_NAND
Matthew McClintocka3055c52011-04-05 14:39:33 -0500232#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
233#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM/* NAND Options */
Liu Yu674ef7b2010-01-18 19:03:28 +0800234#define CONFIG_SYS_BR3_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
235#define CONFIG_SYS_OR3_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
236#else
237#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
238#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500239#define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
240#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
Liu Yu674ef7b2010-01-18 19:03:28 +0800241#endif
Haiying Wang765547d2009-03-27 17:02:45 -0400242
Haiying Wang765547d2009-03-27 17:02:45 -0400243#define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */
244#define CONFIG_SYS_LBC_LBCR 0x00040000 /* LB config reg */
245#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
246#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
247
248#define CONFIG_SYS_INIT_RAM_LOCK 1
249#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200250#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
Haiying Wang765547d2009-03-27 17:02:45 -0400251
Haiying Wang765547d2009-03-27 17:02:45 -0400252#define CONFIG_SYS_GBL_DATA_OFFSET \
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200253 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Haiying Wang765547d2009-03-27 17:02:45 -0400254#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
255
256#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
Haiying Wangfb279492009-06-04 16:12:39 -0400257#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
Haiying Wang765547d2009-03-27 17:02:45 -0400258
259/* Serial Port */
260#define CONFIG_CONS_INDEX 1
Haiying Wang765547d2009-03-27 17:02:45 -0400261#define CONFIG_SYS_NS16550
262#define CONFIG_SYS_NS16550_SERIAL
263#define CONFIG_SYS_NS16550_REG_SIZE 1
264#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Kumar Gala93341902010-04-07 01:34:11 -0500265#ifdef CONFIG_NAND_SPL
266#define CONFIG_NS16550_MIN_FUNCTIONS
267#endif
Haiying Wang765547d2009-03-27 17:02:45 -0400268
269#define CONFIG_SYS_BAUDRATE_TABLE \
270 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
271
272#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
273#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
274
275/* Use the HUSH parser*/
276#define CONFIG_SYS_HUSH_PARSER
277#ifdef CONFIG_SYS_HUSH_PARSER
Haiying Wang765547d2009-03-27 17:02:45 -0400278#endif
279
280/* pass open firmware flat tree */
281#define CONFIG_OF_LIBFDT 1
282#define CONFIG_OF_BOARD_SETUP 1
283#define CONFIG_OF_STDOUT_VIA_ALIAS 1
284
Haiying Wang765547d2009-03-27 17:02:45 -0400285/*
286 * I2C
287 */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200288#define CONFIG_SYS_I2C
289#define CONFIG_SYS_I2C_FSL
290#define CONFIG_SYS_FSL_I2C_SPEED 400000
291#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
292#define CONFIG_SYS_FSL_I2C2_SPEED 400000
293#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
294#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
295#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
296#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
Haiying Wang765547d2009-03-27 17:02:45 -0400297
298/*
299 * I2C2 EEPROM
300 */
301#define CONFIG_ID_EEPROM
302#ifdef CONFIG_ID_EEPROM
303#define CONFIG_SYS_I2C_EEPROM_NXID
304#endif
305#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
306#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
307#define CONFIG_SYS_EEPROM_BUS_NUM 1
308
309#define PLPPAR1_I2C_BIT_MASK 0x0000000F
310#define PLPPAR1_I2C2_VAL 0x00000000
Anton Vorontsov7f52ed52009-10-15 17:47:06 +0400311#define PLPPAR1_ESDHC_VAL 0x0000000A
Haiying Wang765547d2009-03-27 17:02:45 -0400312#define PLPDIR1_I2C_BIT_MASK 0x0000000F
313#define PLPDIR1_I2C2_VAL 0x0000000F
Anton Vorontsov7f52ed52009-10-15 17:47:06 +0400314#define PLPDIR1_ESDHC_VAL 0x00000006
Anton Vorontsovc4ca10f2009-12-16 01:14:31 +0300315#define PLPPAR1_UART0_BIT_MASK 0x00000fc0
316#define PLPPAR1_ESDHC_4BITS_VAL 0x00000a80
317#define PLPDIR1_UART0_BIT_MASK 0x00000fc0
318#define PLPDIR1_ESDHC_4BITS_VAL 0x00000a80
Haiying Wang765547d2009-03-27 17:02:45 -0400319
320/*
321 * General PCI
322 * Memory Addresses are mapped 1-1. I/O is mapped from 0
323 */
Kumar Gala94f2bc42010-12-17 10:18:07 -0600324#define CONFIG_SYS_PCIE1_NAME "Slot"
Haiying Wang765547d2009-03-27 17:02:45 -0400325#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
326#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
327#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
328#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
329#define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000
330#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
331#define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000
332#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
333
Kumar Galae5fe96b2011-01-04 18:04:01 -0600334#define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000
335#define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000
336#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS
337#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
Haiying Wang765547d2009-03-27 17:02:45 -0400338
339#ifdef CONFIG_QE
340/*
341 * QE UEC ethernet configuration
342 */
Haiying Wangf82107f2009-05-20 12:30:37 -0400343#define CONFIG_SYS_UCC_RGMII_MODE /* Set UCC work at RGMII by default */
344#undef CONFIG_SYS_UCC_RMII_MODE /* Set UCC work at RMII mode */
Haiying Wang765547d2009-03-27 17:02:45 -0400345
346#define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
347#define CONFIG_UEC_ETH
Kim Phillips78b7a8e2010-07-26 18:34:57 -0500348#define CONFIG_ETHPRIME "UEC0"
Haiying Wang765547d2009-03-27 17:02:45 -0400349#define CONFIG_PHY_MODE_NEED_CHANGE
350
351#define CONFIG_UEC_ETH1 /* GETH1 */
352#define CONFIG_HAS_ETH0
353
354#ifdef CONFIG_UEC_ETH1
355#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
356#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE
Haiying Wangf82107f2009-05-20 12:30:37 -0400357#if defined(CONFIG_SYS_UCC_RGMII_MODE)
Haiying Wang765547d2009-03-27 17:02:45 -0400358#define CONFIG_SYS_UEC1_TX_CLK QE_CLK12
359#define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH
360#define CONFIG_SYS_UEC1_PHY_ADDR 7
Andy Fleming865ff852011-04-13 00:37:12 -0500361#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
Heiko Schocher582c55a2010-01-20 09:04:28 +0100362#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
Haiying Wangf82107f2009-05-20 12:30:37 -0400363#elif defined(CONFIG_SYS_UCC_RMII_MODE)
364#define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 /* CLK16 for RMII */
365#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
366#define CONFIG_SYS_UEC1_PHY_ADDR 8 /* 0x8 for RMII */
Andy Fleming865ff852011-04-13 00:37:12 -0500367#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
Heiko Schocher582c55a2010-01-20 09:04:28 +0100368#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
Haiying Wangf82107f2009-05-20 12:30:37 -0400369#endif /* CONFIG_SYS_UCC_RGMII_MODE */
370#endif /* CONFIG_UEC_ETH1 */
Haiying Wang765547d2009-03-27 17:02:45 -0400371
372#define CONFIG_UEC_ETH2 /* GETH2 */
373#define CONFIG_HAS_ETH1
374
375#ifdef CONFIG_UEC_ETH2
376#define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */
377#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE
Haiying Wangf82107f2009-05-20 12:30:37 -0400378#if defined(CONFIG_SYS_UCC_RGMII_MODE)
Haiying Wang765547d2009-03-27 17:02:45 -0400379#define CONFIG_SYS_UEC2_TX_CLK QE_CLK17
380#define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH
381#define CONFIG_SYS_UEC2_PHY_ADDR 1
Andy Fleming865ff852011-04-13 00:37:12 -0500382#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
Heiko Schocher582c55a2010-01-20 09:04:28 +0100383#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
Haiying Wangf82107f2009-05-20 12:30:37 -0400384#elif defined(CONFIG_SYS_UCC_RMII_MODE)
385#define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 /* CLK 16 for RMII */
386#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
387#define CONFIG_SYS_UEC2_PHY_ADDR 0x9 /* 0x9 for RMII */
Andy Fleming865ff852011-04-13 00:37:12 -0500388#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
Heiko Schocher582c55a2010-01-20 09:04:28 +0100389#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
Haiying Wangf82107f2009-05-20 12:30:37 -0400390#endif /* CONFIG_SYS_UCC_RGMII_MODE */
391#endif /* CONFIG_UEC_ETH2 */
Haiying Wang765547d2009-03-27 17:02:45 -0400392
Haiying Wang750098d2009-05-20 12:30:36 -0400393#define CONFIG_UEC_ETH3 /* GETH3 */
394#define CONFIG_HAS_ETH2
395
396#ifdef CONFIG_UEC_ETH3
397#define CONFIG_SYS_UEC3_UCC_NUM 2 /* UCC3 */
398#define CONFIG_SYS_UEC3_RX_CLK QE_CLK_NONE
Haiying Wangf82107f2009-05-20 12:30:37 -0400399#if defined(CONFIG_SYS_UCC_RGMII_MODE)
Haiying Wang750098d2009-05-20 12:30:36 -0400400#define CONFIG_SYS_UEC3_TX_CLK QE_CLK12
401#define CONFIG_SYS_UEC3_ETH_TYPE GIGA_ETH
402#define CONFIG_SYS_UEC3_PHY_ADDR 2
Andy Fleming865ff852011-04-13 00:37:12 -0500403#define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
Heiko Schocher582c55a2010-01-20 09:04:28 +0100404#define CONFIG_SYS_UEC3_INTERFACE_SPEED 1000
Haiying Wangf82107f2009-05-20 12:30:37 -0400405#elif defined(CONFIG_SYS_UCC_RMII_MODE)
406#define CONFIG_SYS_UEC3_TX_CLK QE_CLK16 /* CLK_16 for RMII */
407#define CONFIG_SYS_UEC3_ETH_TYPE FAST_ETH
408#define CONFIG_SYS_UEC3_PHY_ADDR 0xA /* 0xA for RMII */
Andy Fleming865ff852011-04-13 00:37:12 -0500409#define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
Heiko Schocher582c55a2010-01-20 09:04:28 +0100410#define CONFIG_SYS_UEC3_INTERFACE_SPEED 100
Haiying Wangf82107f2009-05-20 12:30:37 -0400411#endif /* CONFIG_SYS_UCC_RGMII_MODE */
412#endif /* CONFIG_UEC_ETH3 */
Haiying Wang750098d2009-05-20 12:30:36 -0400413
414#define CONFIG_UEC_ETH4 /* GETH4 */
415#define CONFIG_HAS_ETH3
416
417#ifdef CONFIG_UEC_ETH4
418#define CONFIG_SYS_UEC4_UCC_NUM 3 /* UCC4 */
419#define CONFIG_SYS_UEC4_RX_CLK QE_CLK_NONE
Haiying Wangf82107f2009-05-20 12:30:37 -0400420#if defined(CONFIG_SYS_UCC_RGMII_MODE)
Haiying Wang750098d2009-05-20 12:30:36 -0400421#define CONFIG_SYS_UEC4_TX_CLK QE_CLK17
422#define CONFIG_SYS_UEC4_ETH_TYPE GIGA_ETH
423#define CONFIG_SYS_UEC4_PHY_ADDR 3
Andy Fleming865ff852011-04-13 00:37:12 -0500424#define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
Heiko Schocher582c55a2010-01-20 09:04:28 +0100425#define CONFIG_SYS_UEC4_INTERFACE_SPEED 1000
Haiying Wangf82107f2009-05-20 12:30:37 -0400426#elif defined(CONFIG_SYS_UCC_RMII_MODE)
427#define CONFIG_SYS_UEC4_TX_CLK QE_CLK16 /* CLK16 for RMII */
428#define CONFIG_SYS_UEC4_ETH_TYPE FAST_ETH
429#define CONFIG_SYS_UEC4_PHY_ADDR 0xB /* 0xB for RMII */
Andy Fleming865ff852011-04-13 00:37:12 -0500430#define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
Heiko Schocher582c55a2010-01-20 09:04:28 +0100431#define CONFIG_SYS_UEC4_INTERFACE_SPEED 100
Haiying Wangf82107f2009-05-20 12:30:37 -0400432#endif /* CONFIG_SYS_UCC_RGMII_MODE */
433#endif /* CONFIG_UEC_ETH4 */
Haiying Wang3bd8e532009-05-20 12:30:41 -0400434
435#undef CONFIG_UEC_ETH6 /* GETH6 */
436#define CONFIG_HAS_ETH5
437
438#ifdef CONFIG_UEC_ETH6
439#define CONFIG_SYS_UEC6_UCC_NUM 5 /* UCC6 */
440#define CONFIG_SYS_UEC6_RX_CLK QE_CLK_NONE
441#define CONFIG_SYS_UEC6_TX_CLK QE_CLK_NONE
442#define CONFIG_SYS_UEC6_ETH_TYPE GIGA_ETH
443#define CONFIG_SYS_UEC6_PHY_ADDR 4
Andy Fleming865ff852011-04-13 00:37:12 -0500444#define CONFIG_SYS_UEC6_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII
Heiko Schocher582c55a2010-01-20 09:04:28 +0100445#define CONFIG_SYS_UEC6_INTERFACE_SPEED 1000
Haiying Wang3bd8e532009-05-20 12:30:41 -0400446#endif /* CONFIG_UEC_ETH6 */
447
448#undef CONFIG_UEC_ETH8 /* GETH8 */
449#define CONFIG_HAS_ETH7
450
451#ifdef CONFIG_UEC_ETH8
452#define CONFIG_SYS_UEC8_UCC_NUM 7 /* UCC8 */
453#define CONFIG_SYS_UEC8_RX_CLK QE_CLK_NONE
454#define CONFIG_SYS_UEC8_TX_CLK QE_CLK_NONE
455#define CONFIG_SYS_UEC8_ETH_TYPE GIGA_ETH
456#define CONFIG_SYS_UEC8_PHY_ADDR 6
Andy Fleming865ff852011-04-13 00:37:12 -0500457#define CONFIG_SYS_UEC8_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII
Heiko Schocher582c55a2010-01-20 09:04:28 +0100458#define CONFIG_SYS_UEC8_INTERFACE_SPEED 1000
Haiying Wang3bd8e532009-05-20 12:30:41 -0400459#endif /* CONFIG_UEC_ETH8 */
460
Haiying Wang765547d2009-03-27 17:02:45 -0400461#endif /* CONFIG_QE */
462
463#if defined(CONFIG_PCI)
464
Haiying Wang765547d2009-03-27 17:02:45 -0400465#define CONFIG_PCI_PNP /* do pci plug-and-play */
466
467#undef CONFIG_EEPRO100
468#undef CONFIG_TULIP
Kumar Gala16855ec2010-11-09 23:19:50 -0600469#define CONFIG_E1000 /* Define e1000 pci Ethernet card */
Haiying Wang765547d2009-03-27 17:02:45 -0400470
471#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
472
473#endif /* CONFIG_PCI */
474
Haiying Wang765547d2009-03-27 17:02:45 -0400475/*
476 * Environment
477 */
Liu Yu674ef7b2010-01-18 19:03:28 +0800478#if defined(CONFIG_SYS_RAMBOOT)
479#if defined(CONFIG_RAMBOOT_NAND)
480#define CONFIG_ENV_IS_IN_NAND 1
481#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
482#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
483#endif
484#else
Haiying Wang765547d2009-03-27 17:02:45 -0400485#define CONFIG_ENV_IS_IN_FLASH 1
Haiying Wangfb279492009-06-04 16:12:39 -0400486#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
Haiying Wang1b8e4fa2010-09-29 13:44:14 -0400487#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
488#define CONFIG_ENV_SIZE 0x2000
Liu Yu674ef7b2010-01-18 19:03:28 +0800489#endif
Haiying Wang765547d2009-03-27 17:02:45 -0400490
491#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
492#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
493
494/* QE microcode/firmware address */
Timur Tabif2717b42011-11-22 09:21:25 -0600495#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
496#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xfff00000
Haiying Wang765547d2009-03-27 17:02:45 -0400497
498/*
499 * BOOTP options
500 */
501#define CONFIG_BOOTP_BOOTFILESIZE
502#define CONFIG_BOOTP_BOOTPATH
503#define CONFIG_BOOTP_GATEWAY
504#define CONFIG_BOOTP_HOSTNAME
505
506
507/*
508 * Command line configuration.
509 */
510#include <config_cmd_default.h>
511
512#define CONFIG_CMD_PING
513#define CONFIG_CMD_I2C
514#define CONFIG_CMD_MII
515#define CONFIG_CMD_ELF
516#define CONFIG_CMD_IRQ
517#define CONFIG_CMD_SETEXPR
Becky Bruce199e2622010-06-17 11:37:25 -0500518#define CONFIG_CMD_REGINFO
Haiying Wang765547d2009-03-27 17:02:45 -0400519
520#if defined(CONFIG_PCI)
521 #define CONFIG_CMD_PCI
522#endif
523
524
525#undef CONFIG_WATCHDOG /* watchdog disabled */
526
Anton Vorontsov7f52ed52009-10-15 17:47:06 +0400527#define CONFIG_MMC 1
528
529#ifdef CONFIG_MMC
530#define CONFIG_FSL_ESDHC
Chenhui Zhaoa6da8b82011-01-04 17:23:05 +0800531#define CONFIG_FSL_ESDHC_PIN_MUX
Anton Vorontsov7f52ed52009-10-15 17:47:06 +0400532#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
533#define CONFIG_CMD_MMC
534#define CONFIG_GENERIC_MMC
535#define CONFIG_CMD_EXT2
536#define CONFIG_CMD_FAT
537#define CONFIG_DOS_PARTITION
538#endif
539
Haiying Wang765547d2009-03-27 17:02:45 -0400540/*
541 * Miscellaneous configurable options
542 */
Kim Phillips5be58f52010-07-14 19:47:18 -0500543#define CONFIG_SYS_LONGHELP /* undef to save memory */
544#define CONFIG_CMDLINE_EDITING /* Command-line editing */
545#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Haiying Wang765547d2009-03-27 17:02:45 -0400546#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Haiying Wang765547d2009-03-27 17:02:45 -0400547#if defined(CONFIG_CMD_KGDB)
548#define CONFIG_SYS_CBSIZE 2048 /* Console I/O Buffer Size */
549#else
550#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
551#endif
552#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
553 /* Print Buffer Size */
554#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
555#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
556 /* Boot Argument Buffer Size */
Haiying Wang765547d2009-03-27 17:02:45 -0400557
558/*
559 * For booting Linux, the board info and command line data
Kumar Galaa832ac42011-04-28 10:13:41 -0500560 * have to be in the first 64 MB of memory, since this is
Haiying Wang765547d2009-03-27 17:02:45 -0400561 * the maximum mapped by the Linux kernel during initialization.
562 */
Kumar Galaa832ac42011-04-28 10:13:41 -0500563#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
564#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
Haiying Wang765547d2009-03-27 17:02:45 -0400565
Haiying Wang765547d2009-03-27 17:02:45 -0400566#if defined(CONFIG_CMD_KGDB)
567#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Haiying Wang765547d2009-03-27 17:02:45 -0400568#endif
569
570/*
571 * Environment Configuration
572 */
573#define CONFIG_HOSTNAME mpc8569mds
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000574#define CONFIG_ROOTPATH "/nfsroot"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000575#define CONFIG_BOOTFILE "your.uImage"
Haiying Wang765547d2009-03-27 17:02:45 -0400576
577#define CONFIG_SERVERIP 192.168.1.1
578#define CONFIG_GATEWAYIP 192.168.1.1
579#define CONFIG_NETMASK 255.255.255.0
580
581#define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/
582
583#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
584#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
585
586#define CONFIG_BAUDRATE 115200
587
588#define CONFIG_EXTRA_ENV_SETTINGS \
589 "netdev=eth0\0" \
590 "consoledev=ttyS0\0" \
591 "ramdiskaddr=600000\0" \
592 "ramdiskfile=your.ramdisk.u-boot\0" \
593 "fdtaddr=400000\0" \
594 "fdtfile=your.fdt.dtb\0" \
595 "nfsargs=setenv bootargs root=/dev/nfs rw " \
596 "nfsroot=$serverip:$rootpath " \
597 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
598 "console=$consoledev,$baudrate $othbootargs\0" \
599 "ramargs=setenv bootargs root=/dev/ram rw " \
600 "console=$consoledev,$baudrate $othbootargs\0" \
601
602#define CONFIG_NFSBOOTCOMMAND \
603 "run nfsargs;" \
604 "tftp $loadaddr $bootfile;" \
605 "tftp $fdtaddr $fdtfile;" \
606 "bootm $loadaddr - $fdtaddr"
607
608#define CONFIG_RAMBOOTCOMMAND \
609 "run ramargs;" \
610 "tftp $ramdiskaddr $ramdiskfile;" \
611 "tftp $loadaddr $bootfile;" \
612 "bootm $loadaddr $ramdiskaddr"
613
614#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
615
616#endif /* __CONFIG_H */