blob: f06523ab99b2fa6ea826e6521e7fa952c45ace73 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Masahiro Yamada26f820f2015-01-13 12:44:36 +09002/*
Masahiro Yamada4e3d8402016-07-19 21:56:13 +09003 * Copyright (C) 2014 Panasonic Corporation
4 * Copyright (C) 2015-2016 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada26f820f2015-01-13 12:44:36 +09006 */
7
Simon Glass336d4612020-02-03 07:36:16 -07008#include <dm/device_compat.h>
Masahiro Yamada804cf1c2017-10-13 19:21:57 +09009#include <linux/delay.h>
10#include <linux/errno.h>
Masahiro Yamadaf6e7f072015-05-29 17:30:00 +090011#include <linux/io.h>
Masahiro Yamada336399f2016-03-24 22:32:40 +090012#include <linux/sizes.h>
Masahiro Yamada804cf1c2017-10-13 19:21:57 +090013#include <linux/types.h>
14#include <dm.h>
Masahiro Yamada26f820f2015-01-13 12:44:36 +090015#include <fdtdec.h>
Masahiro Yamada804cf1c2017-10-13 19:21:57 +090016#include <i2c.h>
Masahiro Yamada26f820f2015-01-13 12:44:36 +090017
Masahiro Yamada26f820f2015-01-13 12:44:36 +090018struct uniphier_i2c_regs {
19 u32 dtrm; /* data transmission */
20#define I2C_DTRM_STA (1 << 10)
21#define I2C_DTRM_STO (1 << 9)
22#define I2C_DTRM_NACK (1 << 8)
23#define I2C_DTRM_RD (1 << 0)
24 u32 drec; /* data reception */
25#define I2C_DREC_STS (1 << 12)
26#define I2C_DREC_LRB (1 << 11)
27#define I2C_DREC_LAB (1 << 9)
28 u32 myad; /* slave address */
29 u32 clk; /* clock frequency control */
30 u32 brst; /* bus reset */
31#define I2C_BRST_FOEN (1 << 1)
32#define I2C_BRST_BRST (1 << 0)
33 u32 hold; /* hold time control */
34 u32 bsts; /* bus status monitor */
35 u32 noise; /* noise filter control */
36 u32 setup; /* setup time control */
37};
38
39#define IOBUS_FREQ 100000000
40
Masahiro Yamada804cf1c2017-10-13 19:21:57 +090041struct uniphier_i2c_priv {
42 struct udevice *dev;
Masahiro Yamada26f820f2015-01-13 12:44:36 +090043 struct uniphier_i2c_regs __iomem *regs; /* register base */
44 unsigned long input_clk; /* master clock (Hz) */
45 unsigned long wait_us; /* wait for every byte transfer (us) */
46};
47
48static int uniphier_i2c_probe(struct udevice *dev)
49{
50 fdt_addr_t addr;
Masahiro Yamada804cf1c2017-10-13 19:21:57 +090051 struct uniphier_i2c_priv *priv = dev_get_priv(dev);
Masahiro Yamada26f820f2015-01-13 12:44:36 +090052
Simon Glassa821c4a2017-05-17 17:18:05 -060053 addr = devfdt_get_addr(dev);
Masahiro Yamada336399f2016-03-24 22:32:40 +090054 if (addr == FDT_ADDR_T_NONE)
55 return -EINVAL;
Masahiro Yamada26f820f2015-01-13 12:44:36 +090056
Masahiro Yamada4e3d8402016-07-19 21:56:13 +090057 priv->regs = devm_ioremap(dev, addr, SZ_64);
Masahiro Yamada26f820f2015-01-13 12:44:36 +090058 if (!priv->regs)
59 return -ENOMEM;
60
61 priv->input_clk = IOBUS_FREQ;
62
Masahiro Yamada804cf1c2017-10-13 19:21:57 +090063 priv->dev = dev;
64
Masahiro Yamada26f820f2015-01-13 12:44:36 +090065 /* deassert reset */
66 writel(0x3, &priv->regs->brst);
67
68 return 0;
69}
70
Masahiro Yamada804cf1c2017-10-13 19:21:57 +090071static int send_and_recv_byte(struct uniphier_i2c_priv *priv, u32 dtrm)
Masahiro Yamada26f820f2015-01-13 12:44:36 +090072{
Masahiro Yamada804cf1c2017-10-13 19:21:57 +090073 writel(dtrm, &priv->regs->dtrm);
Masahiro Yamada26f820f2015-01-13 12:44:36 +090074
75 /*
76 * This controller only provides interruption to inform the completion
77 * of each byte transfer. (No status register to poll it.)
78 * Unfortunately, U-Boot does not have a good support of interrupt.
79 * Wait for a while.
80 */
Masahiro Yamada804cf1c2017-10-13 19:21:57 +090081 udelay(priv->wait_us);
Masahiro Yamada26f820f2015-01-13 12:44:36 +090082
Masahiro Yamada804cf1c2017-10-13 19:21:57 +090083 return readl(&priv->regs->drec);
Masahiro Yamada26f820f2015-01-13 12:44:36 +090084}
85
Masahiro Yamada804cf1c2017-10-13 19:21:57 +090086static int send_byte(struct uniphier_i2c_priv *priv, u32 dtrm, bool *stop)
Masahiro Yamada26f820f2015-01-13 12:44:36 +090087{
88 int ret = 0;
89 u32 drec;
90
Masahiro Yamada804cf1c2017-10-13 19:21:57 +090091 drec = send_and_recv_byte(priv, dtrm);
Masahiro Yamada26f820f2015-01-13 12:44:36 +090092
93 if (drec & I2C_DREC_LAB) {
Masahiro Yamada804cf1c2017-10-13 19:21:57 +090094 dev_dbg(priv->dev, "uniphier_i2c: bus arbitration failed\n");
Masahiro Yamada26f820f2015-01-13 12:44:36 +090095 *stop = false;
96 ret = -EREMOTEIO;
97 }
98 if (drec & I2C_DREC_LRB) {
Masahiro Yamada804cf1c2017-10-13 19:21:57 +090099 dev_dbg(priv->dev, "uniphier_i2c: slave did not return ACK\n");
Masahiro Yamada26f820f2015-01-13 12:44:36 +0900100 ret = -EREMOTEIO;
101 }
102 return ret;
103}
104
Masahiro Yamada804cf1c2017-10-13 19:21:57 +0900105static int uniphier_i2c_transmit(struct uniphier_i2c_priv *priv, uint addr,
Masahiro Yamada26f820f2015-01-13 12:44:36 +0900106 uint len, const u8 *buf, bool *stop)
107{
108 int ret;
109
Masahiro Yamada804cf1c2017-10-13 19:21:57 +0900110 dev_dbg(priv->dev, "%s: addr = %x, len = %d\n", __func__, addr, len);
Masahiro Yamada26f820f2015-01-13 12:44:36 +0900111
Masahiro Yamada804cf1c2017-10-13 19:21:57 +0900112 ret = send_byte(priv, I2C_DTRM_STA | I2C_DTRM_NACK | addr << 1, stop);
Masahiro Yamada26f820f2015-01-13 12:44:36 +0900113 if (ret < 0)
114 goto fail;
115
116 while (len--) {
Masahiro Yamada804cf1c2017-10-13 19:21:57 +0900117 ret = send_byte(priv, I2C_DTRM_NACK | *buf++, stop);
Masahiro Yamada26f820f2015-01-13 12:44:36 +0900118 if (ret < 0)
119 goto fail;
120 }
121
122fail:
123 if (*stop)
Masahiro Yamada804cf1c2017-10-13 19:21:57 +0900124 writel(I2C_DTRM_STO | I2C_DTRM_NACK, &priv->regs->dtrm);
Masahiro Yamada26f820f2015-01-13 12:44:36 +0900125
126 return ret;
127}
128
Masahiro Yamada804cf1c2017-10-13 19:21:57 +0900129static int uniphier_i2c_receive(struct uniphier_i2c_priv *priv, uint addr,
Masahiro Yamada26f820f2015-01-13 12:44:36 +0900130 uint len, u8 *buf, bool *stop)
131{
132 int ret;
133
Masahiro Yamada804cf1c2017-10-13 19:21:57 +0900134 dev_dbg(priv->dev, "%s: addr = %x, len = %d\n", __func__, addr, len);
Masahiro Yamada26f820f2015-01-13 12:44:36 +0900135
Masahiro Yamada804cf1c2017-10-13 19:21:57 +0900136 ret = send_byte(priv, I2C_DTRM_STA | I2C_DTRM_NACK |
Masahiro Yamada26f820f2015-01-13 12:44:36 +0900137 I2C_DTRM_RD | addr << 1, stop);
138 if (ret < 0)
139 goto fail;
140
141 while (len--)
Masahiro Yamada804cf1c2017-10-13 19:21:57 +0900142 *buf++ = send_and_recv_byte(priv, len ? 0 : I2C_DTRM_NACK);
Masahiro Yamada26f820f2015-01-13 12:44:36 +0900143
144fail:
145 if (*stop)
Masahiro Yamada804cf1c2017-10-13 19:21:57 +0900146 writel(I2C_DTRM_STO | I2C_DTRM_NACK, &priv->regs->dtrm);
Masahiro Yamada26f820f2015-01-13 12:44:36 +0900147
148 return ret;
149}
150
151static int uniphier_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
152 int nmsgs)
153{
154 int ret = 0;
Masahiro Yamada804cf1c2017-10-13 19:21:57 +0900155 struct uniphier_i2c_priv *priv = dev_get_priv(bus);
Masahiro Yamada26f820f2015-01-13 12:44:36 +0900156 bool stop;
157
158 for (; nmsgs > 0; nmsgs--, msg++) {
159 /* If next message is read, skip the stop condition */
160 stop = nmsgs > 1 && msg[1].flags & I2C_M_RD ? false : true;
161
162 if (msg->flags & I2C_M_RD)
Masahiro Yamada804cf1c2017-10-13 19:21:57 +0900163 ret = uniphier_i2c_receive(priv, msg->addr, msg->len,
Masahiro Yamada26f820f2015-01-13 12:44:36 +0900164 msg->buf, &stop);
165 else
Masahiro Yamada804cf1c2017-10-13 19:21:57 +0900166 ret = uniphier_i2c_transmit(priv, msg->addr, msg->len,
Masahiro Yamada26f820f2015-01-13 12:44:36 +0900167 msg->buf, &stop);
168
169 if (ret < 0)
170 break;
171 }
172
173 return ret;
174}
175
176static int uniphier_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
177{
Masahiro Yamada804cf1c2017-10-13 19:21:57 +0900178 struct uniphier_i2c_priv *priv = dev_get_priv(bus);
Masahiro Yamada26f820f2015-01-13 12:44:36 +0900179
180 /* max supported frequency is 400 kHz */
Simon Glassf3d46152020-01-23 11:48:22 -0700181 if (speed > I2C_SPEED_FAST_RATE)
Masahiro Yamada26f820f2015-01-13 12:44:36 +0900182 return -EINVAL;
183
184 /* bus reset: make sure the bus is idle when change the frequency */
185 writel(0x1, &priv->regs->brst);
186
187 writel((priv->input_clk / speed / 2 << 16) | (priv->input_clk / speed),
188 &priv->regs->clk);
189
190 writel(0x3, &priv->regs->brst);
191
192 /*
193 * Theoretically, each byte can be transferred in
194 * 1000000 * 9 / speed usec. For safety, wait more than double.
195 */
196 priv->wait_us = 20000000 / speed;
197
198 return 0;
199}
200
201
202static const struct dm_i2c_ops uniphier_i2c_ops = {
203 .xfer = uniphier_i2c_xfer,
204 .set_bus_speed = uniphier_i2c_set_bus_speed,
205};
206
207static const struct udevice_id uniphier_i2c_of_match[] = {
Masahiro Yamada6462cde2015-03-11 15:54:46 +0900208 { .compatible = "socionext,uniphier-i2c" },
209 { /* sentinel */ }
Masahiro Yamada26f820f2015-01-13 12:44:36 +0900210};
211
212U_BOOT_DRIVER(uniphier_i2c) = {
213 .name = "uniphier-i2c",
214 .id = UCLASS_I2C,
215 .of_match = uniphier_i2c_of_match,
216 .probe = uniphier_i2c_probe,
Masahiro Yamada804cf1c2017-10-13 19:21:57 +0900217 .priv_auto_alloc_size = sizeof(struct uniphier_i2c_priv),
Masahiro Yamada26f820f2015-01-13 12:44:36 +0900218 .ops = &uniphier_i2c_ops,
219};