blob: e3af073094b21da8a7ef12c40aef49c58a6c06a7 [file] [log] [blame]
wdenk1cb8e982003-03-06 21:55:29 +00001/*
2 * Memory Setup stuff - taken from blob memsetup.S
3 *
4 * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
5 * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
6 *
7 * Modified for the Samsung SMDK2410 by
8 * (C) Copyright 2002
9 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
10 *
11 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 */
29
30
wdenk1cb8e982003-03-06 21:55:29 +000031#include <config.h>
32#include <version.h>
33
34
35/* some parameters for the board */
36
wdenk531716e2003-09-13 19:01:12 +000037#define BWSCON 0x48000000
38#define PLD_BASE 0x2C000000
39#define SDRAM_REG 0x2C000106
wdenk1cb8e982003-03-06 21:55:29 +000040
41/* BWSCON */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020042#define DW8 (0x0)
43#define DW16 (0x1)
44#define DW32 (0x2)
45#define WAIT (0x1<<2)
46#define UBLB (0x1<<3)
wdenk1cb8e982003-03-06 21:55:29 +000047
wdenk531716e2003-09-13 19:01:12 +000048/* BANKSIZE */
49#define BURST_EN (0x1<<7)
50
Wolfgang Denk53677ef2008-05-20 16:00:29 +020051#define B1_BWSCON (DW16)
52#define B2_BWSCON (DW32)
53#define B3_BWSCON (DW32)
54#define B4_BWSCON (DW16 + WAIT + UBLB)
55#define B5_BWSCON (DW8 + UBLB)
56#define B6_BWSCON (DW32)
57#define B7_BWSCON (DW32)
wdenk1cb8e982003-03-06 21:55:29 +000058
59/* BANK0CON */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020060#define B0_Tacs 0x0 /* 0clk */
61#define B0_Tcos 0x1 /* 1clk */
wdenk48b42612003-06-19 23:01:32 +000062/*#define B0_Tcos 0x0 0clk */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020063#define B0_Tacc 0x7 /* 14clk */
wdenk48b42612003-06-19 23:01:32 +000064/*#define B0_Tacc 0x5 8clk */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020065#define B0_Tcoh 0x0 /* 0clk */
66#define B0_Tah 0x0 /* 0clk */
67#define B0_Tacp 0x0 /* page mode is not used */
68#define B0_PMC 0x0 /* page mode disabled */
wdenk1cb8e982003-03-06 21:55:29 +000069
70/* BANK1CON */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020071#define B1_Tacs 0x0 /* 0clk */
72#define B1_Tcos 0x1 /* 1clk */
wdenk48b42612003-06-19 23:01:32 +000073/*#define B1_Tcos 0x0 0clk */
74#define B1_Tacc 0x7 /* 14clk */
75/*#define B1_Tacc 0x5 8clk */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020076#define B1_Tcoh 0x0 /* 0clk */
77#define B1_Tah 0x0 /* 0clk */
78#define B1_Tacp 0x0 /* page mode is not used */
79#define B1_PMC 0x0 /* page mode disabled */
wdenk1cb8e982003-03-06 21:55:29 +000080
Wolfgang Denk53677ef2008-05-20 16:00:29 +020081#define B2_Tacs 0x3 /* 4clk */
82#define B2_Tcos 0x3 /* 4clk */
83#define B2_Tacc 0x7 /* 14clk */
84#define B2_Tcoh 0x3 /* 4clk */
85#define B2_Tah 0x3 /* 4clk */
86#define B2_Tacp 0x0 /* page mode is not used */
87#define B2_PMC 0x0 /* page mode disabled */
wdenk1cb8e982003-03-06 21:55:29 +000088
Wolfgang Denk53677ef2008-05-20 16:00:29 +020089#define B3_Tacs 0x3 /* 4clk */
90#define B3_Tcos 0x3 /* 4clk */
91#define B3_Tacc 0x7 /* 14clk */
92#define B3_Tcoh 0x3 /* 4clk */
93#define B3_Tah 0x3 /* 4clk */
94#define B3_Tacp 0x0 /* page mode is not used */
95#define B3_PMC 0x0 /* page mode disabled */
wdenk1cb8e982003-03-06 21:55:29 +000096
Wolfgang Denk53677ef2008-05-20 16:00:29 +020097#define B4_Tacs 0x3 /* 4clk */
98#define B4_Tcos 0x1 /* 1clk */
99#define B4_Tacc 0x7 /* 14clk */
100#define B4_Tcoh 0x1 /* 1clk */
101#define B4_Tah 0x0 /* 0clk */
102#define B4_Tacp 0x0 /* page mode is not used */
103#define B4_PMC 0x0 /* page mode disabled */
wdenk1cb8e982003-03-06 21:55:29 +0000104
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200105#define B5_Tacs 0x0 /* 0clk */
106#define B5_Tcos 0x3 /* 4clk */
107#define B5_Tacc 0x5 /* 8clk */
108#define B5_Tcoh 0x2 /* 2clk */
109#define B5_Tah 0x1 /* 1clk */
110#define B5_Tacp 0x0 /* page mode is not used */
111#define B5_PMC 0x0 /* page mode disabled */
wdenk1cb8e982003-03-06 21:55:29 +0000112
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200113#define B6_MT 0x3 /* SDRAM */
114#define B6_Trcd 0x1 /* 3clk */
115#define B6_SCAN 0x2 /* 10bit */
wdenk1cb8e982003-03-06 21:55:29 +0000116
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200117#define B7_MT 0x3 /* SDRAM */
118#define B7_Trcd 0x1 /* 3clk */
119#define B7_SCAN 0x2 /* 10bit */
wdenk1cb8e982003-03-06 21:55:29 +0000120
121/* REFRESH parameter */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200122#define REFEN 0x1 /* Refresh enable */
123#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
124#define Trp 0x0 /* 2clk */
125#define Trc 0x3 /* 7clk */
126#define Tchr 0x2 /* 3clk */
127#define REFCNT 1113 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */
wdenk1cb8e982003-03-06 21:55:29 +0000128/**************************************/
129
130_TEXT_BASE:
131 .word TEXT_BASE
132
wdenk400558b2005-04-02 23:52:25 +0000133.globl lowlevel_init
134lowlevel_init:
wdenk1cb8e982003-03-06 21:55:29 +0000135 /* memory control configuration */
136 /* make r0 relative the current location so that it */
137 /* reads SMRDATA out of FLASH rather than memory ! */
wdenk531716e2003-09-13 19:01:12 +0000138 ldr r0, =CSDATA
wdenk1cb8e982003-03-06 21:55:29 +0000139 ldr r1, _TEXT_BASE
140 sub r0, r0, r1
141 ldr r1, =BWSCON /* Bus Width Status Controller */
wdenk531716e2003-09-13 19:01:12 +0000142 add r2, r0, #CSDATA_END-CSDATA
wdenk1cb8e982003-03-06 21:55:29 +00001430:
144 ldr r3, [r0], #4
145 str r3, [r1], #4
146 cmp r2, r0
147 bne 0b
148
wdenk531716e2003-09-13 19:01:12 +0000149 /* PLD access is now possible */
150 /* r0 == SDRAMDATA */
151 /* r1 == SDRAM controller regs */
152 ldr r2, =PLD_BASE
153 ldrb r3, [r2, #SDRAM_REG-PLD_BASE]
154 mov r4, #SDRAMDATA1_END-SDRAMDATA
155 /* calculate start and end point */
wdenk42d1f032003-10-15 23:53:47 +0000156 mla r0, r3, r4, r0
wdenk531716e2003-09-13 19:01:12 +0000157 add r2, r0, r4
1580:
159 ldr r3, [r0], #4
160 str r3, [r1], #4
161 cmp r2, r0
162 bne 0b
wdenk42d1f032003-10-15 23:53:47 +0000163
wdenk1cb8e982003-03-06 21:55:29 +0000164 /* everything is fine now */
165 mov pc, lr
166
167 .ltorg
168/* the literal pools origin */
169
wdenk531716e2003-09-13 19:01:12 +0000170CSDATA:
wdenk1cb8e982003-03-06 21:55:29 +0000171 .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
172 .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
173 .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
174 .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))
175 .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
176 .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
177 .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
wdenk531716e2003-09-13 19:01:12 +0000178CSDATA_END:
179
180SDRAMDATA:
181/* 4Mx8x4 */
wdenk1cb8e982003-03-06 21:55:29 +0000182 .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
183 .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
184 .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
wdenk531716e2003-09-13 19:01:12 +0000185 .word 0x32 + BURST_EN
186 .word 0x30
187 .word 0x30
188SDRAMDATA1_END:
189
190/* 8Mx8x4 (not implemented yet) */
191 .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
192 .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
193 .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
194 .word 0x32 + BURST_EN
195 .word 0x30
196 .word 0x30
wdenk42d1f032003-10-15 23:53:47 +0000197
wdenk531716e2003-09-13 19:01:12 +0000198/* 2Mx8x4 (not implemented yet) */
199 .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
200 .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
201 .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
202 .word 0x32 + BURST_EN
203 .word 0x30
204 .word 0x30
wdenk42d1f032003-10-15 23:53:47 +0000205
wdenk531716e2003-09-13 19:01:12 +0000206/* 4Mx8x2 (not implemented yet) */
207 .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
208 .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
209 .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
210 .word 0x32 + BURST_EN
wdenk1cb8e982003-03-06 21:55:29 +0000211 .word 0x30
212 .word 0x30