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wdenkbf9e3b32004-02-12 00:47:09 +00001/*
2 * fec.h -- Fast Ethernet Controller definitions
3 *
4 * Some definitions copied from commproc.h for MPC8xx:
5 * MPC8xx Communication Processor Module.
6 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
7 *
TsiChung Liew8e585f02007-06-18 13:50:13 -05008 * Add FEC Structure and definitions
9 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
10 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
11 *
wdenkbf9e3b32004-02-12 00:47:09 +000012 * See file CREDITS for list of people who contributed to this
13 * project.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * MA 02111-1307 USA
29 */
30
31#ifndef fec_h
32#define fec_h
33
34/* Buffer descriptors used FEC.
35*/
36typedef struct cpm_buf_desc {
TsiChung Liew8e585f02007-06-18 13:50:13 -050037 ushort cbd_sc; /* Status and Control */
38 ushort cbd_datlen; /* Data length in buffer */
39 uint cbd_bufaddr; /* Buffer address in host memory */
wdenkbf9e3b32004-02-12 00:47:09 +000040} cbd_t;
41
Mike Williams16263082011-07-22 04:01:30 +000042#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */
TsiChungLiew4621fc32008-01-15 13:39:44 -060043#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
44#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
45#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
46#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */
47#define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */
48#define BD_SC_CM ((ushort)0x0200) /* Continous mode */
49#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
50#define BD_SC_P ((ushort)0x0100) /* xmt preamble */
51#define BD_SC_BR ((ushort)0x0020) /* Break received */
52#define BD_SC_FR ((ushort)0x0010) /* Framing error */
53#define BD_SC_PR ((ushort)0x0008) /* Parity error */
54#define BD_SC_OV ((ushort)0x0002) /* Overrun */
55#define BD_SC_CD ((ushort)0x0001) /* Carrier Detect lost */
wdenkbf9e3b32004-02-12 00:47:09 +000056
57/* Buffer descriptor control/status used by Ethernet receive.
58*/
59#define BD_ENET_RX_EMPTY ((ushort)0x8000)
TsiChung Liew8e585f02007-06-18 13:50:13 -050060#define BD_ENET_RX_RO1 ((ushort)0x4000)
wdenkbf9e3b32004-02-12 00:47:09 +000061#define BD_ENET_RX_WRAP ((ushort)0x2000)
62#define BD_ENET_RX_INTR ((ushort)0x1000)
TsiChung Liew8e585f02007-06-18 13:50:13 -050063#define BD_ENET_RX_RO2 BD_ENET_RX_INTR
wdenkbf9e3b32004-02-12 00:47:09 +000064#define BD_ENET_RX_LAST ((ushort)0x0800)
65#define BD_ENET_RX_FIRST ((ushort)0x0400)
66#define BD_ENET_RX_MISS ((ushort)0x0100)
TsiChung Liew8e585f02007-06-18 13:50:13 -050067#define BD_ENET_RX_BC ((ushort)0x0080)
68#define BD_ENET_RX_MC ((ushort)0x0040)
wdenkbf9e3b32004-02-12 00:47:09 +000069#define BD_ENET_RX_LG ((ushort)0x0020)
70#define BD_ENET_RX_NO ((ushort)0x0010)
71#define BD_ENET_RX_SH ((ushort)0x0008)
72#define BD_ENET_RX_CR ((ushort)0x0004)
73#define BD_ENET_RX_OV ((ushort)0x0002)
74#define BD_ENET_RX_CL ((ushort)0x0001)
TsiChung Liew8e585f02007-06-18 13:50:13 -050075#define BD_ENET_RX_TR BD_ENET_RX_CL
wdenkbf9e3b32004-02-12 00:47:09 +000076#define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */
77
78/* Buffer descriptor control/status used by Ethernet transmit.
79*/
80#define BD_ENET_TX_READY ((ushort)0x8000)
81#define BD_ENET_TX_PAD ((ushort)0x4000)
TsiChung Liew8e585f02007-06-18 13:50:13 -050082#define BD_ENET_TX_TO1 BD_ENET_TX_PAD
wdenkbf9e3b32004-02-12 00:47:09 +000083#define BD_ENET_TX_WRAP ((ushort)0x2000)
84#define BD_ENET_TX_INTR ((ushort)0x1000)
TsiChung Liew8e585f02007-06-18 13:50:13 -050085#define BD_ENET_TX_TO2 BD_ENET_TX_INTR_
wdenkbf9e3b32004-02-12 00:47:09 +000086#define BD_ENET_TX_LAST ((ushort)0x0800)
87#define BD_ENET_TX_TC ((ushort)0x0400)
88#define BD_ENET_TX_DEF ((ushort)0x0200)
TsiChung Liew8e585f02007-06-18 13:50:13 -050089#define BD_ENET_TX_ABC BD_ENET_TX_DEF
wdenkbf9e3b32004-02-12 00:47:09 +000090#define BD_ENET_TX_HB ((ushort)0x0100)
91#define BD_ENET_TX_LC ((ushort)0x0080)
92#define BD_ENET_TX_RL ((ushort)0x0040)
93#define BD_ENET_TX_RCMASK ((ushort)0x003c)
94#define BD_ENET_TX_UN ((ushort)0x0002)
95#define BD_ENET_TX_CSL ((ushort)0x0001)
96#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
97
TsiChung Liew8e585f02007-06-18 13:50:13 -050098/*********************************************************************
TsiChung Liew8e585f02007-06-18 13:50:13 -050099* Fast Ethernet Controller (FEC)
TsiChung Liew8e585f02007-06-18 13:50:13 -0500100*********************************************************************/
101/* FEC private information */
102struct fec_info_s {
103 int index;
104 u32 iobase;
105 u32 pinmux;
106 u32 miibase;
107 int phy_addr;
108 int dup_spd;
109 char *phy_name;
110 int phyname_init;
111 cbd_t *rxbd; /* Rx BD */
112 cbd_t *txbd; /* Tx BD */
113 uint rxIdx;
114 uint txIdx;
115 char *txbuf;
116 int initialized;
TsiChungLiew4621fc32008-01-15 13:39:44 -0600117 struct fec_info_s *next;
TsiChung Liew8e585f02007-06-18 13:50:13 -0500118};
119
TsiChungLiew4621fc32008-01-15 13:39:44 -0600120#ifdef CONFIG_MCFFEC
TsiChung Liew8e585f02007-06-18 13:50:13 -0500121/* Register read/write struct */
122typedef struct fec {
TsiChungLiew56115662007-08-15 19:38:15 -0500123#ifdef CONFIG_M5272
124 u32 ecr; /* 0x00 */
125 u32 eir; /* 0x04 */
126 u32 eimr; /* 0x08 */
127 u32 ivsr; /* 0x0C */
128 u32 rdar; /* 0x10 */
129 u32 tdar; /* 0x14 */
130 u8 resv1[0x28]; /* 0x18 */
131 u32 mmfr; /* 0x40 */
132 u32 mscr; /* 0x44 */
133 u8 resv2[0x44]; /* 0x48 */
134 u32 frbr; /* 0x8C */
135 u32 frsr; /* 0x90 */
136 u8 resv3[0x10]; /* 0x94 */
137 u32 tfwr; /* 0xA4 */
138 u32 res4; /* 0xA8 */
139 u32 tfsr; /* 0xAC */
140 u8 resv4[0x50]; /* 0xB0 */
141 u32 opd; /* 0x100 - dummy */
142 u32 rcr; /* 0x104 */
143 u32 mibc; /* 0x108 */
144 u8 resv5[0x38]; /* 0x10C */
145 u32 tcr; /* 0x144 */
146 u8 resv6[0x270]; /* 0x148 */
147 u32 iaur; /* 0x3B8 - dummy */
148 u32 ialr; /* 0x3BC - dummy */
149 u32 palr; /* 0x3C0 */
150 u32 paur; /* 0x3C4 */
151 u32 gaur; /* 0x3C8 */
152 u32 galr; /* 0x3CC */
153 u32 erdsr; /* 0x3D0 */
154 u32 etdsr; /* 0x3D4 */
155 u32 emrbr; /* 0x3D8 */
156 u8 resv12[0x74]; /* 0x18C */
157#else
TsiChung Liew8e585f02007-06-18 13:50:13 -0500158 u8 resv0[0x4];
159 u32 eir;
160 u32 eimr;
161 u8 resv1[0x4];
162 u32 rdar;
163 u32 tdar;
164 u8 resv2[0xC];
165 u32 ecr;
166 u8 resv3[0x18];
167 u32 mmfr;
168 u32 mscr;
169 u8 resv4[0x1C];
170 u32 mibc;
171 u8 resv5[0x1C];
172 u32 rcr;
173 u8 resv6[0x3C];
174 u32 tcr;
175 u8 resv7[0x1C];
176 u32 palr;
177 u32 paur;
178 u32 opd;
179 u8 resv8[0x28];
180 u32 iaur;
181 u32 ialr;
182 u32 gaur;
183 u32 galr;
184 u8 resv9[0x1C];
185 u32 tfwr;
186 u8 resv10[0x4];
187 u32 frbr;
188 u32 frsr;
189 u8 resv11[0x2C];
190 u32 erdsr;
191 u32 etdsr;
192 u32 emrbr;
193 u8 resv12[0x74];
TsiChungLiew56115662007-08-15 19:38:15 -0500194#endif
TsiChung Liew8e585f02007-06-18 13:50:13 -0500195
196 u32 rmon_t_drop;
197 u32 rmon_t_packets;
198 u32 rmon_t_bc_pkt;
199 u32 rmon_t_mc_pkt;
200 u32 rmon_t_crc_align;
201 u32 rmon_t_undersize;
202 u32 rmon_t_oversize;
203 u32 rmon_t_frag;
204 u32 rmon_t_jab;
205 u32 rmon_t_col;
206 u32 rmon_t_p64;
207 u32 rmon_t_p65to127;
208 u32 rmon_t_p128to255;
209 u32 rmon_t_p256to511;
210 u32 rmon_t_p512to1023;
211 u32 rmon_t_p1024to2047;
212 u32 rmon_t_p_gte2048;
213 u32 rmon_t_octets;
214
215 u32 ieee_t_drop;
216 u32 ieee_t_frame_ok;
217 u32 ieee_t_1col;
218 u32 ieee_t_mcol;
219 u32 ieee_t_def;
220 u32 ieee_t_lcol;
221 u32 ieee_t_excol;
222 u32 ieee_t_macerr;
223 u32 ieee_t_cserr;
224 u32 ieee_t_sqe;
225 u32 ieee_t_fdxfc;
226 u32 ieee_t_octets_ok;
227 u8 resv13[0x8];
228
229 u32 rmon_r_drop;
230 u32 rmon_r_packets;
231 u32 rmon_r_bc_pkt;
232 u32 rmon_r_mc_pkt;
233 u32 rmon_r_crc_align;
234 u32 rmon_r_undersize;
235 u32 rmon_r_oversize;
236 u32 rmon_r_frag;
237 u32 rmon_r_jab;
238 u32 rmon_r_resvd_0;
239 u32 rmon_r_p64;
240 u32 rmon_r_p65to127;
241 u32 rmon_r_p128to255;
242 u32 rmon_r_p256to511;
243 u32 rmon_r_p512to1023;
244 u32 rmon_r_p1024to2047;
245 u32 rmon_r_p_gte2048;
246 u32 rmon_r_octets;
247
248 u32 ieee_r_drop;
249 u32 ieee_r_frame_ok;
250 u32 ieee_r_crc;
251 u32 ieee_r_align;
252 u32 ieee_r_macerr;
253 u32 ieee_r_fdxfc;
254 u32 ieee_r_octets_ok;
255} fec_t;
TsiChungLiew4621fc32008-01-15 13:39:44 -0600256#endif /* CONFIG_MCFFEC */
TsiChung Liew8e585f02007-06-18 13:50:13 -0500257
258/*********************************************************************
259* Fast Ethernet Controller (FEC)
260*********************************************************************/
261/* Bit definitions and macros for FEC_EIR */
TsiChungLiew4621fc32008-01-15 13:39:44 -0600262#define FEC_EIR_CLEAR_ALL (0xFFF80000)
263#define FEC_EIR_HBERR (0x80000000)
264#define FEC_EIR_BABR (0x40000000)
265#define FEC_EIR_BABT (0x20000000)
266#define FEC_EIR_GRA (0x10000000)
267#define FEC_EIR_TXF (0x08000000)
268#define FEC_EIR_TXB (0x04000000)
269#define FEC_EIR_RXF (0x02000000)
270#define FEC_EIR_RXB (0x01000000)
271#define FEC_EIR_MII (0x00800000)
272#define FEC_EIR_EBERR (0x00400000)
273#define FEC_EIR_LC (0x00200000)
274#define FEC_EIR_RL (0x00100000)
275#define FEC_EIR_UN (0x00080000)
TsiChung Liew8e585f02007-06-18 13:50:13 -0500276
277/* Bit definitions and macros for FEC_RDAR */
TsiChungLiew4621fc32008-01-15 13:39:44 -0600278#define FEC_RDAR_R_DES_ACTIVE (0x01000000)
TsiChung Liew8e585f02007-06-18 13:50:13 -0500279
280/* Bit definitions and macros for FEC_TDAR */
TsiChungLiew4621fc32008-01-15 13:39:44 -0600281#define FEC_TDAR_X_DES_ACTIVE (0x01000000)
TsiChung Liew8e585f02007-06-18 13:50:13 -0500282
283/* Bit definitions and macros for FEC_ECR */
TsiChungLiew4621fc32008-01-15 13:39:44 -0600284#define FEC_ECR_ETHER_EN (0x00000002)
285#define FEC_ECR_RESET (0x00000001)
TsiChung Liew8e585f02007-06-18 13:50:13 -0500286
287/* Bit definitions and macros for FEC_MMFR */
TsiChungLiew4621fc32008-01-15 13:39:44 -0600288#define FEC_MMFR_DATA(x) (((x)&0xFFFF))
289#define FEC_MMFR_ST(x) (((x)&0x03)<<30)
290#define FEC_MMFR_ST_01 (0x40000000)
291#define FEC_MMFR_OP_RD (0x20000000)
292#define FEC_MMFR_OP_WR (0x10000000)
293#define FEC_MMFR_PA(x) (((x)&0x1F)<<23)
294#define FEC_MMFR_RA(x) (((x)&0x1F)<<18)
295#define FEC_MMFR_TA(x) (((x)&0x03)<<16)
296#define FEC_MMFR_TA_10 (0x00020000)
TsiChung Liew8e585f02007-06-18 13:50:13 -0500297
298/* Bit definitions and macros for FEC_MSCR */
TsiChungLiew4621fc32008-01-15 13:39:44 -0600299#define FEC_MSCR_DIS_PREAMBLE (0x00000080)
300#define FEC_MSCR_MII_SPEED(x) (((x)&0x3F)<<1)
TsiChung Liew8e585f02007-06-18 13:50:13 -0500301
302/* Bit definitions and macros for FEC_MIBC */
TsiChungLiew4621fc32008-01-15 13:39:44 -0600303#define FEC_MIBC_MIB_DISABLE (0x80000000)
304#define FEC_MIBC_MIB_IDLE (0x40000000)
TsiChung Liew8e585f02007-06-18 13:50:13 -0500305
306/* Bit definitions and macros for FEC_RCR */
TsiChungLiew4621fc32008-01-15 13:39:44 -0600307#define FEC_RCR_MAX_FL(x) (((x)&0x7FF)<<16)
308#define FEC_RCR_FCE (0x00000020)
309#define FEC_RCR_BC_REJ (0x00000010)
310#define FEC_RCR_PROM (0x00000008)
311#define FEC_RCR_MII_MODE (0x00000004)
312#define FEC_RCR_DRT (0x00000002)
313#define FEC_RCR_LOOP (0x00000001)
TsiChung Liew8e585f02007-06-18 13:50:13 -0500314
315/* Bit definitions and macros for FEC_TCR */
TsiChungLiew4621fc32008-01-15 13:39:44 -0600316#define FEC_TCR_RFC_PAUSE (0x00000010)
317#define FEC_TCR_TFC_PAUSE (0x00000008)
318#define FEC_TCR_FDEN (0x00000004)
319#define FEC_TCR_HBC (0x00000002)
320#define FEC_TCR_GTS (0x00000001)
TsiChung Liew8e585f02007-06-18 13:50:13 -0500321
322/* Bit definitions and macros for FEC_PAUR */
TsiChungLiew4621fc32008-01-15 13:39:44 -0600323#define FEC_PAUR_PADDR2(x) (((x)&0xFFFF)<<16)
324#define FEC_PAUR_TYPE(x) ((x)&0xFFFF)
TsiChung Liew8e585f02007-06-18 13:50:13 -0500325
326/* Bit definitions and macros for FEC_OPD */
TsiChungLiew4621fc32008-01-15 13:39:44 -0600327#define FEC_OPD_PAUSE_DUR(x) (((x)&0x0000FFFF)<<0)
328#define FEC_OPD_OPCODE(x) (((x)&0x0000FFFF)<<16)
TsiChung Liew8e585f02007-06-18 13:50:13 -0500329
330/* Bit definitions and macros for FEC_TFWR */
TsiChungLiew4621fc32008-01-15 13:39:44 -0600331#define FEC_TFWR_X_WMRK(x) ((x)&0x03)
332#define FEC_TFWR_X_WMRK_64 (0x01)
333#define FEC_TFWR_X_WMRK_128 (0x02)
334#define FEC_TFWR_X_WMRK_192 (0x03)
TsiChung Liew8e585f02007-06-18 13:50:13 -0500335
336/* Bit definitions and macros for FEC_FRBR */
TsiChungLiew4621fc32008-01-15 13:39:44 -0600337#define FEC_FRBR_R_BOUND(x) (((x)&0xFF)<<2)
TsiChung Liew8e585f02007-06-18 13:50:13 -0500338
339/* Bit definitions and macros for FEC_FRSR */
TsiChungLiew4621fc32008-01-15 13:39:44 -0600340#define FEC_FRSR_R_FSTART(x) (((x)&0xFF)<<2)
TsiChung Liew8e585f02007-06-18 13:50:13 -0500341
342/* Bit definitions and macros for FEC_ERDSR */
TsiChungLiew56115662007-08-15 19:38:15 -0500343#define FEC_ERDSR_R_DES_START(x) (((x)&0x3FFFFFFF)<<2)
TsiChung Liew8e585f02007-06-18 13:50:13 -0500344
345/* Bit definitions and macros for FEC_ETDSR */
TsiChungLiew56115662007-08-15 19:38:15 -0500346#define FEC_ETDSR_X_DES_START(x) (((x)&0x3FFFFFFF)<<2)
TsiChung Liew8e585f02007-06-18 13:50:13 -0500347
348/* Bit definitions and macros for FEC_EMRBR */
TsiChungLiew56115662007-08-15 19:38:15 -0500349#define FEC_EMRBR_R_BUF_SIZE(x) (((x)&0x7F)<<4)
TsiChung Liew8e585f02007-06-18 13:50:13 -0500350
TsiChungLiew4621fc32008-01-15 13:39:44 -0600351#define FEC_RESET_DELAY 100
352#define FEC_RX_TOUT 100
TsiChung Liew8e585f02007-06-18 13:50:13 -0500353
TsiChung Liewf3962d32008-10-21 13:47:54 +0000354int fecpin_setclear(struct eth_device *dev, int setclear);
355
356#ifdef CONFIG_SYS_DISCOVER_PHY
357void __mii_init(void);
358uint mii_send(uint mii_cmd);
359int mii_discover_phy(struct eth_device *dev);
Mike Frysinger5700bb62010-07-27 18:35:08 -0400360int mcffec_miiphy_read(const char *devname, unsigned char addr,
TsiChung Liewf3962d32008-10-21 13:47:54 +0000361 unsigned char reg, unsigned short *value);
Mike Frysinger5700bb62010-07-27 18:35:08 -0400362int mcffec_miiphy_write(const char *devname, unsigned char addr,
TsiChung Liewf3962d32008-10-21 13:47:54 +0000363 unsigned char reg, unsigned short value);
364#endif
365
TsiChung Liew8e585f02007-06-18 13:50:13 -0500366#endif /* fec_h */