blob: 229821887082c46e11806b114f0984ca48408635 [file] [log] [blame]
Scott Wood49ea3b62007-04-16 14:34:21 -05001/*
2 * Copyright (C) Freescale Semiconductor, Inc. 2007
3 *
4 * Author: Scott Wood <scottwood@freescale.com>,
5 * with some bits from older board-specific PCI initialization.
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#include <common.h>
27#include <pci.h>
Kim Phillips343d9102007-07-25 19:25:28 -050028
29#if defined(CONFIG_OF_LIBFDT)
30#include <libfdt.h>
31#include <libfdt_env.h>
32#elif defined(CONFIG_OF_FLAT_TREE)
Kim Phillips5c5d3242007-04-25 12:34:38 -050033#include <ft_build.h>
Kim Phillips343d9102007-07-25 19:25:28 -050034#endif
35
Scott Wood49ea3b62007-04-16 14:34:21 -050036#include <asm/mpc8349_pci.h>
37
38#ifdef CONFIG_83XX_GENERIC_PCI
39#define MAX_BUSES 2
40
41DECLARE_GLOBAL_DATA_PTR;
42
43static struct pci_controller pci_hose[MAX_BUSES];
44static int pci_num_buses;
45
46static void pci_init_bus(int bus, struct pci_region *reg)
47{
48 volatile immap_t *immr = (volatile immap_t *)CFG_IMMR;
49 volatile pot83xx_t *pot = immr->ios.pot;
50 volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[bus];
51 struct pci_controller *hose = &pci_hose[bus];
52 u32 dev;
53 u16 reg16;
54 int i;
55
56 if (bus == 1)
57 pot += 3;
58
59 /* Setup outbound translation windows */
60 for (i = 0; i < 3; i++, reg++, pot++) {
61 if (reg->size == 0)
62 break;
63
64 hose->regions[i] = *reg;
65 hose->region_count++;
66
67 pot->potar = reg->bus_start >> 12;
68 pot->pobar = reg->phys_start >> 12;
69 pot->pocmr = ~(reg->size - 1) >> 12;
70
71 if (reg->flags & PCI_REGION_IO)
72 pot->pocmr |= POCMR_IO;
73#ifdef CONFIG_83XX_PCI_STREAMING
74 else if (reg->flags & PCI_REGION_PREFETCH)
75 pot->pocmr |= POCMR_SE;
76#endif
77
78 if (bus == 1)
79 pot->pocmr |= POCMR_DST;
80
81 pot->pocmr |= POCMR_EN;
82 }
83
84 /* Point inbound translation at RAM */
85 pci_ctrl->pitar1 = 0;
86 pci_ctrl->pibar1 = 0;
87 pci_ctrl->piebar1 = 0;
88 pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
89 PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1);
90
91 i = hose->region_count++;
92 hose->regions[i].bus_start = 0;
93 hose->regions[i].phys_start = 0;
94 hose->regions[i].size = gd->ram_size;
95 hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_MEMORY;
96
97 hose->first_busno = 0;
98 hose->last_busno = 0xff;
99
100 pci_setup_indirect(hose, CFG_IMMR + 0x8300 + bus * 0x80,
101 CFG_IMMR + 0x8304 + bus * 0x80);
102
103 pci_register_hose(hose);
104
105 /*
106 * Write to Command register
107 */
108 reg16 = 0xff;
109 dev = PCI_BDF(hose->first_busno, 0, 0);
110 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &reg16);
111 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
112 pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
113
114 /*
115 * Clear non-reserved bits in status register.
116 */
117 pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
118 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
119 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
120
121#ifdef CONFIG_PCI_SCAN_SHOW
122 printf("PCI: Bus Dev VenId DevId Class Int\n");
123#endif
124 /*
125 * Hose scan.
126 */
127 hose->last_busno = pci_hose_scan(hose);
128}
129
130/*
131 * The caller must have already set OCCR, and the PCI_LAW BARs
132 * must have been set to cover all of the requested regions.
133 *
134 * If fewer than three regions are requested, then the region
135 * list is terminated with a region of size 0.
136 */
137void mpc83xx_pci_init(int num_buses, struct pci_region **reg, int warmboot)
138{
139 volatile immap_t *immr = (volatile immap_t *)CFG_IMMR;
140 int i;
141
142 if (num_buses > MAX_BUSES) {
143 printf("%d PCI buses requsted, %d supported\n",
144 num_buses, MAX_BUSES);
145
146 num_buses = MAX_BUSES;
147 }
148
149 pci_num_buses = num_buses;
150
151 /*
152 * Release PCI RST Output signal.
153 * Power on to RST high must be at least 100 ms as per PCI spec.
154 * On warm boots only 1 ms is required.
155 */
156 udelay(warmboot ? 1000 : 100000);
157
158 for (i = 0; i < num_buses; i++)
159 immr->pci_ctrl[i].gcr = 1;
160
161 /*
162 * RST high to first config access must be at least 2^25 cycles
163 * as per PCI spec. This could be cut in half if we know we're
164 * running at 66MHz. This could be insufficiently long if we're
165 * running the PCI bus at significantly less than 33MHz.
166 */
167 udelay(1020000);
168
169 for (i = 0; i < num_buses; i++)
170 pci_init_bus(i, reg[i]);
171}
172
Kim Phillips343d9102007-07-25 19:25:28 -0500173#if defined(CONFIG_OF_LIBFDT)
174void ft_pci_setup(void *blob, bd_t *bd)
175{
176 int nodeoffset;
177 int err;
178 int tmp[2];
179
180 if (pci_num_buses < 1)
181 return;
182
183 nodeoffset = fdt_find_node_by_path(blob, "/" OF_SOC "/pci@8500");
184 if (nodeoffset >= 0) {
185 tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
186 tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
187 err = fdt_setprop(blob, nodeoffset, "bus-range", tmp, sizeof(tmp));
188 }
189
190 if (pci_num_buses < 2)
191 return;
192
193 nodeoffset = fdt_find_node_by_path(blob, "/" OF_SOC "/pci@8600");
194 if (nodeoffset >= 0) {
195 tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
196 tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
197 err = fdt_setprop(blob, nodeoffset, "bus-range", tmp, sizeof(tmp));
198 }
199}
200#elif CONFIG_OF_FLAT_TREE
Scott Wood49ea3b62007-04-16 14:34:21 -0500201void ft_pci_setup(void *blob, bd_t *bd)
202{
203 u32 *p;
204 int len;
205
206 if (pci_num_buses < 1)
207 return;
208
209 p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len);
210 if (p) {
211 p[0] = pci_hose[0].first_busno;
212 p[1] = pci_hose[0].last_busno;
213 }
214
215 if (pci_num_buses < 2)
216 return;
217
218 p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8600/bus-range", &len);
219 if (p) {
220 p[0] = pci_hose[1].first_busno;
221 p[1] = pci_hose[1].last_busno;
222 }
223}
224#endif /* CONFIG_OF_FLAT_TREE */
225
226#endif /* CONFIG_83XX_GENERIC_PCI */