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Tom Rixe63e5902009-10-17 12:41:06 -05001/*
2 * (C) Copyright 2006-2009
3 * Texas Instruments Incorporated.
4 * Richard Woodruff <r-woodruff2@ti.com>
5 * Syed Mohammed Khasim <x0khasim@ti.com>
6 * Nishanth Menon <nm@ti.com>
7 *
8 * Configuration settings for the 3430 TI SDP3430 board.
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28
29#ifndef __CONFIG_H
30#define __CONFIG_H
31
32/* TODO: REMOVE THE FOLLOWING
33 * Retained the following till size.h is removed in u-boot
34 */
35#include <asm/sizes.h>
36/*
37 * High Level Configuration Options
38 */
Tom Rixe63e5902009-10-17 12:41:06 -050039#define CONFIG_OMAP 1 /* in a TI OMAP core */
40#define CONFIG_OMAP34XX 1 /* which is a 34XX */
Tom Rixe63e5902009-10-17 12:41:06 -050041#define CONFIG_OMAP3_3430SDP 1 /* working with SDP Rev2 */
42
Vaibhav Hiremathcae377b2010-06-07 15:20:34 -040043#define CONFIG_SDRC /* The chip has SDRC controller */
44
Tom Rixe63e5902009-10-17 12:41:06 -050045#include <asm/arch/cpu.h> /* get chip and board defs */
46#include <asm/arch/omap3.h>
47
48/*
49 * NOTE: these #defines presume standard SDP jumper settings.
50 * In particular:
51 * - 26 MHz clock (not 19.2 or 38.4 MHz)
52 * - Boot from 128MB NOR, not NAND or OneNAND
53 *
54 * At this writing, OMAP3 U-Boot support doesn't permit concurrent
55 * support for all the flash types the board supports.
56 */
57#define CONFIG_DISPLAY_CPUINFO 1
58#define CONFIG_DISPLAY_BOARDINFO 1
59
60/* Clock Defines */
61#define V_OSCK 26000000 /* Clock output from T2 */
62#define V_SCLK (V_OSCK >> 1)
63
64#undef CONFIG_USE_IRQ /* no support for IRQs */
65#define CONFIG_MISC_INIT_R
66
67#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
68#define CONFIG_SETUP_MEMORY_TAGS 1
69#define CONFIG_INITRD_TAG 1
70#define CONFIG_REVISION_TAG 1
71
Grant Likely2fa8ca92011-03-28 09:59:07 +000072#define CONFIG_OF_LIBFDT 1
73
Tom Rixe63e5902009-10-17 12:41:06 -050074/*
75 * Size of malloc() pool
76 * Total Size Environment - 256k
77 * Malloc - add 256k
78 */
79#define CONFIG_ENV_SIZE (256 << 10)
80#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (256 << 10))
Tom Rixe63e5902009-10-17 12:41:06 -050081
82/*--------------------------------------------------------------------------*/
83
84/*
85 * Hardware drivers
86 */
87
88/*
89 * TWL4030
90 */
91#define CONFIG_TWL4030_POWER 1
92
93/*
94 * serial port - NS16550 compatible
95 */
96#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
97
98#define CONFIG_SYS_NS16550
99#define CONFIG_SYS_NS16550_SERIAL
100#define CONFIG_SYS_NS16550_REG_SIZE (-4)
101#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
102
103/* Original SDP u-boot used UART1 and thus J8 (innermost); that can be
104 * swapped with UART2 via jumpering. Downsides of using J8: it doesn't
105 * support UART boot (that's only for UART3); it prevents sharing a Linux
106 * kernel (LL_DEBUG_UART3) or filesystem (getty ttyS2) with most boards.
107 *
108 * UART boot uses UART3 on J9, and the SDP user's guide says to use
109 * that for console. Downsides of using J9: you can't use IRDA too;
110 * since UART3 isn't in the CORE power domain, it may be a bit less
111 * usable in certain PM-sensitive debug scenarios.
112 */
113#undef CONSOLE_J9 /* else J8/UART1 (innermost) */
114
115#ifdef CONSOLE_J9
116#define CONFIG_CONS_INDEX 3
117#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
118#define CONFIG_SERIAL3 3 /* UART3 */
119#else
120#define CONFIG_CONS_INDEX 1
121#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
122#define CONFIG_SERIAL1 1 /* UART1 */
123#endif
124
125#define CONFIG_ENV_OVERWRITE
126#define CONFIG_BAUDRATE 115200
127#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
128 115200}
129
130/*
131 * I2C for power management setup
132 */
133#define CONFIG_HARD_I2C 1
134#define CONFIG_SYS_I2C_SPEED 100000
135#define CONFIG_SYS_I2C_SLAVE 1
136#define CONFIG_SYS_I2C_BUS 0
137#define CONFIG_SYS_I2C_BUS_SELECT 1
138#define CONFIG_DRIVER_OMAP34XX_I2C 1
139
Tom Rixe63e5902009-10-17 12:41:06 -0500140/* OMITTED: single 1 Gbit MT29F1G NAND flash */
141
142/*
143 * NOR boot support - single 1 Gbit PF48F6000M0 Strataflash
144 */
145#define CONFIG_SYS_FLASH_BASE 0x10000000
146#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
147#define CONFIG_SYS_FLASH_CFI 1 /* use CFI geometry data */
148#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* ~10x faster writes */
149#define CONFIG_SYS_FLASH_PROTECTION 1 /* hardware sector protection */
150#define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* flinfo 'E' for empty */
151#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
152#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
153
154#define CONFIG_SYS_FLASH_CFI_WIDTH 2
155#define PHYS_FLASH_SIZE (128 << 20)
156#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors on one chip */
157
Tom Rixe63e5902009-10-17 12:41:06 -0500158/* OMITTED: single 2 Gbit KFM2G16 OneNAND flash */
159
160#define CONFIG_ENV_IS_IN_FLASH 1
161#define CONFIG_SYS_ENV_SECT_SIZE (256 << 10)
162#define CONFIG_ENV_OFFSET CONFIG_SYS_ENV_SECT_SIZE
163#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_ENV_SECT_SIZE)
164/*--------------------------------------------------------------------------*/
165
166/* commands to include */
167#include <config_cmd_default.h>
168
169/* Enabled commands */
170#define CONFIG_CMD_DHCP /* DHCP Support */
171#define CONFIG_CMD_EXT2 /* EXT2 Support */
172#define CONFIG_CMD_FAT /* FAT support */
173#define CONFIG_CMD_I2C /* I2C serial bus support */
174#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
175#define CONFIG_CMD_MMC /* MMC support */
176#define CONFIG_CMD_NET
177
178/* Disabled commands */
179#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
180#undef CONFIG_CMD_IMLS /* List all found images */
181
182/*--------------------------------------------------------------------------*/
183/*
184 * MMC boot support
185 */
186
187#if defined(CONFIG_CMD_MMC)
Tom Rini7cc862b2011-09-03 21:52:21 -0400188#define CONFIG_GENERIC_MMC 1
Tom Rixe63e5902009-10-17 12:41:06 -0500189#define CONFIG_MMC 1
Tom Rini7cc862b2011-09-03 21:52:21 -0400190#define CONFIG_OMAP_HSMMC 1
Tom Rixe63e5902009-10-17 12:41:06 -0500191#define CONFIG_DOS_PARTITION 1
192#endif
193
194/*----------------------------------------------------------------------------
195 * SMSC9115 Ethernet from SMSC9118 family
196 *----------------------------------------------------------------------------
197 */
198#if defined(CONFIG_CMD_NET)
199
Nishanth Menona1725992009-10-16 00:06:36 -0500200#define CONFIG_LAN91C96
Tom Rixe63e5902009-10-17 12:41:06 -0500201#define CONFIG_LAN91C96_BASE DEBUG_BASE
202#define CONFIG_LAN91C96_EXT_PHY
203
204#define CONFIG_BOOTP_SEND_HOSTNAME
205/*
206 * BOOTP fields
207 */
208#define CONFIG_BOOTP_SUBNETMASK 0x00000001
209#define CONFIG_BOOTP_GATEWAY 0x00000002
210#define CONFIG_BOOTP_HOSTNAME 0x00000004
211#define CONFIG_BOOTP_BOOTPATH 0x00000010
212#endif /* (CONFIG_CMD_NET) */
213
214/*
215 * Environment setup
216 *
217 * Default boot order: mmc bootscript, MMC uImage, NOR image.
218 * Network booting environment must be configured at site.
219 */
220
221/* allow overwriting serial config and ethaddr */
222#define CONFIG_ENV_OVERWRITE
223
224#define CONFIG_EXTRA_ENV_SETTINGS \
225 "loadaddr=0x82000000\0" \
226 "console=ttyS0,115200n8\0" \
227 "mmcargs=setenv bootargs console=${console} " \
228 "root=/dev/mmcblk0p2 rw " \
229 "rootfstype=ext3 rootwait\0" \
230 "norargs=setenv bootargs console=${console} " \
231 "root=/dev/mtdblock3 rw " \
232 "rootfstype=jffs2\0" \
233 "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
234 "bootscript=echo Running bootscript from MMC/SD ...; " \
235 "autoscr ${loadaddr}\0" \
236 "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
237 "mmcboot=echo Booting from MMC/SD ...; " \
238 "run mmcargs; " \
239 "bootm ${loadaddr}\0" \
240 "norboot=echo Booting from NOR ...; " \
241 "run norargs; " \
242 "bootm 0x80000\0" \
243
244#define CONFIG_BOOTCOMMAND \
245 "if mmcinit; then " \
246 "if run loadbootscript; then " \
247 "run bootscript; " \
248 "else " \
249 "if run loaduimage; then " \
250 "run mmcboot; " \
251 "else run norboot; " \
252 "fi; " \
253 "fi; " \
254 "else run norboot; fi"
255
256#define CONFIG_AUTO_COMPLETE 1
257
258/*--------------------------------------------------------------------------*/
259
260/*
261 * Miscellaneous configurable options
262 */
Tom Rixe63e5902009-10-17 12:41:06 -0500263
264#define CONFIG_SYS_LONGHELP /* undef to save memory */
265#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
266#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Robert P. J. Day1270ec12009-12-12 12:10:33 -0500267#define CONFIG_SYS_PROMPT "OMAP34XX SDP # "
Vaibhav Hiremathf62b1252011-09-03 21:24:19 -0400268#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
Tom Rixe63e5902009-10-17 12:41:06 -0500269/* Print Buffer Size */
270#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
271 sizeof(CONFIG_SYS_PROMPT) + 16)
272#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
273/* Boot Argument Buffer Size */
274#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
275
276/* SDRAM Test range - start at 16 meg boundary -ends at 32Meg -
277 * a basic sanity check ONLY
278 * IF you would like to increase coverage, increase the end address
279 * or run the test with custom options
280 */
281#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x01000000)
282#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + (32 << 20))
283
284/* Default load address */
285#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0)
286
287/*--------------------------------------------------------------------------*/
288
289/*
290 * 3430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
291 * 32KHz clk, or from external sig. This rate is divided by a local divisor.
292 */
293#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
294#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
295#define CONFIG_SYS_HZ 1000
296
297/*
298 * Stack sizes
299 *
300 * The stack sizes are set up in start.S using the settings below
301 */
302#define CONFIG_STACKSIZE (128 << 10) /* Regular stack */
Tom Rixe63e5902009-10-17 12:41:06 -0500303
Dirk Behme5ec789f2010-11-30 11:10:40 -0500304#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
305#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
306#define CONFIG_SYS_INIT_RAM_SIZE 0x800
307#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
308 CONFIG_SYS_INIT_RAM_SIZE - \
309 GENERATED_GBL_DATA_SIZE)
Tom Rixe63e5902009-10-17 12:41:06 -0500310/*
311 * SDRAM Memory Map
312 */
313#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
314#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
315#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 meg */
316#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
317
Tom Rixe63e5902009-10-17 12:41:06 -0500318/*--------------------------------------------------------------------------*/
319
320/*
321 * NOR FLASH usage ... default nCS0:
322 * - one 256KB sector for U-Boot
323 * - one 256KB sector for its parameters (not all used)
324 * - eight sectors (2 MB) for kernel
325 * - rest for JFFS2
326 */
327
328/* Monitor at start of flash */
329#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
330#define CONFIG_SYS_MONITOR_LEN (256 << 10)
331
Tom Rixe63e5902009-10-17 12:41:06 -0500332/*
333 * NAND FLASH usage ... default nCS1:
334 * - four 128KB sectors for X-Loader
335 * - four 128KB sectors for U-Boot
336 * - two 128KB sector for its parameters
337 * - 32 sectors (4 MB) for kernel
338 * - rest for filesystem
339 */
340
341/*
342 * OneNAND FLASH usage ... default nCS2:
343 * - four 128KB sectors for X-Loader
344 * - two 128KB sectors for U-Boot
345 * - one 128KB sector for its parameters
346 * - sixteen sectors (2 MB) for kernel
347 * - rest for filesystem
348 */
349
Aneesh V8e408522011-11-21 23:38:59 +0000350#define CONFIG_SYS_CACHELINE_SIZE 64
351
Tom Rixe63e5902009-10-17 12:41:06 -0500352#endif /* __CONFIG_H */