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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Alison Wang186fc4d2012-10-18 19:25:52 +00002/*
3 * Configuation settings for the Freescale MCF54418 TWR board.
4 *
5 * Copyright 2010-2012 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
Alison Wang186fc4d2012-10-18 19:25:52 +00007 */
8
9/*
10 * board/config.h - configuration options, board specific
11 */
12
13#ifndef _M54418TWR_H
14#define _M54418TWR_H
15
16/*
17 * High Level Configuration Options
18 * (easy to change)
19 */
Alison Wang186fc4d2012-10-18 19:25:52 +000020
21#define CONFIG_MCFUART
22#define CONFIG_SYS_UART_PORT (0)
Alison Wang186fc4d2012-10-18 19:25:52 +000023#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
24
Angelo Dureghelloc74dda82017-05-14 21:42:27 +020025#define LDS_BOARD_TEXT board/freescale/m54418twr/sbf_dram_init.o (.text*)
26
Alison Wang186fc4d2012-10-18 19:25:52 +000027#undef CONFIG_WATCHDOG
28
29#define CONFIG_TIMESTAMP /* Print image info with timestamp */
30
31/*
32 * BOOTP options
33 */
34#define CONFIG_BOOTP_BOOTFILESIZE
Alison Wang186fc4d2012-10-18 19:25:52 +000035
Alison Wang186fc4d2012-10-18 19:25:52 +000036/*
37 * NAND FLASH
38 */
39#ifdef CONFIG_CMD_NAND
40#define CONFIG_JFFS2_NAND
41#define CONFIG_NAND_FSL_NFC
42#define CONFIG_SYS_NAND_BASE 0xFC0FC000
43#define CONFIG_SYS_MAX_NAND_DEVICE 1
44#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
45#define CONFIG_SYS_NAND_SELECT_DEVICE
Alison Wang186fc4d2012-10-18 19:25:52 +000046#endif
47
48/* Network configuration */
49#define CONFIG_MCFFEC
50#ifdef CONFIG_MCFFEC
Alison Wang186fc4d2012-10-18 19:25:52 +000051#define CONFIG_MII_INIT 1
52#define CONFIG_SYS_DISCOVER_PHY
53#define CONFIG_SYS_RX_ETH_BUFFER 2
Lothar Waßmanne34b9132017-05-18 17:26:58 +020054#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
Alison Wang186fc4d2012-10-18 19:25:52 +000055#define CONFIG_SYS_TX_ETH_BUFFER 2
56#define CONFIG_HAS_ETH1
57
58#define CONFIG_SYS_FEC0_PINMUX 0
59#define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
60#define CONFIG_SYS_FEC1_PINMUX 0
61#define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_MIIBASE
62#define MCFFEC_TOUT_LOOP 50000
63#define CONFIG_SYS_FEC0_PHYADDR 0
64#define CONFIG_SYS_FEC1_PHYADDR 1
65
Alison Wang186fc4d2012-10-18 19:25:52 +000066#define CONFIG_ETHPRIME "FEC0"
67#define CONFIG_IPADDR 192.168.1.2
68#define CONFIG_NETMASK 255.255.255.0
69#define CONFIG_SERVERIP 192.168.1.1
70#define CONFIG_GATEWAYIP 192.168.1.1
71
Alison Wang186fc4d2012-10-18 19:25:52 +000072#define CONFIG_SYS_FEC_BUF_USE_SRAM
73/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
74#ifndef CONFIG_SYS_DISCOVER_PHY
75#define FECDUPLEX FULL
76#define FECSPEED _100BASET
77#define LINKSTATUS 1
78#else
79#define LINKSTATUS 0
80#ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
81#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
82#endif
83#endif /* CONFIG_SYS_DISCOVER_PHY */
84#endif
85
Mario Six5bc05432018-03-28 14:38:20 +020086#define CONFIG_HOSTNAME "M54418TWR"
Alison Wang186fc4d2012-10-18 19:25:52 +000087
88#if defined(CONFIG_CF_SBF)
89/* ST Micro serial flash */
90#define CONFIG_SYS_LOAD_ADDR2 0x40010007
91#define CONFIG_EXTRA_ENV_SETTINGS \
92 "netdev=eth0\0" \
93 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
94 "loadaddr=0x40010000\0" \
95 "sbfhdr=sbfhdr.bin\0" \
96 "uboot=u-boot.bin\0" \
97 "load=tftp ${loadaddr} ${sbfhdr};" \
98 "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \
99 "upd=run load; run prog\0" \
100 "prog=sf probe 0:1 1000000 3;" \
101 "sf erase 0 40000;" \
102 "sf write ${loadaddr} 0 40000;" \
103 "save\0" \
104 ""
105#elif defined(CONFIG_SYS_NAND_BOOT)
106#define CONFIG_EXTRA_ENV_SETTINGS \
107 "netdev=eth0\0" \
108 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
109 "loadaddr=0x40010000\0" \
110 "u-boot=u-boot.bin\0" \
111 "load=tftp ${loadaddr} ${u-boot};\0" \
112 "upd=run load; run prog\0" \
113 "prog=nand device 0;" \
114 "nand erase 0 40000;" \
115 "nb_update ${loadaddr} ${filesize};" \
116 "save\0" \
117 ""
118#else
119#define CONFIG_SYS_UBOOT_END 0x3FFFF
120#define CONFIG_EXTRA_ENV_SETTINGS \
121 "netdev=eth0\0" \
122 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
123 "loadaddr=40010000\0" \
124 "u-boot=u-boot.bin\0" \
125 "load=tftp ${loadaddr) ${u-boot}\0" \
126 "upd=run load; run prog\0" \
127 "prog=prot off mram" " ;" \
128 "cp.b ${loadaddr} 0 ${filesize};" \
129 "save\0" \
130 ""
131#endif
132
133/* Realtime clock */
134#undef CONFIG_MCFRTC
135#define CONFIG_RTC_MCFRRTC
136#define CONFIG_SYS_MCFRRTC_BASE 0xFC0A8000
137
138/* Timer */
139#define CONFIG_MCFTMR
140#undef CONFIG_MCFPIT
141
142/* I2c */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200143#undef CONFIG_SYS_FSL_I2C
Heiko Schocherea818db2013-01-29 08:53:15 +0100144#undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
Alison Wang186fc4d2012-10-18 19:25:52 +0000145/* I2C speed and slave address */
146#define CONFIG_SYS_I2C_SPEED 80000
147#define CONFIG_SYS_I2C_SLAVE 0x7F
148#define CONFIG_SYS_I2C_OFFSET 0x58000
149#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
150
151/* DSPI and Serial Flash */
Alison Wang186fc4d2012-10-18 19:25:52 +0000152#define CONFIG_CF_DSPI
153#define CONFIG_SERIAL_FLASH
Alison Wang186fc4d2012-10-18 19:25:52 +0000154#define CONFIG_SYS_SBFHDR_SIZE 0x7
155#ifdef CONFIG_CMD_SPI
Alison Wang186fc4d2012-10-18 19:25:52 +0000156
157# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \
158 DSPI_CTAR_PCSSCK_1CLK | \
159 DSPI_CTAR_PASC(0) | \
160 DSPI_CTAR_PDT(0) | \
161 DSPI_CTAR_CSSCK(0) | \
162 DSPI_CTAR_ASC(0) | \
163 DSPI_CTAR_DT(1))
164# define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0)
165# define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0)
166#endif
167
168/* Input, PCI, Flexbus, and VCO */
169#define CONFIG_EXTRA_CLOCK
170
171#define CONFIG_PRAM 2048 /* 2048 KB */
172
Alison Wang186fc4d2012-10-18 19:25:52 +0000173#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
174
Alison Wang186fc4d2012-10-18 19:25:52 +0000175#define CONFIG_SYS_MBAR 0xFC000000
176
177/*
178 * Low Level Configuration Settings
179 * (address mappings, register initial values, etc.)
180 * You should know what you are doing if you make changes here.
181 */
182
183/*-----------------------------------------------------------------------
184 * Definitions for initial stack pointer and data area (in DPRAM)
185 */
186#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
187/* End of used area in internal SRAM */
188#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
189#define CONFIG_SYS_INIT_RAM_CTRL 0x221
Alison Wang186fc4d2012-10-18 19:25:52 +0000190#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \
Masahiro Yamada627b73e2014-02-07 09:23:03 +0900191 GENERATED_GBL_DATA_SIZE) - 32)
Alison Wang186fc4d2012-10-18 19:25:52 +0000192#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
193#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
194
195/*-----------------------------------------------------------------------
196 * Start addresses for the final memory configuration
197 * (Set up by the startup code)
198 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
199 */
200#define CONFIG_SYS_SDRAM_BASE 0x40000000
201#define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */
202
203#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x400)
204#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
205#define CONFIG_SYS_DRAM_TEST
206
207#if defined(CONFIG_CF_SBF) || defined(CONFIG_SYS_NAND_BOOT)
208#define CONFIG_SERIAL_BOOT
209#endif
210
211#if defined(CONFIG_SERIAL_BOOT)
Masahiro Yamada61a43922015-12-11 12:22:25 +0900212#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
Alison Wang186fc4d2012-10-18 19:25:52 +0000213#else
214#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
215#endif
216
217#define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024)
218/* Reserve 256 kB for Monitor */
219#define CONFIG_SYS_MONITOR_LEN (256 << 10)
220/* Reserve 256 kB for malloc() */
221#define CONFIG_SYS_MALLOC_LEN (256 << 10)
222
223/*
224 * For booting Linux, the board info and command line data
225 * have to be in the first 8 MB of memory, since this is
226 * the maximum mapped by the Linux kernel during initialization ??
227 */
228/* Initial Memory map for Linux */
229#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \
230 (CONFIG_SYS_SDRAM_SIZE << 20))
231
232/* Configuration for environment
233 * Environment is embedded in u-boot in the second sector of the flash
234 */
235#if !defined(CONFIG_SERIAL_BOOT) /*MRAM boot*/
Alison Wang186fc4d2012-10-18 19:25:52 +0000236#define CONFIG_ENV_ADDR (0x40000 - 0x1000) /*MRAM size 40000*/
237#define CONFIG_ENV_SIZE 0x1000
238#endif
239
240#if defined(CONFIG_CF_SBF)
Alison Wang186fc4d2012-10-18 19:25:52 +0000241#define CONFIG_ENV_OFFSET 0x40000
242#define CONFIG_ENV_SIZE 0x2000
243#define CONFIG_ENV_SECT_SIZE 0x10000
244#endif
245#if defined(CONFIG_SYS_NAND_BOOT)
Alison Wang186fc4d2012-10-18 19:25:52 +0000246#define CONFIG_ENV_OFFSET 0x80000
247#define CONFIG_ENV_SIZE 0x20000
248#define CONFIG_ENV_SECT_SIZE 0x20000
249#endif
250#undef CONFIG_ENV_OVERWRITE
251
252/* FLASH organization */
253#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
254
Alison Wang186fc4d2012-10-18 19:25:52 +0000255#ifdef CONFIG_SYS_FLASH_CFI
256
Alison Wang186fc4d2012-10-18 19:25:52 +0000257/* Max size that the board might have */
258#define CONFIG_SYS_FLASH_SIZE 0x1000000
259#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
260/* max number of memory banks */
261#define CONFIG_SYS_MAX_FLASH_BANKS 1
262/* max number of sectors on one chip */
263#define CONFIG_SYS_MAX_FLASH_SECT 270
264/* "Real" (hardware) sectors protection */
Alison Wang186fc4d2012-10-18 19:25:52 +0000265#define CONFIG_SYS_FLASH_CHECKSUM
266#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE }
267#else
268/* max number of sectors on one chip */
269#define CONFIG_SYS_MAX_FLASH_SECT 270
270/* max number of sectors on one chip */
271#define CONFIG_SYS_MAX_FLASH_BANKS 0
272#endif
273
274/*
275 * This is setting for JFFS2 support in u-boot.
276 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
277 */
278#ifdef CONFIG_CMD_JFFS2
279#define CONFIG_JFFS2_DEV "nand0"
280#define CONFIG_JFFS2_PART_OFFSET (0x800000)
Alison Wang186fc4d2012-10-18 19:25:52 +0000281
282#endif
283
Alison Wang186fc4d2012-10-18 19:25:52 +0000284/* Cache Configuration */
285#define CONFIG_SYS_CACHELINE_SIZE 16
286#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
287 CONFIG_SYS_INIT_RAM_SIZE - 8)
288#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
289 CONFIG_SYS_INIT_RAM_SIZE - 4)
290#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA)
291#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
292#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
293 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
294 CF_ACR_EN | CF_ACR_SM_ALL)
295#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \
296 CF_CACR_ICINVA | CF_CACR_EUSP)
297#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
298 CF_CACR_DEC | CF_CACR_DDCM_P | \
299 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
300
301#define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
302 CONFIG_SYS_INIT_RAM_SIZE - 12)
303
304/*-----------------------------------------------------------------------
305 * Memory bank definitions
306 */
307/*
308 * CS0 - NOR Flash 16MB
309 * CS1 - Available
310 * CS2 - Available
311 * CS3 - Available
312 * CS4 - Available
313 * CS5 - Available
314 */
315
316 /* Flash */
317#define CONFIG_SYS_CS0_BASE 0x00000000
318#define CONFIG_SYS_CS0_MASK 0x000F0101
319#define CONFIG_SYS_CS0_CTRL 0x00001D60
320
321#endif /* _M54418TWR_H */