blob: 47ef6e53eda2b5ae3958073f0135fe8265bfa6b9 [file] [log] [blame]
Bartlomiej Sieka53d4a492007-02-09 10:45:42 +01001/*
2 * (C) Copyright 2003-2007
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * modified for Promess PRO - by Andy Joseph, andy@promessdev.com
6 * modified for Promess PRO-Motion - by Robert McCullough, rob@promessdev.com
7 * modified by Chris M. Tumas 6/20/06 Change CAS latency to 2 from 3
Wolfgang Denk8ed44d92008-10-19 02:35:50 +02008 * Also changed the refresh for 100MHz operation
Bartlomiej Sieka53d4a492007-02-09 10:45:42 +01009 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28
29#include <common.h>
30#include <mpc5xxx.h>
Bartlomiej Siekac00125e2007-05-27 16:58:45 +020031#include <miiphy.h>
Grant Likelycf2817a2007-09-06 09:46:23 -060032#include <libfdt.h>
Bartlomiej Sieka53d4a492007-02-09 10:45:42 +010033
Bartlomiej Siekaa11c0b82007-05-27 16:51:48 +020034#if defined(CONFIG_STATUS_LED)
35#include <status_led.h>
36#endif /* CONFIG_STATUS_LED */
37
Bartlomiej Sieka53d4a492007-02-09 10:45:42 +010038/* Kollmorgen DPR initialization data */
39struct init_elem {
40 unsigned long addr;
41 unsigned len;
42 char *data;
43 } init_seq[] = {
44 {0x500003F2, 2, "\x86\x00"}, /* HW parameter */
45 {0x500003F0, 2, "\x00\x00"},
46 {0x500003EC, 4, "\x00\x80\xc1\x52"}, /* Magic word */
47 };
48
49/*
50 * Initialize Kollmorgen DPR
51 */
52static void kollmorgen_init(void)
53{
54 unsigned i, j;
55 vu_char *p;
56
57 for (i = 0; i < sizeof(init_seq) / sizeof(struct init_elem); ++i) {
58 p = (vu_char *)init_seq[i].addr;
59 for (j = 0; j < init_seq[i].len; ++j)
60 *(p + j) = *(init_seq[i].data + j);
61 }
62
63 printf("DPR: Kollmorgen DPR initialized\n");
64}
65
66
67/*
68 * Early board initalization.
69 */
70int board_early_init_r(void)
71{
72 /* Now, when we are in RAM, disable Boot Chipselect and enable CS0 */
73 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25);
74 *(vu_long *)MPC5XXX_ADDECR |= (1 << 16);
75
76 /* Initialize Kollmorgen DPR */
77 kollmorgen_init();
78
79 return 0;
80}
81
82
Bartlomiej Siekac00125e2007-05-27 16:58:45 +020083/*
84 * Additional PHY intialization. After being reset in mpc5xxx_fec_init_phy(),
85 * PHY goes into FX mode. To take it out of the FX mode and switch into
86 * desired TX operation, one needs to clear the FX_SEL bit of Mode Control
87 * Register.
88 */
89void reset_phy(void)
90{
91 unsigned short mode_control;
92
Heiko Schocher48690d82010-07-20 17:45:02 +020093 miiphy_read("FEC", CONFIG_PHY_ADDR, 0x15, &mode_control);
94 miiphy_write("FEC", CONFIG_PHY_ADDR, 0x15,
Bartlomiej Siekac00125e2007-05-27 16:58:45 +020095 mode_control & 0xfffe);
96 return;
97}
98
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099#ifndef CONFIG_SYS_RAMBOOT
Bartlomiej Sieka53d4a492007-02-09 10:45:42 +0100100/*
101 * Helper function to initialize SDRAM controller.
102 */
Bartlomiej Sieka70492882007-05-27 17:26:46 +0200103static void sdram_start(int hi_addr)
Bartlomiej Sieka53d4a492007-02-09 10:45:42 +0100104{
105 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
106
107 /* unlock mode register */
108 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 |
109 hi_addr_bit;
110
111 /* precharge all banks */
112 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
113 hi_addr_bit;
114
115 /* auto refresh */
116 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
117 hi_addr_bit;
118
119 /* auto refresh, second time */
120 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
121 hi_addr_bit;
122
123 /* set mode register */
124 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
125
126 /* normal operation */
127 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
128}
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200129#endif /* !CONFIG_SYS_RAMBOOT */
Bartlomiej Sieka53d4a492007-02-09 10:45:42 +0100130
131
132/*
133 * Initalize SDRAM - configure SDRAM controller, detect memory size.
134 */
Becky Bruce9973e3c2008-06-09 16:03:40 -0500135phys_size_t initdram(int board_type)
Bartlomiej Sieka53d4a492007-02-09 10:45:42 +0100136{
137 ulong dramsize = 0;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138#ifndef CONFIG_SYS_RAMBOOT
Bartlomiej Sieka53d4a492007-02-09 10:45:42 +0100139 ulong test1, test2;
140
Bartlomiej Siekaeff50192007-10-23 11:36:07 +0200141 /* According to AN3221 (MPC5200B SDRAM Initialization and
142 * Configuration), the SDelay register must be written a value of
143 * 0x00000004 as the first step of the SDRAM contorller configuration.
144 */
145 *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
146
Bartlomiej Sieka53d4a492007-02-09 10:45:42 +0100147 /* configure SDRAM start/end for detection */
148 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */
149 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */
150
151 /* setup config registers */
152 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
153 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
154
155 sdram_start(0);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156 test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
Bartlomiej Sieka53d4a492007-02-09 10:45:42 +0100157 sdram_start(1);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158 test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
Bartlomiej Sieka53d4a492007-02-09 10:45:42 +0100159 if (test1 > test2) {
160 sdram_start(0);
161 dramsize = test1;
162 } else {
163 dramsize = test2;
164 }
165
166 /* memory smaller than 1MB is impossible */
167 if (dramsize < (1 << 20))
168 dramsize = 0;
169
170 /* set SDRAM CS0 size according to the amount of RAM found */
Wolfgang Denk74357112007-02-27 14:26:04 +0100171 if (dramsize > 0) {
Bartlomiej Sieka53d4a492007-02-09 10:45:42 +0100172 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
173 __builtin_ffs(dramsize >> 20) - 1;
Wolfgang Denk74357112007-02-27 14:26:04 +0100174 } else {
Bartlomiej Sieka53d4a492007-02-09 10:45:42 +0100175 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
Wolfgang Denk74357112007-02-27 14:26:04 +0100176 }
Bartlomiej Sieka53d4a492007-02-09 10:45:42 +0100177
178 /* let SDRAM CS1 start right after CS0 and disable it */
179 *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize;
180
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#else /* !CONFIG_SYS_RAMBOOT */
Bartlomiej Sieka53d4a492007-02-09 10:45:42 +0100182 /* retrieve size of memory connected to SDRAM CS0 */
183 dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
184 if (dramsize >= 0x13)
185 dramsize = (1 << (dramsize - 0x13)) << 20;
186 else
187 dramsize = 0;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#endif /* CONFIG_SYS_RAMBOOT */
Bartlomiej Sieka53d4a492007-02-09 10:45:42 +0100189
190 /* return total ram size */
191 return dramsize;
192}
193
194
Bartlomiej Sieka70492882007-05-27 17:26:46 +0200195int checkboard(void)
Bartlomiej Sieka53d4a492007-02-09 10:45:42 +0100196{
Bartlomiej Siekac75e6392007-05-27 16:55:23 +0200197 uchar rev = *(vu_char *)CPLD_REV_REGISTER;
198 printf("Board: Promess Motion-PRO board (CPLD rev. 0x%02x)\n", rev);
Bartlomiej Sieka53d4a492007-02-09 10:45:42 +0100199 return 0;
200}
Bartlomiej Sieka1f1369c2007-05-08 09:21:57 +0200201
202
Grant Likelycf2817a2007-09-06 09:46:23 -0600203#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
Bartlomiej Sieka1f1369c2007-05-08 09:21:57 +0200204void ft_board_setup(void *blob, bd_t *bd)
205{
206 ft_cpu_setup(blob, bd);
207}
Grant Likelycf2817a2007-09-06 09:46:23 -0600208#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
Bartlomiej Siekaa11c0b82007-05-27 16:51:48 +0200209
210
211#if defined(CONFIG_STATUS_LED)
Bartlomiej Sieka70492882007-05-27 17:26:46 +0200212void __led_init(led_id_t regaddr, int state)
Bartlomiej Siekaa11c0b82007-05-27 16:51:48 +0200213{
214 *((vu_long *) regaddr) |= ENABLE_GPIO_OUT;
215
216 if (state == STATUS_LED_ON)
217 *((vu_long *) regaddr) |= LED_ON;
218 else
219 *((vu_long *) regaddr) &= ~LED_ON;
220}
221
Bartlomiej Sieka70492882007-05-27 17:26:46 +0200222void __led_set(led_id_t regaddr, int state)
Bartlomiej Siekaa11c0b82007-05-27 16:51:48 +0200223{
224 if (state == STATUS_LED_ON)
225 *((vu_long *) regaddr) |= LED_ON;
226 else
227 *((vu_long *) regaddr) &= ~LED_ON;
228}
229
Bartlomiej Sieka70492882007-05-27 17:26:46 +0200230void __led_toggle(led_id_t regaddr)
Bartlomiej Siekaa11c0b82007-05-27 16:51:48 +0200231{
232 *((vu_long *) regaddr) ^= LED_ON;
233}
234#endif /* CONFIG_STATUS_LED */