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wdenkc6097192002-11-03 00:24:07 +00001/*
2 * Cirrus Logic CS8900A Ethernet
3 *
wdenk6069ff22003-02-28 00:49:47 +00004 * (C) 2003 Wolfgang Denk, wd@denx.de
5 * Extension to synchronize ethaddr environment variable
6 * against value in EEPROM
7 *
wdenkc6097192002-11-03 00:24:07 +00008 * (C) Copyright 2002
9 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
10 * Marius Groeger <mgroeger@sysgo.de>
11 *
12 * Copyright (C) 1999 Ben Williamson <benw@pobox.com>
13 *
14 * See file CREDITS for list of people who contributed to this
15 * project.
16 *
17 * This program is loaded into SRAM in bootstrap mode, where it waits
18 * for commands on UART1 to read and write memory, jump to code etc.
19 * A design goal for this program is to be entirely independent of the
20 * target board. Anything with a CL-PS7111 or EP7211 should be able to run
21 * this code in bootstrap mode. All the board specifics can be handled on
22 * the host.
23 *
24 * This program is free software; you can redistribute it and/or modify
25 * it under the terms of the GNU General Public License as published by
26 * the Free Software Foundation; either version 2 of the License, or
27 * (at your option) any later version.
28 *
29 * This program is distributed in the hope that it will be useful,
30 * but WITHOUT ANY WARRANTY; without even the implied warranty of
31 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
32 * GNU General Public License for more details.
33 *
34 * You should have received a copy of the GNU General Public License
35 * along with this program; if not, write to the Free Software
36 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
37 */
38
39#include <common.h>
40#include <command.h>
41#include "cs8900.h"
42#include <net.h>
43
wdenka2663ea2003-12-07 18:32:37 +000044#undef DEBUG
wdenkc6097192002-11-03 00:24:07 +000045
46/* packet page register access functions */
47
48#ifdef CS8900_BUS32
49/* we don't need 16 bit initialisation on 32 bit bus */
50#define get_reg_init_bus(x) get_reg((x))
51#else
wdenk6069ff22003-02-28 00:49:47 +000052static unsigned short get_reg_init_bus (int regno)
wdenkc6097192002-11-03 00:24:07 +000053{
wdenk6069ff22003-02-28 00:49:47 +000054 /* force 16 bit busmode */
55 volatile unsigned char c;
wdenkc6097192002-11-03 00:24:07 +000056
wdenk6069ff22003-02-28 00:49:47 +000057 c = CS8900_BUS16_0;
58 c = CS8900_BUS16_1;
59 c = CS8900_BUS16_0;
60 c = CS8900_BUS16_1;
61 c = CS8900_BUS16_0;
62
63 CS8900_PPTR = regno;
Guennadi Liakhovetski13e0b8f2008-04-03 13:36:18 +020064 return CS8900_PDATA;
wdenkc6097192002-11-03 00:24:07 +000065}
66#endif
67
wdenk6069ff22003-02-28 00:49:47 +000068static unsigned short get_reg (int regno)
wdenkc6097192002-11-03 00:24:07 +000069{
wdenk6069ff22003-02-28 00:49:47 +000070 CS8900_PPTR = regno;
Guennadi Liakhovetski13e0b8f2008-04-03 13:36:18 +020071 return CS8900_PDATA;
wdenkc6097192002-11-03 00:24:07 +000072}
73
74
wdenk6069ff22003-02-28 00:49:47 +000075static void put_reg (int regno, unsigned short val)
wdenkc6097192002-11-03 00:24:07 +000076{
wdenk6069ff22003-02-28 00:49:47 +000077 CS8900_PPTR = regno;
78 CS8900_PDATA = val;
wdenkc6097192002-11-03 00:24:07 +000079}
80
wdenk6069ff22003-02-28 00:49:47 +000081static void eth_reset (void)
wdenkc6097192002-11-03 00:24:07 +000082{
wdenk6069ff22003-02-28 00:49:47 +000083 int tmo;
84 unsigned short us;
wdenkc6097192002-11-03 00:24:07 +000085
wdenk6069ff22003-02-28 00:49:47 +000086 /* reset NIC */
87 put_reg (PP_SelfCTL, get_reg (PP_SelfCTL) | PP_SelfCTL_Reset);
wdenkc6097192002-11-03 00:24:07 +000088
wdenk6069ff22003-02-28 00:49:47 +000089 /* wait for 200ms */
90 udelay (200000);
91 /* Wait until the chip is reset */
wdenkc6097192002-11-03 00:24:07 +000092
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020093 tmo = get_timer (0) + 1 * CONFIG_SYS_HZ;
wdenk6069ff22003-02-28 00:49:47 +000094 while ((((us = get_reg_init_bus (PP_SelfSTAT)) & PP_SelfSTAT_InitD) == 0)
95 && tmo < get_timer (0))
96 /*NOP*/;
wdenkc6097192002-11-03 00:24:07 +000097}
98
wdenka2663ea2003-12-07 18:32:37 +000099static void eth_reginit (void)
100{
101 /* receive only error free packets addressed to this card */
102 put_reg (PP_RxCTL, PP_RxCTL_IA | PP_RxCTL_Broadcast | PP_RxCTL_RxOK);
103 /* do not generate any interrupts on receive operations */
104 put_reg (PP_RxCFG, 0);
105 /* do not generate any interrupts on transmit operations */
106 put_reg (PP_TxCFG, 0);
107 /* do not generate any interrupts on buffer operations */
108 put_reg (PP_BufCFG, 0);
109 /* enable transmitter/receiver mode */
110 put_reg (PP_LineCTL, PP_LineCTL_Rx | PP_LineCTL_Tx);
111}
112
Mike Frysinger0a5238c2009-02-11 19:06:09 -0500113void cs8900_get_enetaddr (void)
wdenkc6097192002-11-03 00:24:07 +0000114{
wdenk6069ff22003-02-28 00:49:47 +0000115 int i;
Mike Frysinger0a5238c2009-02-11 19:06:09 -0500116 uchar enetaddr[6];
wdenk6069ff22003-02-28 00:49:47 +0000117
Mike Frysinger0a5238c2009-02-11 19:06:09 -0500118 /* if the env is setup, then bail */
119 if (eth_getenv_enetaddr("ethaddr", enetaddr))
120 return;
wdenk6069ff22003-02-28 00:49:47 +0000121
122 /* verify chip id */
123 if (get_reg_init_bus (PP_ChipID) != 0x630e)
124 return;
125 eth_reset ();
Guennadi Liakhovetski13e0b8f2008-04-03 13:36:18 +0200126 if ((get_reg (PP_SelfSTAT) & (PP_SelfSTAT_EEPROM | PP_SelfSTAT_EEPROM_OK)) ==
wdenk6069ff22003-02-28 00:49:47 +0000127 (PP_SelfSTAT_EEPROM | PP_SelfSTAT_EEPROM_OK)) {
128
129 /* Load the MAC from EEPROM */
130 for (i = 0; i < 6 / 2; i++) {
131 unsigned int Addr;
132
133 Addr = get_reg (PP_IA + i * 2);
Mike Frysinger0a5238c2009-02-11 19:06:09 -0500134 enetaddr[i * 2] = Addr & 0xFF;
135 enetaddr[i * 2 + 1] = Addr >> 8;
wdenk6069ff22003-02-28 00:49:47 +0000136 }
137
Mike Frysinger0a5238c2009-02-11 19:06:09 -0500138 eth_setenv_enetaddr("ethaddr", enetaddr);
139 debug("### Set environment from HW MAC addr = \"%pM\"\n", enetaddr);
wdenk6069ff22003-02-28 00:49:47 +0000140 }
wdenkc6097192002-11-03 00:24:07 +0000141}
142
wdenk6069ff22003-02-28 00:49:47 +0000143void eth_halt (void)
wdenkc6097192002-11-03 00:24:07 +0000144{
wdenk6069ff22003-02-28 00:49:47 +0000145 /* disable transmitter/receiver mode */
146 put_reg (PP_LineCTL, 0);
wdenkc6097192002-11-03 00:24:07 +0000147
wdenk6069ff22003-02-28 00:49:47 +0000148 /* "shutdown" to show ChipID or kernel wouldn't find he cs8900 ... */
149 get_reg_init_bus (PP_ChipID);
wdenkc6097192002-11-03 00:24:07 +0000150}
151
wdenk6069ff22003-02-28 00:49:47 +0000152int eth_init (bd_t * bd)
wdenkc6097192002-11-03 00:24:07 +0000153{
Ladislav Michlfd88d912009-03-23 18:16:34 +0100154 uchar enetaddr[6];
Mike Frysinger0a5238c2009-02-11 19:06:09 -0500155
wdenk6069ff22003-02-28 00:49:47 +0000156 /* verify chip id */
157 if (get_reg_init_bus (PP_ChipID) != 0x630e) {
158 printf ("CS8900 Ethernet chip not found?!\n");
159 return 0;
160 }
161
162 eth_reset ();
163 /* set the ethernet address */
Mike Frysinger0a5238c2009-02-11 19:06:09 -0500164 eth_getenv_enetaddr("ethaddr", enetaddr);
165 put_reg (PP_IA + 0, enetaddr[0] | (enetaddr[1] << 8));
166 put_reg (PP_IA + 2, enetaddr[2] | (enetaddr[3] << 8));
167 put_reg (PP_IA + 4, enetaddr[4] | (enetaddr[5] << 8));
wdenk6069ff22003-02-28 00:49:47 +0000168
wdenka2663ea2003-12-07 18:32:37 +0000169 eth_reginit ();
wdenkc6097192002-11-03 00:24:07 +0000170 return 0;
wdenkc6097192002-11-03 00:24:07 +0000171}
172
173/* Get a data block via Ethernet */
Guennadi Liakhovetski13e0b8f2008-04-03 13:36:18 +0200174int eth_rx (void)
wdenkc6097192002-11-03 00:24:07 +0000175{
wdenk6069ff22003-02-28 00:49:47 +0000176 int i;
177 unsigned short rxlen;
178 unsigned short *addr;
179 unsigned short status;
wdenkc6097192002-11-03 00:24:07 +0000180
wdenk6069ff22003-02-28 00:49:47 +0000181 status = get_reg (PP_RER);
wdenkc6097192002-11-03 00:24:07 +0000182
wdenk6069ff22003-02-28 00:49:47 +0000183 if ((status & PP_RER_RxOK) == 0)
184 return 0;
wdenkc6097192002-11-03 00:24:07 +0000185
wdenk6069ff22003-02-28 00:49:47 +0000186 status = CS8900_RTDATA; /* stat */
187 rxlen = CS8900_RTDATA; /* len */
wdenkc6097192002-11-03 00:24:07 +0000188
wdenka2663ea2003-12-07 18:32:37 +0000189#ifdef DEBUG
wdenk6069ff22003-02-28 00:49:47 +0000190 if (rxlen > PKTSIZE_ALIGN + PKTALIGN)
191 printf ("packet too big!\n");
wdenka2663ea2003-12-07 18:32:37 +0000192#endif
wdenk6069ff22003-02-28 00:49:47 +0000193 for (addr = (unsigned short *) NetRxPackets[0], i = rxlen >> 1; i > 0;
194 i--)
195 *addr++ = CS8900_RTDATA;
196 if (rxlen & 1)
197 *addr++ = CS8900_RTDATA;
wdenkc6097192002-11-03 00:24:07 +0000198
wdenk6069ff22003-02-28 00:49:47 +0000199 /* Pass the packet up to the protocol layers. */
200 NetReceive (NetRxPackets[0], rxlen);
wdenkc6097192002-11-03 00:24:07 +0000201
wdenk6069ff22003-02-28 00:49:47 +0000202 return rxlen;
wdenkc6097192002-11-03 00:24:07 +0000203}
204
205/* Send a data block via Ethernet. */
Guennadi Liakhovetski13e0b8f2008-04-03 13:36:18 +0200206int eth_send (volatile void *packet, int length)
wdenkc6097192002-11-03 00:24:07 +0000207{
wdenk6069ff22003-02-28 00:49:47 +0000208 volatile unsigned short *addr;
209 int tmo;
210 unsigned short s;
wdenkc6097192002-11-03 00:24:07 +0000211
212retry:
wdenk6069ff22003-02-28 00:49:47 +0000213 /* initiate a transmit sequence */
214 CS8900_TxCMD = PP_TxCmd_TxStart_Full;
215 CS8900_TxLEN = length;
wdenkc6097192002-11-03 00:24:07 +0000216
wdenk6069ff22003-02-28 00:49:47 +0000217 /* Test to see if the chip has allocated memory for the packet */
218 if ((get_reg (PP_BusSTAT) & PP_BusSTAT_TxRDY) == 0) {
219 /* Oops... this should not happen! */
wdenka2663ea2003-12-07 18:32:37 +0000220#ifdef DEBUG
wdenk6069ff22003-02-28 00:49:47 +0000221 printf ("cs: unable to send packet; retrying...\n");
wdenka2663ea2003-12-07 18:32:37 +0000222#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223 for (tmo = get_timer (0) + 5 * CONFIG_SYS_HZ; get_timer (0) < tmo;)
wdenk6069ff22003-02-28 00:49:47 +0000224 /*NOP*/;
225 eth_reset ();
wdenka2663ea2003-12-07 18:32:37 +0000226 eth_reginit ();
wdenk6069ff22003-02-28 00:49:47 +0000227 goto retry;
228 }
wdenkc6097192002-11-03 00:24:07 +0000229
wdenk6069ff22003-02-28 00:49:47 +0000230 /* Write the contents of the packet */
231 /* assume even number of bytes */
232 for (addr = packet; length > 0; length -= 2)
233 CS8900_RTDATA = *addr++;
wdenkc6097192002-11-03 00:24:07 +0000234
wdenk6069ff22003-02-28 00:49:47 +0000235 /* wait for transfer to succeed */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200236 tmo = get_timer (0) + 5 * CONFIG_SYS_HZ;
wdenk6069ff22003-02-28 00:49:47 +0000237 while ((s = get_reg (PP_TER) & ~0x1F) == 0) {
238 if (get_timer (0) >= tmo)
239 break;
240 }
wdenkc6097192002-11-03 00:24:07 +0000241
wdenk6069ff22003-02-28 00:49:47 +0000242 /* nothing */ ;
243 if ((s & (PP_TER_CRS | PP_TER_TxOK)) != PP_TER_TxOK) {
wdenka2663ea2003-12-07 18:32:37 +0000244#ifdef DEBUG
wdenk6069ff22003-02-28 00:49:47 +0000245 printf ("\ntransmission error %#x\n", s);
wdenka2663ea2003-12-07 18:32:37 +0000246#endif
wdenk6069ff22003-02-28 00:49:47 +0000247 }
wdenkc6097192002-11-03 00:24:07 +0000248
wdenk6069ff22003-02-28 00:49:47 +0000249 return 0;
wdenkc6097192002-11-03 00:24:07 +0000250}
251
wdenk1cb8e982003-03-06 21:55:29 +0000252static void cs8900_e2prom_ready(void)
253{
Guennadi Liakhovetski13e0b8f2008-04-03 13:36:18 +0200254 while (get_reg(PP_SelfSTAT) & SI_BUSY)
255 ;
wdenk1cb8e982003-03-06 21:55:29 +0000256}
257
258/***********************************************************/
259/* read a 16-bit word out of the EEPROM */
260/***********************************************************/
261
262int cs8900_e2prom_read(unsigned char addr, unsigned short *value)
263{
264 cs8900_e2prom_ready();
265 put_reg(PP_EECMD, EEPROM_READ_CMD | addr);
266 cs8900_e2prom_ready();
267 *value = get_reg(PP_EEData);
268
269 return 0;
270}
271
272
273/***********************************************************/
274/* write a 16-bit word into the EEPROM */
275/***********************************************************/
276
wdenk06d01db2003-03-14 20:47:52 +0000277int cs8900_e2prom_write(unsigned char addr, unsigned short value)
wdenk1cb8e982003-03-06 21:55:29 +0000278{
279 cs8900_e2prom_ready();
280 put_reg(PP_EECMD, EEPROM_WRITE_EN);
281 cs8900_e2prom_ready();
282 put_reg(PP_EEData, value);
283 put_reg(PP_EECMD, EEPROM_WRITE_CMD | addr);
284 cs8900_e2prom_ready();
285 put_reg(PP_EECMD, EEPROM_WRITE_DIS);
286 cs8900_e2prom_ready();
287
wdenk06d01db2003-03-14 20:47:52 +0000288 return 0;
wdenk1cb8e982003-03-06 21:55:29 +0000289}