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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 3a473b2a6523db9cdf2b5aed22d9730b4ebc5693 / . / board / Marvell / include / pci.h
blob: 167248db1e411e26a88c86811a6a62ba05b5f537 [file] [log] [blame]
wdenk3a473b22004-01-03 00:43:19 +0000[diff] [blame^]1/* PCI.h - PCI functions header file */
2
3/* Copyright - Galileo technology. */
4
5#ifndef __INCpcih
6#define __INCpcih
7
8/* includes */
9
10#include"core.h"
11#include"memory.h"
12
13/* According to PCI REV 2.1 MAX agents allowed on the bus are -21- */
14#define PCI_MAX_DEVICES 22
15
16
17/* Macros */
18
19/* The next Macros configurate the initiator board (SELF) or any any agent on
20 the PCI to become: MASTER, response to MEMORY transactions , response to
21 IO transactions or TWO both MEMORY_IO transactions. Those configuration
22 are for both PCI0 and PCI1. */
23
24#define PCI_MEMORY_ENABLE(host, deviceNumber) pciWriteConfigReg(host, \
25 PCI_STATUS_AND_COMMAND,deviceNumber,MEMORY_ENABLE | \
26 pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber) )
27
28#define PCI_IO_ENABLE(host, deviceNumber) pciWriteConfigReg(host, \
29 PCI_STATUS_AND_COMMAND,deviceNumber,I_O_ENABLE | \
30 pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber) )
31
32#define PCI_SLAVE_ENABLE(host, deviceNumber) pciWriteConfigReg(host, \
33 PCI_STATUS_AND_COMMAND,deviceNumber,MEMORY_ENABLE | I_O_ENABLE | \
34 pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber) )
35
36#define PCI_DISABLE(host, deviceNumber) pciWriteConfigReg(host, \
37 PCI_STATUS_AND_COMMAND,deviceNumber,0xfffffff8 & \
38 pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber))
39
40#define PCI_MASTER_ENABLE(host,deviceNumber) pciWriteConfigReg(host, \
41 PCI_STATUS_AND_COMMAND,deviceNumber,MASTER_ENABLE | \
42 pciReadConfigReg(host,PCI_STATUS_AND_COMMAND,deviceNumber) )
43
44#define PCI_MASTER_DISABLE(deviceNumber) pciWriteConfigReg(host, \
45 PCI_STATUS_AND_COMMAND,deviceNumber,~MASTER_ENABLE & \
46 pciReadConfigReg(host,PCI_STATUS_AND_COMMAND,deviceNumber) )
47
48#define MASTER_ENABLE BIT2
49#define MEMORY_ENABLE BIT1
50#define I_O_ENABLE BIT0
51#define SELF 32
52
53/* Agent on the PCI bus may have up to 6 BARS. */
54#define BAR0 0x10
55#define BAR1 0x14
56#define BAR2 0x18
57#define BAR3 0x1c
58#define BAR4 0x20
59#define BAR5 0x24
60#define BAR_SEL_MEM_IO BIT0
61#define BAR_MEM_TYPE_32_BIT NO_BIT
62#define BAR_MEM_TYPE_BELOW_1M BIT1
63#define BAR_MEM_TYPE_64_BIT BIT2
64#define BAR_MEM_TYPE_RESERVED (BIT1 | BIT2)
65#define BAR_MEM_TYPE_MASK (BIT1 | BIT2)
66#define BAR_PREFETCHABLE BIT3
67#define BAR_CONFIG_MASK (BIT0 | BIT1 | BIT2 | BIT3)
68
69/* Defines for the access regions. */
70#define PREFETCH_ENABLE BIT12
71#define PREFETCH_DISABLE NO_BIT
72#define DELAYED_READ_ENABLE BIT13
73/* #define CACHING_ENABLE BIT14 */
74/* aggressive prefetch: PCI slave prefetch two burst in advance*/
75#define AGGRESSIVE_PREFETCH BIT16
76/* read line aggresive prefetch: PCI slave prefetch two burst in advance*/
77#define READ_LINE_AGGRESSIVE_PREFETCH BIT17
78/* read multiple aggresive prefetch: PCI slave prefetch two burst in advance*/
79#define READ_MULTI_AGGRESSIVE_PREFETCH BIT18
80#define MAX_BURST_4 NO_BIT
81#define MAX_BURST_8 BIT20 /* Bits[21:20] = 01 */
82#define MAX_BURST_16 BIT21 /* Bits[21:20] = 10 */
83#define PCI_BYTE_SWAP NO_BIT /* Bits[25:24] = 00 */
84#define PCI_NO_SWAP BIT24 /* Bits[25:24] = 01 */
85#define PCI_BYTE_AND_WORD_SWAP BIT25 /* Bits[25:24] = 10 */
86#define PCI_WORD_SWAP (BIT24 | BIT25) /* Bits[25:24] = 11 */
87#define PCI_ACCESS_PROTECT BIT28
88#define PCI_WRITE_PROTECT BIT29
89
90/* typedefs */
91
92typedef enum __pciAccessRegions{REGION0,REGION1,REGION2,REGION3,REGION4,REGION5,
93 REGION6,REGION7} PCI_ACCESS_REGIONS;
94
95typedef enum __pciAgentPrio{LOW_AGENT_PRIO,HI_AGENT_PRIO} PCI_AGENT_PRIO;
96typedef enum __pciAgentPark{PARK_ON_AGENT,DONT_PARK_ON_AGENT} PCI_AGENT_PARK;
97
98typedef enum __pciSnoopType{PCI_NO_SNOOP,PCI_SNOOP_WT,PCI_SNOOP_WB}
99 PCI_SNOOP_TYPE;
100typedef enum __pciSnoopRegion{PCI_SNOOP_REGION0,PCI_SNOOP_REGION1,
101 PCI_SNOOP_REGION2,PCI_SNOOP_REGION3}
102 PCI_SNOOP_REGION;
103
104typedef enum __memPciHost{PCI_HOST0,PCI_HOST1} PCI_HOST;
105typedef enum __memPciRegion{PCI_REGION0,PCI_REGION1,
106 PCI_REGION2,PCI_REGION3,
107 PCI_IO}
108 PCI_REGION;
109
110/*ronen 7/Dec/03 */
111typedef enum __pci_bar_windows{PCI_CS0_BAR, PCI_CS1_BAR, PCI_CS2_BAR,
112 PCI_CS3_BAR, PCI_DEV_CS0_BAR, PCI_DEV_CS1_BAR,
113 PCI_DEV_CS2_BAR, PCI_DEV_CS3_BAR, PCI_BOOT_CS_BAR,
114 PCI_MEM_INT_REG_BAR, PCI_IO_INT_REG_BAR,
115 PCI_P2P_MEM0_BAR, PCI_P2P_MEM1_BAR,
116 PCI_P2P_IO_BAR, PCI_CPU_BAR, PCI_INT_SRAM_BAR,
117 PCI_LAST_BAR} PCI_INTERNAL_BAR;
118
119typedef struct pciBar {
120 unsigned int detectBase;
121 unsigned int base;
122 unsigned int size;
123 unsigned int type;
124} PCI_BAR;
125
126typedef struct pciDevice {
127 PCI_HOST host;
128 char type[40];
129 unsigned int deviceNum;
130 unsigned int venID;
131 unsigned int deviceID;
132 PCI_BAR bar[6];
133} PCI_DEVICE;
134
135typedef struct pciSelfBars {
136 unsigned int SCS0Base;
137 unsigned int SCS0Size;
138 unsigned int SCS1Base;
139 unsigned int SCS1Size;
140 unsigned int SCS2Base;
141 unsigned int SCS2Size;
142 unsigned int SCS3Base;
143 unsigned int SCS3Size;
144 unsigned int internalMemBase;
145 unsigned int internalIOBase;
146 unsigned int CS0Base;
147 unsigned int CS0Size;
148 unsigned int CS1Base;
149 unsigned int CS1Size;
150 unsigned int CS2Base;
151 unsigned int CS2Size;
152 unsigned int CS3Base;
153 unsigned int CS3Size;
154 unsigned int CSBootBase;
155 unsigned int CSBootSize;
156 unsigned int P2PMem0Base;
157 unsigned int P2PMem0Size;
158 unsigned int P2PMem1Base;
159 unsigned int P2PMem1Size;
160 unsigned int P2PIOBase;
161 unsigned int P2PIOSize;
162 unsigned int CPUBase;
163 unsigned int CPUSize;
164} PCI_SELF_BARS;
165
166/* read/write configuration registers on local PCI bus. */
167void pciWriteConfigReg(PCI_HOST host, unsigned int regOffset,
168 unsigned int pciDevNum, unsigned int data);
169unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset,
170 unsigned int pciDevNum);
171
172/* read/write configuration registers on another PCI bus. */
173void pciOverBridgeWriteConfigReg(PCI_HOST host,
174 unsigned int regOffset,
175 unsigned int pciDevNum,
176 unsigned int busNum,unsigned int data);
177unsigned int pciOverBridgeReadConfigReg(PCI_HOST host,
178 unsigned int regOffset,
179 unsigned int pciDevNum,
180 unsigned int busNum);
181
182/* Performs full scane on both PCI and returns all detail possible on the
183 agents which exist on the bus. */
184void pciScanDevices(PCI_HOST host, PCI_DEVICE *pci0Detect,
185 unsigned int numberOfElment);
186
187/* Master`s memory space */
188bool pciMapSpace(PCI_HOST host, PCI_REGION region,
189 unsigned int remapBase,
190 unsigned int deviceBase,
191 unsigned int deviceLength);
192unsigned int pciGetSpaceBase(PCI_HOST host, PCI_REGION region);
193unsigned int pciGetSpaceSize(PCI_HOST host, PCI_REGION region);
194
195/* Slave`s memory space */
196void pciMapMemoryBank(PCI_HOST host, MEMORY_BANK bank,
197 unsigned int pci0Dram0Base, unsigned int pci0Dram0Size);
198
199#if 0 /* GARBAGE routines - dont use till they get cleaned up */
200void pci0ScanSelfBars(PCI_SELF_BARS *pci0SelfBars);
201void pci1ScanSelfBars(PCI_SELF_BARS *pci1SelfBars);
202void pci0MapInternalRegSpace(unsigned int pci0InternalBase);
203void pci1MapInternalRegSpace(unsigned int pci1InternalBase);
204void pci0MapInternalRegIOSpace(unsigned int pci0InternalBase);
205void pci1MapInternalRegIOSpace(unsigned int pci1InternalBase);
206void pci0MapDevice0MemorySpace(unsigned int pci0Dev0Base,
207 unsigned int pci0Dev0Length);
208void pci1MapDevice0MemorySpace(unsigned int pci1Dev0Base,
209 unsigned int pci1Dev0Length);
210void pci0MapDevice1MemorySpace(unsigned int pci0Dev1Base,
211 unsigned int pci0Dev1Length);
212void pci1MapDevice1MemorySpace(unsigned int pci1Dev1Base,
213 unsigned int pci1Dev1Length);
214void pci0MapDevice2MemorySpace(unsigned int pci0Dev2Base,
215 unsigned int pci0Dev2Length);
216void pci1MapDevice2MemorySpace(unsigned int pci1Dev2Base,
217 unsigned int pci1Dev2Length);
218void pci0MapDevice3MemorySpace(unsigned int pci0Dev3Base,
219 unsigned int pci0Dev3Length);
220void pci1MapDevice3MemorySpace(unsigned int pci1Dev3Base,
221 unsigned int pci1Dev3Length);
222void pci0MapBootDeviceMemorySpace(unsigned int pci0DevBootBase,
223 unsigned int pci0DevBootLength);
224void pci1MapBootDeviceMemorySpace(unsigned int pci1DevBootBase,
225 unsigned int pci1DevBootLength);
226void pci0MapP2pMem0Space(unsigned int pci0P2pMem0Base,
227 unsigned int pci0P2pMem0Length);
228void pci1MapP2pMem0Space(unsigned int pci1P2pMem0Base,
229 unsigned int pci1P2pMem0Length);
230void pci0MapP2pMem1Space(unsigned int pci0P2pMem1Base,
231 unsigned int pci0P2pMem1Length);
232void pci1MapP2pMem1Space(unsigned int pci1P2pMem1Base,
233 unsigned int pci1P2pMem1Length);
234void pci0MapP2pIoSpace(unsigned int pci0P2pIoBase,
235 unsigned int pci0P2pIoLength);
236void pci1MapP2pIoSpace(unsigned int pci1P2pIoBase,
237 unsigned int pci1P2pIoLength);
238
239void pci0MapCPUspace(unsigned int pci0CpuBase, unsigned int pci0CpuLengs);
240void pci1MapCPUspace(unsigned int pci1CpuBase, unsigned int pci1CpuLengs);
241#endif
242
243/* PCI region options */
244
245bool pciSetRegionFeatures(PCI_HOST host, PCI_ACCESS_REGIONS region,
246 unsigned int features, unsigned int baseAddress,
247 unsigned int regionLength);
248
249void pciDisableAccessRegion(PCI_HOST host, PCI_ACCESS_REGIONS region);
250
251/* PCI arbiter */
252
253bool pciArbiterEnable(PCI_HOST host);
254bool pciArbiterDisable(PCI_HOST host);
255bool pciSetArbiterAgentsPriority(PCI_HOST host, PCI_AGENT_PRIO internalAgent,
256 PCI_AGENT_PRIO externalAgent0,
257 PCI_AGENT_PRIO externalAgent1,
258 PCI_AGENT_PRIO externalAgent2,
259 PCI_AGENT_PRIO externalAgent3,
260 PCI_AGENT_PRIO externalAgent4,
261 PCI_AGENT_PRIO externalAgent5);
262bool pciSetArbiterAgentsPriority(PCI_HOST host, PCI_AGENT_PRIO internalAgent,
263 PCI_AGENT_PRIO externalAgent0,
264 PCI_AGENT_PRIO externalAgent1,
265 PCI_AGENT_PRIO externalAgent2,
266 PCI_AGENT_PRIO externalAgent3,
267 PCI_AGENT_PRIO externalAgent4,
268 PCI_AGENT_PRIO externalAgent5);
269bool pciParkingDisable(PCI_HOST host, PCI_AGENT_PARK internalAgent,
270 PCI_AGENT_PARK externalAgent0,
271 PCI_AGENT_PARK externalAgent1,
272 PCI_AGENT_PARK externalAgent2,
273 PCI_AGENT_PARK externalAgent3,
274 PCI_AGENT_PARK externalAgent4,
275 PCI_AGENT_PARK externalAgent5);
276bool pciEnableBrokenAgentDetection(PCI_HOST host, unsigned char brokenValue);
277bool pciEnableBrokenAgentDetection(PCI_HOST host, unsigned char brokenValue);
278
279/* PCI-to-PCI (P2P) */
280
281bool pciP2PConfig(PCI_HOST host,
282 unsigned int SecondBusLow,unsigned int SecondBusHigh,
283 unsigned int busNum,unsigned int devNum);
284/* PCI Cache-coherency */
285
286bool pciSetRegionSnoopMode(PCI_HOST host, PCI_SNOOP_REGION region,
287 PCI_SNOOP_TYPE snoopType,
288 unsigned int baseAddress,
289 unsigned int regionLength);
290
291PCI_DEVICE * pciFindDevice(unsigned short ven, unsigned short dev);
292
293#endif /* __INCpcih */