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Marc Zyngierecf07a72014-07-12 14:24:04 +01001/*
2 * Copyright (C) 2013 - ARM Ltd
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#ifndef __ARM_PSCI_H__
19#define __ARM_PSCI_H__
20
Simon Glassc3dc39a2020-05-10 11:39:55 -060021#ifndef __ASSEMBLY__
22#include <linux/bitops.h>
23#endif
24
Marek Vasut46dcb312022-12-22 01:46:34 +010025#define ARM_PSCI_VER_1_1 (0x00010001)
Hou Zhiqiang2c774162016-07-29 18:26:36 +080026#define ARM_PSCI_VER_1_0 (0x00010000)
27#define ARM_PSCI_VER_0_2 (0x00000002)
28
Beniamino Galvani5a07abb2016-05-08 08:30:14 +020029/* PSCI 0.1 interface */
Marc Zyngierecf07a72014-07-12 14:24:04 +010030#define ARM_PSCI_FN_BASE 0x95c1ba5e
31#define ARM_PSCI_FN(n) (ARM_PSCI_FN_BASE + (n))
32
33#define ARM_PSCI_FN_CPU_SUSPEND ARM_PSCI_FN(0)
34#define ARM_PSCI_FN_CPU_OFF ARM_PSCI_FN(1)
35#define ARM_PSCI_FN_CPU_ON ARM_PSCI_FN(2)
36#define ARM_PSCI_FN_MIGRATE ARM_PSCI_FN(3)
37
38#define ARM_PSCI_RET_SUCCESS 0
39#define ARM_PSCI_RET_NI (-1)
40#define ARM_PSCI_RET_INVAL (-2)
41#define ARM_PSCI_RET_DENIED (-3)
Hongbo Zhang116339d2016-07-21 18:09:36 +080042#define ARM_PSCI_RET_ALREADY_ON (-4)
43#define ARM_PSCI_RET_ON_PENDING (-5)
44#define ARM_PSCI_RET_INTERNAL_FAILURE (-6)
45#define ARM_PSCI_RET_NOT_PRESENT (-7)
46#define ARM_PSCI_RET_DISABLED (-8)
47#define ARM_PSCI_RET_INVALID_ADDRESS (-9)
Marc Zyngierecf07a72014-07-12 14:24:04 +010048
Beniamino Galvani5a07abb2016-05-08 08:30:14 +020049/* PSCI 0.2 interface */
50#define ARM_PSCI_0_2_FN_BASE 0x84000000
51#define ARM_PSCI_0_2_FN(n) (ARM_PSCI_0_2_FN_BASE + (n))
52
macro.wave.z@gmail.com14bf25d2016-12-08 11:58:24 +080053#define ARM_PSCI_0_2_FN64_BASE 0xC4000000
54#define ARM_PSCI_0_2_FN64(n) (ARM_PSCI_0_2_FN64_BASE + (n))
55
Beniamino Galvani5a07abb2016-05-08 08:30:14 +020056#define ARM_PSCI_0_2_FN_PSCI_VERSION ARM_PSCI_0_2_FN(0)
57#define ARM_PSCI_0_2_FN_CPU_SUSPEND ARM_PSCI_0_2_FN(1)
58#define ARM_PSCI_0_2_FN_CPU_OFF ARM_PSCI_0_2_FN(2)
59#define ARM_PSCI_0_2_FN_CPU_ON ARM_PSCI_0_2_FN(3)
60#define ARM_PSCI_0_2_FN_AFFINITY_INFO ARM_PSCI_0_2_FN(4)
61#define ARM_PSCI_0_2_FN_MIGRATE ARM_PSCI_0_2_FN(5)
62#define ARM_PSCI_0_2_FN_MIGRATE_INFO_TYPE ARM_PSCI_0_2_FN(6)
63#define ARM_PSCI_0_2_FN_MIGRATE_INFO_UP_CPU ARM_PSCI_0_2_FN(7)
64#define ARM_PSCI_0_2_FN_SYSTEM_OFF ARM_PSCI_0_2_FN(8)
65#define ARM_PSCI_0_2_FN_SYSTEM_RESET ARM_PSCI_0_2_FN(9)
66
macro.wave.z@gmail.com14bf25d2016-12-08 11:58:24 +080067#define ARM_PSCI_0_2_FN64_CPU_SUSPEND ARM_PSCI_0_2_FN64(1)
68#define ARM_PSCI_0_2_FN64_CPU_ON ARM_PSCI_0_2_FN64(3)
69#define ARM_PSCI_0_2_FN64_AFFINITY_INFO ARM_PSCI_0_2_FN64(4)
70#define ARM_PSCI_0_2_FN64_MIGRATE ARM_PSCI_0_2_FN64(5)
71#define ARM_PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU ARM_PSCI_0_2_FN64(7)
72
Hongbo Zhang116339d2016-07-21 18:09:36 +080073/* PSCI 1.0 interface */
74#define ARM_PSCI_1_0_FN_PSCI_FEATURES ARM_PSCI_0_2_FN(10)
75#define ARM_PSCI_1_0_FN_CPU_FREEZE ARM_PSCI_0_2_FN(11)
76#define ARM_PSCI_1_0_FN_CPU_DEFAULT_SUSPEND ARM_PSCI_0_2_FN(12)
77#define ARM_PSCI_1_0_FN_NODE_HW_STATE ARM_PSCI_0_2_FN(13)
78#define ARM_PSCI_1_0_FN_SYSTEM_SUSPEND ARM_PSCI_0_2_FN(14)
79#define ARM_PSCI_1_0_FN_SET_SUSPEND_MODE ARM_PSCI_0_2_FN(15)
80#define ARM_PSCI_1_0_FN_STAT_RESIDENCY ARM_PSCI_0_2_FN(16)
81#define ARM_PSCI_1_0_FN_STAT_COUNT ARM_PSCI_0_2_FN(17)
82
macro.wave.z@gmail.com14bf25d2016-12-08 11:58:24 +080083#define ARM_PSCI_1_0_FN64_CPU_DEFAULT_SUSPEND ARM_PSCI_0_2_FN64(12)
84#define ARM_PSCI_1_0_FN64_NODE_HW_STATE ARM_PSCI_0_2_FN64(13)
85#define ARM_PSCI_1_0_FN64_SYSTEM_SUSPEND ARM_PSCI_0_2_FN64(14)
86#define ARM_PSCI_1_0_FN64_STAT_RESIDENCY ARM_PSCI_0_2_FN64(16)
87#define ARM_PSCI_1_0_FN64_STAT_COUNT ARM_PSCI_0_2_FN64(17)
88
Marek Vasut11a1a3b2022-12-22 01:46:35 +010089/* PSCI 1.1 interface */
90#define ARM_PSCI_1_1_FN64_SYSTEM_RESET2 ARM_PSCI_0_2_FN64(18)
91
Chen-Yu Tsai980d6a52016-06-19 12:38:36 +080092/* 1KB stack per core */
93#define ARM_PSCI_STACK_SHIFT 10
94#define ARM_PSCI_STACK_SIZE (1 << ARM_PSCI_STACK_SHIFT)
95
Hongbo Zhang7e742c22016-07-21 18:09:37 +080096/* PSCI affinity level state returned by AFFINITY_INFO */
97#define PSCI_AFFINITY_LEVEL_ON 0
98#define PSCI_AFFINITY_LEVEL_OFF 1
99#define PSCI_AFFINITY_LEVEL_ON_PENDING 2
100
Rajesh Ravi41acbc52019-11-22 14:50:01 -0800101#define PSCI_RESET2_TYPE_VENDOR_SHIFT 31
102#define PSCI_RESET2_TYPE_VENDOR BIT(PSCI_RESET2_TYPE_VENDOR_SHIFT)
103
Tom Rinidd09f7e2015-03-05 20:19:36 -0500104#ifndef __ASSEMBLY__
Chen-Yu Tsaicbeeb2a2016-06-07 10:54:26 +0800105#include <asm/types.h>
Simon Glasscd93d622020-05-10 11:40:13 -0600106#include <linux/bitops.h>
Chen-Yu Tsaicbeeb2a2016-06-07 10:54:26 +0800107
Patrick Delaunay9ce751a2018-04-16 10:15:12 +0200108/* These 3 helper functions assume cpu < CONFIG_ARMV7_PSCI_NR_CPUS */
Chen-Yu Tsai45c334e2016-07-05 21:45:07 +0800109u32 psci_get_target_pc(int cpu);
Patrick Delaunay1a047c22018-04-16 10:13:22 +0200110u32 psci_get_context_id(int cpu);
Patrick Delaunay1a047c22018-04-16 10:13:22 +0200111void psci_save(int cpu, u32 pc, u32 context_id);
Chen-Yu Tsai45c334e2016-07-05 21:45:07 +0800112
Chen-Yu Tsaicbeeb2a2016-06-07 10:54:26 +0800113void psci_cpu_entry(void);
114u32 psci_get_cpu_id(void);
Chen-Yu Tsaicbeeb2a2016-06-07 10:54:26 +0800115void psci_cpu_off_common(void);
116
Tom Rinidd09f7e2015-03-05 20:19:36 -0500117int psci_update_dt(void *fdt);
Jan Kiszkace416fa2015-04-21 07:18:34 +0200118void psci_board_init(void);
Hou Zhiqiang45684ae2016-06-28 20:18:16 +0800119int fdt_psci(void *fdt);
Hongbo Zhangd38def12016-08-19 17:20:30 +0800120
121void psci_v7_flush_dcache_all(void);
Tom Rinidd09f7e2015-03-05 20:19:36 -0500122#endif /* ! __ASSEMBLY__ */
123
Marc Zyngierecf07a72014-07-12 14:24:04 +0100124#endif /* __ARM_PSCI_H__ */