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Jon Loeliger0cde4b02007-04-11 16:50:57 -05001/*
2 * Copyright 2007 Freescale Semiconductor, Inc.
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23/*
24 * mpc8544ds board configuration file
25 *
26 */
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
30/* High Level Configuration Options */
31#define CONFIG_BOOKE 1 /* BOOKE */
32#define CONFIG_E500 1 /* BOOKE e500 family */
33#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
34#define CONFIG_MPC8544 1
35#define CONFIG_MPC8544DS 1
36
Wolfgang Denk2ae18242010-10-06 09:05:45 +020037#ifndef CONFIG_SYS_TEXT_BASE
38#define CONFIG_SYS_TEXT_BASE 0xfff80000
39#endif
40
Ed Swarthout837f1ba2007-07-27 01:50:51 -050041#define CONFIG_PCI 1 /* Enable PCI/PCIE */
42#define CONFIG_PCI1 1 /* PCI controller 1 */
43#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
44#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
45#define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */
46#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
Kumar Gala8ff3de62007-12-07 12:17:34 -060047#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
Kumar Gala0151cba2008-10-21 11:33:58 -050048#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
Jon Loeliger0cde4b02007-04-11 16:50:57 -050049
Kumar Gala4bcae9c2008-01-16 01:16:16 -060050#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
Roy Zangf6155c62009-07-09 10:05:48 +080051#define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/
Kumar Gala4bcae9c2008-01-16 01:16:16 -060052
Ed Swarthout837f1ba2007-07-27 01:50:51 -050053#define CONFIG_TSEC_ENET /* tsec ethernet support */
Jon Loeliger0cde4b02007-04-11 16:50:57 -050054#define CONFIG_ENV_OVERWRITE
Ed Swarthout837f1ba2007-07-27 01:50:51 -050055#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
Jon Loeliger0cde4b02007-04-11 16:50:57 -050056
Jon Loeliger0cde4b02007-04-11 16:50:57 -050057#ifndef __ASSEMBLY__
58extern unsigned long get_board_sys_clk(unsigned long dummy);
59#endif
60#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
61
62/*
63 * These can be toggled for performance analysis, otherwise use default.
64 */
Ed Swarthout837f1ba2007-07-27 01:50:51 -050065#define CONFIG_L2_CACHE /* toggle L2 cache */
Jon Loeliger0cde4b02007-04-11 16:50:57 -050066#define CONFIG_BTB /* toggle branch predition */
Jon Loeliger0cde4b02007-04-11 16:50:57 -050067
68/*
69 * Only possible on E500 Version 2 or newer cores.
70 */
71#define CONFIG_ENABLE_36BIT_PHYS 1
72
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020073#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
74#define CONFIG_SYS_MEMTEST_END 0x00400000
Ed Swarthout837f1ba2007-07-27 01:50:51 -050075#define CONFIG_PANIC_HANG /* do not reset board on panic */
Jon Loeliger0cde4b02007-04-11 16:50:57 -050076
77/*
78 * Base addresses -- Note these are effective addresses where the
79 * actual resources get mapped (not physical addresses)
80 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020081#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
82#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
83#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
84#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
Jon Loeliger0cde4b02007-04-11 16:50:57 -050085
Kumar Gala1167a2f2008-08-26 08:02:30 -050086/* DDR Setup */
87#define CONFIG_FSL_DDR2
88#undef CONFIG_FSL_DDR_INTERACTIVE
89#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
90#define CONFIG_DDR_SPD
Jon Loeliger0cde4b02007-04-11 16:50:57 -050091
Dave Liu9b0ad1b2008-10-28 17:53:38 +080092#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
Kumar Gala1167a2f2008-08-26 08:02:30 -050093#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
94
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020095#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
96#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Kumar Gala1167a2f2008-08-26 08:02:30 -050097#define CONFIG_VERY_BIG_RAM
98
99#define CONFIG_NUM_DDR_CONTROLLERS 1
100#define CONFIG_DIMM_SLOTS_PER_CTLR 1
101#define CONFIG_CHIP_SELECTS_PER_CTRL 2
102
103/* I2C addresses of SPD EEPROMs */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500104#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
105
Kumar Gala1167a2f2008-08-26 08:02:30 -0500106/* Make sure required options are set */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500107#ifndef CONFIG_SPD_EEPROM
108#error ("CONFIG_SPD_EEPROM is required")
109#endif
110
111#undef CONFIG_CLOCKS_IN_MHZ
112
113/*
114 * Memory map
115 *
116 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
117 *
118 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
119 *
120 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
121 *
122 * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable
123 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
124 *
125 * Localbus cacheable
126 *
127 * 0xf000_0000 0xf3ff_ffff SDRAM 64M Cacheable
128 * 0xf401_0000 0xf401_3fff L1 for stack 4K Cacheable TLB0
129 *
130 * Localbus non-cacheable
131 *
132 * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M non-cacheable
133 * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable
134 * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable
135 *
136 */
137
138/*
139 * Local Bus Definitions
140 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#define CONFIG_SYS_BOOT_BLOCK 0xfc000000 /* boot TLB */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500142
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH 8M */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500144
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200145#define CONFIG_SYS_BR0_PRELIM 0xff801001
146#define CONFIG_SYS_BR1_PRELIM 0xfe801001
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500147
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_OR0_PRELIM 0xff806e65
149#define CONFIG_SYS_OR1_PRELIM 0xff806e65
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500150
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200151#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500152
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153#define CONFIG_SYS_FLASH_QUIET_TEST
154#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
155#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
156#undef CONFIG_SYS_FLASH_CHECKSUM
157#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
158#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Kumar Gala81e56e92008-06-09 18:55:38 -0500159#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500160
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200161#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500162
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200163#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#define CONFIG_SYS_FLASH_CFI
165#define CONFIG_SYS_FLASH_EMPTY_INFO
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500166
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#define CONFIG_SYS_LBC_NONCACHE_BASE 0xf8000000
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500168
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169#define CONFIG_SYS_BR2_PRELIM 0xf8201001 /* port size 16bit */
170#define CONFIG_SYS_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500171
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200172#define CONFIG_SYS_BR3_PRELIM 0xf8100801 /* port size 8bit */
173#define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500174
Kim Phillips7608d752007-08-21 17:00:17 -0500175#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500176#define PIXIS_BASE 0xf8100000 /* PIXIS registers */
177#define PIXIS_ID 0x0 /* Board ID at offset 0 */
178#define PIXIS_VER 0x1 /* Board version at offset 1 */
179#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
180#define PIXIS_RST 0x4 /* PIXIS Reset Control register */
181#define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch
182 * register */
183#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
184#define PIXIS_VCTL 0x10 /* VELA Control Register */
185#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
186#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
187#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
Kumar Gala6bb5b412009-07-14 22:42:01 -0500188#define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */
189#define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500190#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
191#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
192#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
193#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
Andy Fleming5a8a1632008-08-31 16:33:30 -0500194#define PIXIS_VSPEED2 0x1d /* VELA VSpeed 2 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195#define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/
Andy Fleming5a8a1632008-08-31 16:33:30 -0500196#define PIXIS_VSPEED2_TSEC1SER 0x2
197#define PIXIS_VSPEED2_TSEC3SER 0x1
198#define PIXIS_VCFGEN1_TSEC1SER 0x20
199#define PIXIS_VCFGEN1_TSEC3SER 0x40
Liu Yubff188b2008-10-10 11:40:58 +0800200#define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER|PIXIS_VSPEED2_TSEC3SER)
201#define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER|PIXIS_VCFGEN1_TSEC3SER)
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500202
203
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204#define CONFIG_SYS_INIT_RAM_LOCK 1
205#define CONFIG_SYS_INIT_RAM_ADDR 0xf4010000 /* Initial L1 address */
206#define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500207
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500208
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
210#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
211#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500212
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
214#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500215
216/* Serial Port - controlled on board with jumper J8
217 * open - index 2
218 * shorted - index 1
219 */
220#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#define CONFIG_SYS_NS16550
222#define CONFIG_SYS_NS16550_SERIAL
223#define CONFIG_SYS_NS16550_REG_SIZE 1
224#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500225
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226#define CONFIG_SYS_BAUDRATE_TABLE \
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500227 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
228
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
230#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500231
232/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#define CONFIG_SYS_HUSH_PARSER
234#ifdef CONFIG_SYS_HUSH_PARSER
235#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500236#endif
237
238/* pass open firmware flat tree */
Kumar Galaaddce572007-11-26 17:12:24 -0600239#define CONFIG_OF_LIBFDT 1
240#define CONFIG_OF_BOARD_SETUP 1
241#define CONFIG_OF_STDOUT_VIA_ALIAS 1
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500242
243/* I2C */
244#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
245#define CONFIG_HARD_I2C /* I2C with hardware support */
246#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200247#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
248#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
249#define CONFIG_SYS_I2C_SLAVE 0x7F
250#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
251#define CONFIG_SYS_I2C_OFFSET 0x3100
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500252
253/*
254 * General PCI
255 * Memory space is mapped 1-1, but I/O space must start from 0.
256 */
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600257#define CONFIG_SYS_PCIE_VIRT 0x80000000 /* 1G PCIE TLB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200258#define CONFIG_SYS_PCIE_PHYS 0x80000000 /* 1G PCIE TLB */
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600259#define CONFIG_SYS_PCI_VIRT 0xc0000000 /* 512M PCI TLB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200260#define CONFIG_SYS_PCI_PHYS 0xc0000000 /* 512M PCI TLB */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500261
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600262#define CONFIG_SYS_PCI1_MEM_VIRT 0xc0000000
Kumar Gala10795f42008-12-02 16:08:36 -0600263#define CONFIG_SYS_PCI1_MEM_BUS 0xc0000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600264#define CONFIG_SYS_PCI1_MEM_PHYS 0xc0000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200265#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600266#define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600267#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200268#define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000
269#define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500270
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500271/* controller 2, Slot 1, tgtid 1, Base address 9000 */
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600272#define CONFIG_SYS_PCIE2_MEM_VIRT 0x80000000
Kumar Gala10795f42008-12-02 16:08:36 -0600273#define CONFIG_SYS_PCIE2_MEM_BUS 0x80000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600274#define CONFIG_SYS_PCIE2_MEM_PHYS 0x80000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200275#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600276#define CONFIG_SYS_PCIE2_IO_VIRT 0xe1010000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600277#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200278#define CONFIG_SYS_PCIE2_IO_PHYS 0xe1010000
279#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500280
281/* controller 1, Slot 2,tgtid 2, Base address a000 */
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600282#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
Kumar Gala10795f42008-12-02 16:08:36 -0600283#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600284#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200285#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600286#define CONFIG_SYS_PCIE1_IO_VIRT 0xe1020000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600287#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200288#define CONFIG_SYS_PCIE1_IO_PHYS 0xe1020000
289#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500290
291/* controller 3, direct to uli, tgtid 3, Base address b000 */
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600292#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
Kumar Gala10795f42008-12-02 16:08:36 -0600293#define CONFIG_SYS_PCIE3_MEM_BUS 0xb0000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600294#define CONFIG_SYS_PCIE3_MEM_PHYS 0xb0000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200295#define CONFIG_SYS_PCIE3_MEM_SIZE 0x00100000 /* 1M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600296#define CONFIG_SYS_PCIE3_IO_VIRT 0xb0100000 /* reuse mem LAW */
Kumar Gala5f91ef62008-12-02 16:08:37 -0600297#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200298#define CONFIG_SYS_PCIE3_IO_PHYS 0xb0100000 /* reuse mem LAW */
299#define CONFIG_SYS_PCIE3_IO_SIZE 0x00100000 /* 1M */
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600300#define CONFIG_SYS_PCIE3_MEM_VIRT2 0xb0200000
Kumar Gala10795f42008-12-02 16:08:36 -0600301#define CONFIG_SYS_PCIE3_MEM_BUS2 0xb0200000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600302#define CONFIG_SYS_PCIE3_MEM_PHYS2 0xb0200000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200303#define CONFIG_SYS_PCIE3_MEM_SIZE2 0x00200000 /* 1M */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500304
305#if defined(CONFIG_PCI)
306
Kumar Gala630d9bf2008-07-14 14:07:03 -0500307/*PCIE video card used*/
Kumar Galaaca5f012008-12-02 16:08:40 -0600308#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT
Kumar Gala630d9bf2008-07-14 14:07:03 -0500309
310/*PCI video card used*/
Kumar Galaaca5f012008-12-02 16:08:40 -0600311/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/
Kumar Gala630d9bf2008-07-14 14:07:03 -0500312
313/* video */
314#define CONFIG_VIDEO
315
316#if defined(CONFIG_VIDEO)
317#define CONFIG_BIOSEMU
318#define CONFIG_CFB_CONSOLE
319#define CONFIG_VIDEO_SW_CURSOR
320#define CONFIG_VGA_AS_SINGLE_DEVICE
321#define CONFIG_ATI_RADEON_FB
322#define CONFIG_VIDEO_LOGO
323/*#define CONFIG_CONSOLE_CURSOR*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200324#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
Kumar Gala630d9bf2008-07-14 14:07:03 -0500325#endif
326
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500327#define CONFIG_NET_MULTI
328#define CONFIG_PCI_PNP /* do pci plug-and-play */
329
330#undef CONFIG_EEPRO100
331#undef CONFIG_TULIP
332#define CONFIG_RTL8139
333
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500334#ifndef CONFIG_PCI_PNP
Kumar Gala5f91ef62008-12-02 16:08:37 -0600335 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS
336 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500337 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
338#endif
339
340#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
341#define CONFIG_DOS_PARTITION
342#define CONFIG_SCSI_AHCI
343
344#ifdef CONFIG_SCSI_AHCI
345#define CONFIG_SATA_ULI5288
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200346#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
347#define CONFIG_SYS_SCSI_MAX_LUN 1
348#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
349#define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500350#endif /* SCSCI */
351
352#endif /* CONFIG_PCI */
353
354
355#if defined(CONFIG_TSEC_ENET)
356
357#ifndef CONFIG_NET_MULTI
Ed Swarthout837f1ba2007-07-27 01:50:51 -0500358#define CONFIG_NET_MULTI 1
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500359#endif
360
361#define CONFIG_MII 1 /* MII PHY management */
362#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
Kim Phillips255a35772007-05-16 16:52:19 -0500363#define CONFIG_TSEC1 1
364#define CONFIG_TSEC1_NAME "eTSEC1"
365#define CONFIG_TSEC3 1
366#define CONFIG_TSEC3_NAME "eTSEC3"
Ed Swarthout837f1ba2007-07-27 01:50:51 -0500367
Liu Yubff188b2008-10-10 11:40:58 +0800368#define CONFIG_PIXIS_SGMII_CMD
Andy Fleming652f7c22008-08-31 16:33:28 -0500369#define CONFIG_FSL_SGMII_RISER 1
370#define SGMII_RISER_PHY_OFFSET 0x1c
371
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500372#define TSEC1_PHY_ADDR 0
373#define TSEC3_PHY_ADDR 1
374
Andy Fleming3a790132007-08-15 20:03:25 -0500375#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
376#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
377
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500378#define TSEC1_PHYIDX 0
379#define TSEC3_PHYIDX 0
380
381#define CONFIG_ETHPRIME "eTSEC1"
382
383#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500384#endif /* CONFIG_TSEC_ENET */
385
386/*
387 * Environment
388 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200389#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200390#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200391#define CONFIG_ENV_ADDR 0xfff80000
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500392#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200393#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x70000)
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500394#endif
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200395#define CONFIG_ENV_SIZE 0x2000
396#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500397
398#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200399#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500400
Jon Loeliger2835e512007-06-13 13:22:08 -0500401/*
Jon Loeliger659e2f62007-07-10 09:10:49 -0500402 * BOOTP options
403 */
404#define CONFIG_BOOTP_BOOTFILESIZE
405#define CONFIG_BOOTP_BOOTPATH
406#define CONFIG_BOOTP_GATEWAY
407#define CONFIG_BOOTP_HOSTNAME
408
409
410/*
Jon Loeliger2835e512007-06-13 13:22:08 -0500411 * Command line configuration.
412 */
413#include <config_cmd_default.h>
414
415#define CONFIG_CMD_PING
416#define CONFIG_CMD_I2C
417#define CONFIG_CMD_MII
Kumar Gala82ac8c92007-12-07 12:04:30 -0600418#define CONFIG_CMD_ELF
Kumar Gala1c9aa762008-09-22 23:40:42 -0500419#define CONFIG_CMD_IRQ
420#define CONFIG_CMD_SETEXPR
Becky Bruce199e2622010-06-17 11:37:25 -0500421#define CONFIG_CMD_REGINFO
Jon Loeliger2835e512007-06-13 13:22:08 -0500422
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500423#if defined(CONFIG_PCI)
Jon Loeliger2835e512007-06-13 13:22:08 -0500424 #define CONFIG_CMD_PCI
Jon Loeliger2835e512007-06-13 13:22:08 -0500425 #define CONFIG_CMD_NET
Ed Swarthout837f1ba2007-07-27 01:50:51 -0500426 #define CONFIG_CMD_SCSI
427 #define CONFIG_CMD_EXT2
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500428#endif
Jon Loeliger2835e512007-06-13 13:22:08 -0500429
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500430
431#undef CONFIG_WATCHDOG /* watchdog disabled */
432
433/*
434 * Miscellaneous configurable options
435 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200436#define CONFIG_SYS_LONGHELP /* undef to save memory */
Kim Phillips5be58f52010-07-14 19:47:18 -0500437#define CONFIG_CMDLINE_EDITING /* Command-line editing */
438#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200439#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
440#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger2835e512007-06-13 13:22:08 -0500441#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200442#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500443#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200444#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500445#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200446#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
447#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
448#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
449#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500450
451/*
452 * For booting Linux, the board info and command line data
Kumar Gala89188a62009-07-15 08:54:50 -0500453 * have to be in the first 16 MB of memory, since this is
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500454 * the maximum mapped by the Linux kernel during initialization.
455 */
Kumar Gala89188a62009-07-15 08:54:50 -0500456#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500457
Jon Loeliger2835e512007-06-13 13:22:08 -0500458#if defined(CONFIG_CMD_KGDB)
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500459#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
460#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
461#endif
462
463/*
464 * Environment Configuration
465 */
466
467/* The mac addresses for all ethernet interface */
468#if defined(CONFIG_TSEC_ENET)
Kumar Galaea5877e2007-08-16 11:01:21 -0500469#define CONFIG_HAS_ETH0
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500470#define CONFIG_ETHADDR 00:E0:0C:02:00:FD
471#define CONFIG_HAS_ETH1
472#define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500473#endif
474
475#define CONFIG_IPADDR 192.168.1.251
476
477#define CONFIG_HOSTNAME 8544ds_unknown
478#define CONFIG_ROOTPATH /nfs/mpc85xx
Ed Swarthout837f1ba2007-07-27 01:50:51 -0500479#define CONFIG_BOOTFILE 8544ds/uImage.uboot
480#define CONFIG_UBOOTPATH 8544ds/u-boot.bin /* TFTP server */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500481
Kumar Gala50c03c82007-11-27 22:42:34 -0600482#define CONFIG_SERVERIP 192.168.1.1
483#define CONFIG_GATEWAYIP 192.168.1.1
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500484#define CONFIG_NETMASK 255.255.0.0
485
486#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
487
488#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
Ed Swarthout837f1ba2007-07-27 01:50:51 -0500489#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500490
491#define CONFIG_BAUDRATE 115200
492
Ed Swarthout837f1ba2007-07-27 01:50:51 -0500493#define CONFIG_EXTRA_ENV_SETTINGS \
494 "netdev=eth0\0" \
495 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
496 "tftpflash=tftpboot $loadaddr $uboot; " \
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200497 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
498 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
499 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
500 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
501 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500502 "consoledev=ttyS0\0" \
503 "ramdiskaddr=2000000\0" \
Ed Swarthout837f1ba2007-07-27 01:50:51 -0500504 "ramdiskfile=8544ds/ramdisk.uboot\0" \
Kumar Gala50c03c82007-11-27 22:42:34 -0600505 "fdtaddr=c00000\0" \
506 "fdtfile=8544ds/mpc8544ds.dtb\0" \
507 "bdev=sda3\0"
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500508
509#define CONFIG_NFSBOOTCOMMAND \
510 "setenv bootargs root=/dev/nfs rw " \
511 "nfsroot=$serverip:$rootpath " \
512 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
513 "console=$consoledev,$baudrate $othbootargs;" \
514 "tftp $loadaddr $bootfile;" \
Kumar Gala50c03c82007-11-27 22:42:34 -0600515 "tftp $fdtaddr $fdtfile;" \
516 "bootm $loadaddr - $fdtaddr"
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500517
Ed Swarthout837f1ba2007-07-27 01:50:51 -0500518#define CONFIG_RAMBOOTCOMMAND \
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500519 "setenv bootargs root=/dev/ram rw " \
520 "console=$consoledev,$baudrate $othbootargs;" \
521 "tftp $ramdiskaddr $ramdiskfile;" \
522 "tftp $loadaddr $bootfile;" \
Kumar Gala50c03c82007-11-27 22:42:34 -0600523 "tftp $fdtaddr $fdtfile;" \
524 "bootm $loadaddr $ramdiskaddr $fdtaddr"
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500525
Ed Swarthout837f1ba2007-07-27 01:50:51 -0500526#define CONFIG_BOOTCOMMAND \
527 "setenv bootargs root=/dev/$bdev rw " \
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500528 "console=$consoledev,$baudrate $othbootargs;" \
529 "tftp $loadaddr $bootfile;" \
Kumar Gala50c03c82007-11-27 22:42:34 -0600530 "tftp $fdtaddr $fdtfile;" \
531 "bootm $loadaddr - $fdtaddr"
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500532
533#endif /* __CONFIG_H */